From 7321000b5feef91a88fc8b78c125ae8944e06053 Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Tue, 28 Sep 2021 14:41:55 -0700 Subject: [PATCH] dt-bindings: Add bindings for multi channel llcc and cinder llcc Add bindings for cinder llcc node and descriptions for additional nodes needed to support mulitple channel configurations in llcc. Change-Id: I5fa54bfe79379e12140bcc25316a5b55632efbfc --- bindings/arm/msm/qcom,llcc.txt | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/bindings/arm/msm/qcom,llcc.txt b/bindings/arm/msm/qcom,llcc.txt index 8b9b975c..b213ddbe 100644 --- a/bindings/arm/msm/qcom,llcc.txt +++ b/bindings/arm/msm/qcom,llcc.txt @@ -14,7 +14,7 @@ Properties: Definition: must be "qcom,sdm845-llcc" or "qcom,lahaina-llcc" or "qcom,shima-llcc" or "qcom,waipio-llcc" or "qcom,sdxlemur-llcc" or "qcom,diwali-llcc" - or "qcom,kalama-llcc". + or "qcom,kalama-llcc" or "qcom,cinder-llcc". "qcom,llcc-v2" must be appended for V2 hardware or "qcom,llcc-v21" for V2.1 or "qcom,llcc-v41" for V4.1. @@ -24,17 +24,32 @@ Properties: Definition: The first element specifies the llcc base start address and the size of the register region. The second element specifies the llcc broadcast base address and size of the register region. + The third element is optional and specifies the feature register + used to decide which llcc configuration to use if multiple are + available. - reg-names: Usage: required Value Type: Definition: Register region names. Must be "llcc_base", "llcc_broadcast_base". + The third element is needed only if multiple llcc configurations + are available and must be "multi_ch_reg". - interrupts: Usage: required Definition: The interrupt is associated with the llcc edac device. It's used for llcc cache single and double bit error detection and reporting. + +- multi-ch-off: + Usage: optional + Value Type: + Definition: If this exists, then the device has the potential to be configured + with different numbers of ddr channels at runtime. The value here + specifies the offset in bits into the "multi_ch_reg" register and + and the number of bits used to decied which llcc configuration to + use. + Example: cache-controller@1100000 {