diff --git a/qcom/sdxpinn-pcie.dtsi b/qcom/sdxpinn-pcie.dtsi new file mode 100644 index 00000000..e4bf681c --- /dev/null +++ b/qcom/sdxpinn-pcie.dtsi @@ -0,0 +1,414 @@ +#include + +&soc { + pcie0: qcom,pcie@1bf0000 { + compatible = "qcom,pci-msm"; + + reg = <0x01bf0000 0x4000>, + <0x01bf7000 0x2000>, + <0x48000000 0xf20>, + <0x48000f20 0xa8>, + <0x48001000 0x2000>, + <0x48100000 0x100000>, + <0x01bf4000 0x1000>; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", + "conf", "mhi"; + + cell-index = <0>; + linux,pci-domain = <0>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x48200000 0x48200000 0x0 0x100000>, + <0x02000000 0x0 0x48300000 0x48300000 0x0 0x3d00000>; + + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + + msi-parent = <&pcie0_msi>; + + perst-gpio = <&tlmm 44 0>; + wake-gpio = <&tlmm 42 0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pcie0_clkreq_default + &pcie0_perst_default + &pcie0_wake_default>; + pinctrl-1 = <&pcie0_clkreq_sleep + &pcie0_perst_default + &pcie0_wake_default>; + + gdsc-core-vdd-supply = <&gcc_pcie_gdsc>; + gdsc-phy-vdd-supply = <&gcc_pcie_phy_gdsc>; + vreg-1p2-supply = <&pmx75_l1>; + vreg-0p9-supply = <&pmx75_l4>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + vreg-mx-supply = <&VDD_MXA_LEVEL>; + + qcom,vreg-1p2-voltage-level = <1200000 1200000 21700>; + qcom,vreg-0p9-voltage-level = <880000 880000 177000>; + qcom,vreg-cx-voltage-level = ; + qcom,vreg-mx-voltage-level = ; + qcom,bw-scale = /* Gen1 */ + ; + + //interconnect-names = "icc_path"; + //interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; + + clocks = <&gcc GCC_PCIE_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_RCHNG_PHY_CLK>, + <&gcc GCC_PCIE_PIPE_CLK_SRC>, + <&pcie_pipe_clk>; + + clock-names = "pcie_pipe_clk", "pcie_ref_clk_src", + "pcie_aux_clk", "pcie_cfg_ahb_clk", + "pcie_mstr_axi_clk", "pcie_slv_axi_clk", + "pcie_clkref_en", "pcie_slv_q2a_axi_clk", + "pcie_sleep_clk", "pcie_phy_refgen_clk", + "pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src"; + + clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <100000000>, <0>, <0>; + clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>, + <0>, <0>, <0>, <0>; + resets = <&gcc GCC_PCIE_BCR>, + <&gcc GCC_PCIE_PHY_BCR>; + reset-names = "pcie_core_reset", + "pcie_phy_reset"; + + //qcom,smmu-sid-base = <0x0800>; + //iommu-map = <0x0 &apps_smmu 0x0800 0x1>, + // <0x100 &apps_smmu 0x0801 0x1>; + + qcom,aux-clk-freq = <20>; /* 19.2 MHz */ + qcom,tpwr-on-scale = <1>; + qcom,tpwr-on-value = <9>; + qcom,eq-fmdc-t-min-phase23 = <1>; + qcom,slv-addr-space-size = <0x4000000>; + qcom,ep-latency = <10>; + qcom,num-parf-testbus-sel = <0xb9>; + + pcie0_rp: pcie0_rp { + reg = <0 0 0 0 0>; + }; + }; + + pcie0_msi: qcom,pcie0_msi@a0000000 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0xa0000000 0x0>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + ; + qcom,snps; + }; + + pcie1: qcom,pcie@1c08000 { + compatible = "qcom,pci-msm"; + + reg = <0x01c08000 0x4000>, + <0x01c0e000 0x2000>, + <0x68000000 0xf1d>, + <0x68000f20 0xa8>, + <0x68001000 0x1000>, + <0x68100000 0x100000>, + <0x01c0c000 0x1000>; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", + "conf", "mhi"; + + cell-index = <1>; + linux,pci-domain = <1>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x68200000 0x68200000 0x0 0x100000>, + <0x02000000 0x0 0x68300000 0x68300000 0x0 0x3d00000>; + + interrupt-parent = <&pcie1>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + + msi-parent = <&pcie1_msi>; + + perst-gpio = <&tlmm 125 0>; + wake-gpio = <&tlmm 123 0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pcie1_clkreq_default + &pcie1_perst_default + &pcie1_wake_default>; + pinctrl-1 = <&pcie1_clkreq_sleep + &pcie1_perst_default + &pcie1_wake_default>; + + gdsc-core-vdd-supply = <&gcc_pcie_1_gdsc>; + gdsc-phy-vdd-supply = <&gcc_pcie_1_phy_gdsc>; + vreg-1p2-supply = <&pmx75_l1>; + vreg-0p9-supply = <&pmx75_l4>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + vreg-mx-supply = <&VDD_MXA_LEVEL>; + + qcom,vreg-1p2-voltage-level = <1200000 1200000 12000>; + qcom,vreg-0p9-voltage-level = <912000 880000 77800>; + qcom,vreg-cx-voltage-level = ; + qcom,vreg-mx-voltage-level = ; + qcom,bw-scale = /* Gen1 */ + ; + + //interconnect-names = "icc_path"; + //interconnects = <&system_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>; + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_CLKREF_EN>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, + <&pcie_1_pipe_clk>; + + clock-names = "pcie_pipe_clk", "pcie_ref_clk_src", + "pcie_aux_clk", "pcie_cfg_ahb_clk", + "pcie_mstr_axi_clk", "pcie_slv_axi_clk", + "pcie_clkref_en", "pcie_slv_q2a_axi_clk", + "pcie_phy_refgen_clk", "pcie_pipe_clk_mux", + "pcie_pipe_clk_ext_src"; + clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <100000000>, <0>, <0>; + clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>, + <0>, <0>, <0>; + + resets = <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "pcie_1_core_reset", + "pcie_1_phy_reset"; + + //qcom,smmu-sid-base = <0x0880>; + //iommu-map = <0x0 &apps_smmu 0x0880 0x1>, + // <0x100 &apps_smmu 0x0881 0x1>; + + qcom,aux-clk-freq = <20>; /* 19.2 MHz */ + qcom,tpwr-on-scale = <1>; + qcom,tpwr-on-value = <9>; + qcom,eq-fmdc-t-min-phase23 = <1>; + qcom,slv-addr-space-size = <0x4000000>; + qcom,ep-latency = <10>; + qcom,num-parf-testbus-sel = <0xb9>; + + pcie1_rp: pcie1_rp { + reg = <0 0 0 0 0>; + + }; + }; + + pcie1_msi: qcom,pcie1_msi@a0000000 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0xa0000000 0x0>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + ; + qcom,snps; + }; + + pcie2: qcom,pcie@1c10000 { + compatible = "qcom,pci-msm"; + + reg = <0x01c10000 0x4000>, + <0x1c16000 0x2000>, + <0x6c000000 0xf1d>, + <0x6c000f20 0xa8>, + <0x6c001000 0x1000>, + <0x6c100000 0x100000>, + <0x01c14000 0x1000>; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", + "conf", "mhi"; + + cell-index = <2>; + linux,pci-domain = <2>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x6c200000 0x6c200000 0x0 0x100000>, + <0x02000000 0x0 0x6c300000 0x6c300000 0x0 0x3d00000>; + + interrupt-parent = <&pcie2>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + + msi-parent = <&pcie2_msi>; + + perst-gpio = <&tlmm 122 0>; + wake-gpio = <&tlmm 120 0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pcie2_clkreq_default + &pcie2_perst_default + &pcie2_wake_default>; + pinctrl-1 = <&pcie2_clkreq_sleep + &pcie2_perst_default + &pcie2_wake_default>; + + gdsc-core-vdd-supply = <&gcc_pcie_2_gdsc>; + gdsc-phy-vdd-supply = <&gcc_pcie_2_phy_gdsc>; + vreg-1p2-supply = <&pmx75_l1>; + vreg-0p9-supply = <&pmx75_l4>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + vreg-mx-supply = <&VDD_MXA_LEVEL>; + + qcom,vreg-1p2-voltage-level = <1200000 1200000 15000>; + qcom,vreg-0p9-voltage-level = <912000 880000 48000>; + qcom,vreg-cx-voltage-level = ; + qcom,vreg-mx-voltage-level = ; + qcom,bw-scale = /* Gen1 */ + ; + + //interconnect-names = "icc_path"; + //interconnects = <&system_noc MASTER_PCIE_2 &mc_virt SLAVE_EBI1>; + + clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_2_AUX_CLK>, + <&gcc GCC_PCIE_2_CFG_AHB_CLK>, + <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_2_SLV_AXI_CLK>, + <&gcc GCC_PCIE_2_CLKREF_EN>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_2_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_2_PIPE_CLK_SRC>, + <&pcie_2_pipe_clk>; + + clock-names = "pcie_pipe_clk", "pcie_ref_clk_src", + "pcie_aux_clk", "pcie_cfg_ahb_clk", + "pcie_mstr_axi_clk", "pcie_slv_axi_clk", + "pcie_clkref_en", "pcie_slv_q2a_axi_clk", + "pcie_phy_refgen_clk","pcie_pipe_clk_mux", + "pcie_pipe_clk_ext_src"; + clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <100000000>, <0>, <0>; + clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>, + <0>, <0>, <0>; + + resets = <&gcc GCC_PCIE_2_BCR>, + <&gcc GCC_PCIE_2_PHY_BCR>; + reset-names = "pcie_2_core_reset", + "pcie_2_phy_reset"; + + //qcom,smmu-sid-base = <0x0900>; + //iommu-map = <0x0 &apps_smmu 0x0900 0x1>, + // <0x100 &apps_smmu 0x0901 0x1>; + + qcom,aux-clk-freq = <20>; /* 19.2 MHz */ + qcom,tpwr-on-scale = <1>; + qcom,tpwr-on-value = <9>; + qcom,eq-fmdc-t-min-phase23 = <1>; + qcom,slv-addr-space-size = <0x4000000>; + qcom,ep-latency = <10>; + qcom,num-parf-testbus-sel = <0xb9>; + + pcie2_rp: pcie2_rp { + reg = <0 0 0 0 0>; + }; + }; + + pcie2_msi: qcom,pcie2_msi@a0000000 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0xa0000000 0x0>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + ; + qcom,snps; + }; +}; diff --git a/qcom/sdxpinn-pinctrl.dtsi b/qcom/sdxpinn-pinctrl.dtsi index c186ab6d..a65f6c02 100644 --- a/qcom/sdxpinn-pinctrl.dtsi +++ b/qcom/sdxpinn-pinctrl.dtsi @@ -39,4 +39,166 @@ }; }; }; + + pcie0 { + pcie0_perst_default: pcie0_perst_default { + mux { + pins = "gpio44"; + function = "gpio"; + }; + + config { + pins = "gpio44"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie0_clkreq_default: pcie0_clkreq_default { + mux { + pins = "gpio43"; + function = "pcie0_clkreqn"; + }; + + config { + pins = "gpio43"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_wake_default: pcie0_wake_default { + mux { + pins = "gpio42"; + function = "gpio"; + }; + + config { + pins = "gpio42"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_clkreq_sleep: pcie0_clkreq_sleep { + mux { + pins = "gpio43"; + function = "gpio"; + }; + + config { + pins = "gpio43"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + pcie1 { + pcie1_perst_default: pcie1_perst_default { + mux { + pins = "gpio125"; + function = "gpio"; + }; + + config { + pins = "gpio125"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie1_clkreq_default: pcie1_clkreq_default { + mux { + pins = "gpio124"; + function = "pcie1_clkreqn"; + }; + + config { + pins = "gpio124"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_wake_default: pcie1_wake_default { + mux { + pins = "gpio123"; + function = "gpio"; + }; + + config { + pins = "gpio123"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_clkreq_sleep: pcie1_clkreq_sleep { + mux { + pins = "gpio124"; + function = "gpio"; + }; + + config { + pins = "gpio124"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + pcie2 { + pcie2_perst_default: pcie2_perst_default { + mux { + pins = "gpio122"; + function = "gpio"; + }; + + config { + pins = "gpio122"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie2_clkreq_default: pcie2_clkreq_default { + mux { + pins = "gpio121"; + function = "pcie2_clkreqn"; + }; + + config { + pins = "gpio121"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie2_wake_default: pcie2_wake_default { + mux { + pins = "gpio120"; + function = "gpio"; + }; + + config { + pins = "gpio120"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie2_clkreq_sleep: pcie2_clkreq_sleep { + mux { + pins = "gpio121"; + function = "gpio"; + }; + + config { + pins = "gpio121"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; }; diff --git a/qcom/sdxpinn-rumi.dtsi b/qcom/sdxpinn-rumi.dtsi index b4e80013..ca3db4b2 100644 --- a/qcom/sdxpinn-rumi.dtsi +++ b/qcom/sdxpinn-rumi.dtsi @@ -6,6 +6,64 @@ clock-frequency = <500000>; }; +&soc { + pcie0: qcom,pcie@1bf0000 { + status = "disabled"; + reg = <0x01bf0000 0x4000>, + <0x01bf7000 0x2000>, + <0x48000000 0xf20>, + <0x48000f20 0xa8>, + <0x48001000 0x2000>, + <0x48100000 0x100000>, + <0x01bf4000 0x1000>, + <0x01bf7500 0x1000>; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", + "conf", "mhi", "rumi"; + qcom,target-link-speed = <0x1>; + qcom,link-check-max-count = <200>; /* 1 sec */ + qcom,no-l1-supported; + qcom,no-l1ss-supported; + qcom,no-aux-clk-sync; + }; + + pcie1: qcom,pcie@1c08000 { + status = "disabled"; + reg = <0x01c08000 0x4000>, + <0x01c0e000 0x2000>, + <0x68000000 0xf1d>, + <0x68000f20 0xa8>, + <0x68001000 0x1000>, + <0x68100000 0x100000>, + <0x01c0c000 0x1000>, + <0x01c0d000 0x1000>; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", + "conf", "mhi", "rumi"; + qcom,target-link-speed = <0x1>; + qcom,link-check-max-count = <200>; /* 1 sec */ + qcom,no-l1-supported; + qcom,no-l1ss-supported; + qcom,no-aux-clk-sync; + }; + + pcie2: qcom,pcie@1c10000 { + status = "disabled"; + reg = <0x01c10000 0x4000>, + <0x1c16000 0x2000>, + <0x6c000000 0xf1d>, + <0x6c000f20 0xa8>, + <0x6c001000 0x1000>, + <0x6c100000 0x100000>, + <0x01c14000 0x1000>; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", + "conf", "mhi"; + qcom,target-link-speed = <0x1>; + qcom,link-check-max-count = <200>; + qcom,no-l1-supported; + qcom,no-l1ss-supported; + qcom,no-aux-clk-sync; + }; +}; + &qupv3_se1_2uart { qcom,rumi_platform; }; diff --git a/qcom/sdxpinn.dtsi b/qcom/sdxpinn.dtsi index 6d1e4164..df486589 100644 --- a/qcom/sdxpinn.dtsi +++ b/qcom/sdxpinn.dtsi @@ -652,6 +652,7 @@ #include "ipcc-test-sdxpinn.dtsi" #include "sdxpinn-regulators.dtsi" #include "sdxpinn-pinctrl.dtsi" +#include "sdxpinn-pcie.dtsi" #include "sdxpinn-qupv3.dtsi" &qupv3_se1_2uart {