From 986c3e84167df21e6fdb6b89e2d9a5dd13d5cab3 Mon Sep 17 00:00:00 2001 From: Tushar Nimkar Date: Sun, 13 Feb 2022 11:27:12 +0530 Subject: [PATCH] dt-bindings: cpuss-sleep-stats: Add support for v2 compatible For Quad core targets, read address of counter registers varies. This adds new v2 compatible since some devices may have different offsets to read cpuss sleep stats. Change-Id: I5a6ad8054d808001526bd84146c767dee0f4fe13 --- bindings/soc/qcom/cpuss-sleep-stats.yaml | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/bindings/soc/qcom/cpuss-sleep-stats.yaml b/bindings/soc/qcom/cpuss-sleep-stats.yaml index 47760b99..1bd98295 100644 --- a/bindings/soc/qcom/cpuss-sleep-stats.yaml +++ b/bindings/soc/qcom/cpuss-sleep-stats.yaml @@ -18,7 +18,8 @@ description: properties: compatible: enum: - - cpuss-sleep-stats + - qcom,cpuss-sleep-stats + - qcom,cpuss-sleep-stats-v2 reg: maxItems: 10 @@ -29,7 +30,7 @@ reguired: - reg-names - num-cpus -example: +examples: - | cpuss-sleep-stats@18000054 { compatible = "qcom,cpuss-sleep-stats"; @@ -44,3 +45,13 @@ example: "l3_seq_lpm_cntr_cfg", "apss_seq_mem_base"; num-cpus = <8>; }; + - | + cpuss-sleep-stats@17800054 { + compatible = "qcom,cpuss-sleep-stats-v2"; + reg = <0x17800054 0x4>, <0x17810054 0x4>, <0x17820054 0x4>, + <0x17830054 0x4>, <0x17880098 0x4>, <0x178C0000 0x10000>; + reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1", + "seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3", + "l3_seq_lpm_cntr_cfg", "apss_seq_mem_base"; + num-cpus = <4>; + };