From 1ac883623006e80157b106fd264a44b25f8fc581 Mon Sep 17 00:00:00 2001
From: Jyothi Kumar Seerapu <jseerapu@qti.qualcomm.com>
Date: Tue, 8 Nov 2022 20:05:52 +0530
Subject: [PATCH] ARM: dts: msm: Make PCIe0 to enumerate with x2 lane for
 sdxpinn

Some sdxpinn targets have fuse blown parts and so in those targets
one PCIe lane got disabled for PCIe0 and such devices are
enumerates with x1 lane width.

Hence, updated in PHY settings for PCIe0 to make sure that device
enumerate with x2 lane width for PCIe0 of all sdxpinn targets.

Change-Id: I2fdac831e670c2573541cb2e53a8c0f252f7f6e5
---
 qcom/sdxpinn-pcie.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/qcom/sdxpinn-pcie.dtsi b/qcom/sdxpinn-pcie.dtsi
index e1d95457..de5cfb7d 100644
--- a/qcom/sdxpinn-pcie.dtsi
+++ b/qcom/sdxpinn-pcie.dtsi
@@ -287,7 +287,7 @@
 				0x1828 0x00 0x0
 				0x1c28 0x00 0x0
 				0x1e24 0x00 0x0
-				0x1e28 0x00 0x0
+				0x1e28 0x01 0x0
 				0x1200 0x00 0x0
 				0x1244 0x03 0x0>;