From a44d58bbc2871961db1a2cb4c915b42099dcc91c Mon Sep 17 00:00:00 2001 From: Sayan Dey Date: Mon, 14 Mar 2022 19:05:57 +0530 Subject: [PATCH] ARM: dts: msm: Add initial device tree for sdxpinn target Add initial device tree support for sdxpinn target. Change-Id: I8c1c6b1c4d23d4cf0cd4dc26fcbc4aa73dfeb583 --- bindings/arm/msm/msm.txt | 4 + qcom/Makefile | 3 + qcom/sdxpinn-rumi.dts | 11 +++ qcom/sdxpinn-rumi.dtsi | 7 ++ qcom/sdxpinn.dts | 9 ++ qcom/sdxpinn.dtsi | 193 +++++++++++++++++++++++++++++++++++++++ 6 files changed, 227 insertions(+) create mode 100644 qcom/sdxpinn-rumi.dts create mode 100644 qcom/sdxpinn-rumi.dtsi create mode 100644 qcom/sdxpinn.dts create mode 100644 qcom/sdxpinn.dtsi diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index 489ac2de..9858b875 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -98,6 +98,9 @@ SoCs: - DIWALI compatible = "qcom,diwali" +- SDXPINN + compatible = "qcom,sdxpinn" + Generic board variants: - CDP device: @@ -290,3 +293,4 @@ compatible = "qcom,sa6155p-adp-star" compatible = "qcom,khaje-idp" compatible = "qcom,khaje-qrd" compatible = "qcom,khaje-atp" +compatible = "qcom,sdxpinn-rumi" diff --git a/qcom/Makefile b/qcom/Makefile index cc56e5f1..63beddda 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -113,6 +113,9 @@ sdmsteppeauto-overlays-dtb-$(CONFIG_ARCH_SA6155) += $(SA6155_BOARDS) $(SA6155P_B dtb-y += $(sdmsteppeauto-dtb-y) +sdxpinn-dtb-$(CONFIG_ARCH_SDXPINN) += sdxpinn-rumi.dtb +dtb-y += $(sdxpinn-dtb-y) + endif ifeq ($(CONFIG_ARCH_KALAMA), y) diff --git a/qcom/sdxpinn-rumi.dts b/qcom/sdxpinn-rumi.dts new file mode 100644 index 00000000..d8d4ee1d --- /dev/null +++ b/qcom/sdxpinn-rumi.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/memreserve/ 0x90f00000 0x00010000; + +#include "sdxpinn.dtsi" +#include "sdxpinn-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXPINN RUMI"; + compatible = "qcom,sdxpinn-rumi", "qcom,sdxpinn", "qcom,rumi"; + qcom,board-id = <15 0>; +}; diff --git a/qcom/sdxpinn-rumi.dtsi b/qcom/sdxpinn-rumi.dtsi new file mode 100644 index 00000000..95fcd374 --- /dev/null +++ b/qcom/sdxpinn-rumi.dtsi @@ -0,0 +1,7 @@ +&arch_timer { + clock-frequency = <500000>; +}; + +&memtimer { + clock-frequency = <500000>; +}; diff --git a/qcom/sdxpinn.dts b/qcom/sdxpinn.dts new file mode 100644 index 00000000..5edac0b8 --- /dev/null +++ b/qcom/sdxpinn.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "sdxpinn.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXPINN SoC"; + compatible = "qcom,sdxpinn"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/sdxpinn.dtsi b/qcom/sdxpinn.dtsi new file mode 100644 index 00000000..295c351d --- /dev/null +++ b/qcom/sdxpinn.dtsi @@ -0,0 +1,193 @@ +#include + +/ { + model = "Qualcomm Technologies, Inc. SDXPINN"; + compatible = "qcom,sdxpinn"; + qcom,msm-id = <556 0x10000>; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + memory { device_type = "memory"; reg = <0 0 0 0>; }; + + reserved_memory: reserved-memory { }; + + chosen: chosen { }; + + aliases { }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x90f00000>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "arm,arch-cache"; + cache-level = <3>; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x90f00000>; + + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x90f00000>; + + L2_2: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x300>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x90f00000>; + + L2_3: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + }; + }; + + soc: soc { }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@17200000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x17200000 0x10000>,/* GICD */ + <0x17260000 0x80000>;/* GICR * 4 */ + interrupts = ; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + memtimer: timer@17420000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17420000 0x1000>; + clock-frequency = <19200000>; + + frame@17421000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x17421000 0x1000>, + <0x17422000 0x1000>; + }; + + frame@17423000 { + frame-number = <1>; + interrupts = ; + reg = <0x17423000 0x1000>; + status = "disabled"; + }; + + frame@17425000 { + frame-number = <2>; + interrupts = ; + reg = <0x17425000 0x1000>; + status = "disabled"; + }; + + frame@17427000 { + frame-number = <3>; + interrupts = ; + reg = <0x17427000 0x1000>; + status = "disabled"; + }; + + frame@17429000 { + frame-number = <4>; + interrupts = ; + reg = <0x17429000 0x1000>; + status = "disabled"; + }; + + frame@1742b000 { + frame-number = <5>; + interrupts = ; + reg = <0x1742b000 0x1000>; + status = "disabled"; + }; + + frame@1742d000 { + frame-number = <6>; + interrupts = ; + reg = <0x1742d000 0x1000>; + status = "disabled"; + }; + }; +};