From 2a109b8b9079e6404cd69cd9a352211828cd5547 Mon Sep 17 00:00:00 2001 From: Lei Chen Date: Fri, 21 Oct 2022 14:34:57 +0800 Subject: [PATCH 01/46] ARM: dts: msm: Add display device tree support for Kalama+sdxpinn Add display device tree for Kalama + sdxpinn MTP and CDP. Change-Id: I462040ca698e77f7991c0b42f71e962277631344 --- display/kalama-sde-display-cdp-overlay.dts | 2 +- display/kalama-sde-display-mtp-overlay.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/display/kalama-sde-display-cdp-overlay.dts b/display/kalama-sde-display-cdp-overlay.dts index 1651b2ac..49138b93 100644 --- a/display/kalama-sde-display-cdp-overlay.dts +++ b/display/kalama-sde-display-cdp-overlay.dts @@ -7,5 +7,5 @@ model = "Qualcomm Technologies, Inc. Kalama CDP"; compatible = "qcom,kalama-cdp", "qcom,kalama", "qcom,cdp"; qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>; - qcom,board-id = <0x10001 0>; + qcom,board-id = <0x10001 0>, <0x03010001 0x3>; }; diff --git a/display/kalama-sde-display-mtp-overlay.dts b/display/kalama-sde-display-mtp-overlay.dts index b8dfac33..f34fc315 100644 --- a/display/kalama-sde-display-mtp-overlay.dts +++ b/display/kalama-sde-display-mtp-overlay.dts @@ -7,5 +7,5 @@ model = "Qualcomm Technologies, Inc. Kalama MTP"; compatible = "qcom,kalama-mtp", "qcom,kalama", "qcom,mtp"; qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>; - qcom,board-id = <0x10008 0>; + qcom,board-id = <0x10008 0>, <0x02010008 0x2>; }; From 94a11be8d48011848b899d53976e7db7a99a2563 Mon Sep 17 00:00:00 2001 From: Grace An Date: Wed, 2 Nov 2022 16:06:48 -0700 Subject: [PATCH 02/46] ARM: dts: msm: add ipcc dpu client physical id on kalama Add new property ipcc dpu client physical id for ipcc registers access. Change-Id: Id80ac63c91eac1da722530206519ddaa1f81c4ae --- bindings/sde.txt | 6 ++++++ display/kalama-sde-common.dtsi | 1 + 2 files changed, 7 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index c4e77f03..0b4fa143 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -513,6 +513,9 @@ Optional properties: silver or gold or gold+. - qcom,sde-qos-cpu-dma-latency: A u32 value indicating desired PM QoS CPU DMA latency in usec. - qcom,sde-qos-cpu-irq-latency: A u32 value indicating desired PM QoS CPU irq latency in usec. +- qcom,sde-ipcc-protocol-id: A u32 value indicating ipcc protocol id used for hw fencing feature. +- qcom,sde-ipcc-client-dpu-phys-id: A u32 value indicating ipcc physical client id of dpu used + for ipcc registers access. - qcom,sde-inline-rot-xin: An integer array of xin-ids related to inline rotation. - qcom,sde-inline-rot-xin-type: A string array indicating the type of xin, @@ -831,6 +834,9 @@ Example: qcom,sde-qos-cpu-dma-latency = <300>; qcom,sde-qos-cpu-irq-latency = <300>; + qcom,sde-ipcc-protocol-id = <0x2>; + qcom,sde-ipcc-client-dpu-phys-id = <0x19>; + qcom,sde-vbif-off = <0 0>; qcom,sde-vbif-id = <0 1>; qcom,sde-vbif-default-ot-rd-limit = <32>; diff --git a/display/kalama-sde-common.dtsi b/display/kalama-sde-common.dtsi index 128d75b6..c5674a58 100644 --- a/display/kalama-sde-common.dtsi +++ b/display/kalama-sde-common.dtsi @@ -230,6 +230,7 @@ qcom,sde-qos-cpu-irq-latency = <300>; qcom,sde-ipcc-protocol-id = <0x2>; + qcom,sde-ipcc-client-dpu-phys-id = <0x19>; /* offsets are relative to "mdp_phys + qcom,sde-off */ qcom,sde-reg-dma-off = <0 0x400>; From 25593f0e7d436fefaa193bc88db03d73de03989e Mon Sep 17 00:00:00 2001 From: Shubham Talekar Date: Wed, 30 Nov 2022 14:04:01 +0530 Subject: [PATCH 03/46] ARM: dts: msm: add support for hdk kalama target Add display support for HDK kalama target. Change-Id: Icf303ac03d687523fc4a305161cb6e14f62ed25e --- display/kalama-sde-display-hdk-overlay.dts | 6 ++++-- display/kalama-sde.dts | 3 ++- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/display/kalama-sde-display-hdk-overlay.dts b/display/kalama-sde-display-hdk-overlay.dts index 06273df3..d59f1b54 100644 --- a/display/kalama-sde-display-hdk-overlay.dts +++ b/display/kalama-sde-display-hdk-overlay.dts @@ -5,7 +5,9 @@ / { model = "Qualcomm Technologies, Inc. Kalama HDK"; - compatible = "qcom,kalama-hdk", "qcom,kalama", "qcom,hdk"; - qcom,msm-id = <536 0x10000>, <536 0x20000>; + compatible = "qcom,kalama-hdk", "qcom,kalama", "qcom,hdk", + "qcom,kalamap"; + qcom,msm-id = <536 0x10000>, <536 0x20000>, <603 0x20000>, + <604 0x20000>; qcom,board-id = <0x1001f 0>; }; diff --git a/display/kalama-sde.dts b/display/kalama-sde.dts index ef25cb06..6f77c1f9 100644 --- a/display/kalama-sde.dts +++ b/display/kalama-sde.dts @@ -4,6 +4,7 @@ #include "kalama-sde.dtsi" / { - qcom,msm-id = <519 0x10000>, <536 0x10000>; + qcom,msm-id = <519 0x10000>, <536 0x10000>, + <603 0x20000>, <604 0x20000>; qcom,board-id = <0 0>; }; From 34fbe7c719cf14c1e88f2f8ad03ad8802cda4def Mon Sep 17 00:00:00 2001 From: Ayushi Makhija Date: Tue, 13 Dec 2022 21:39:57 +0530 Subject: [PATCH 04/46] bindings: correct typo in qcom,bl-dsc-cmd-state property name Update qcom,bl-dsc-cmd-state property name in bindings documentation. Change-Id: I0d24c86eff03a098c80f5f9f7a70ef7368c6c704 --- bindings/mdss-dsi-panel.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt index 6faaae72..6640a3e0 100644 --- a/bindings/mdss-dsi-panel.txt +++ b/bindings/mdss-dsi-panel.txt @@ -260,7 +260,7 @@ Optional properties: 255 = default value. - qcom,mdss-dsi-bl-inverted-dbv: A boolean to specify whether to invert the display brightness value. When this boolean is set, will inverted display brightness value. -- qcom,bl-dsc-cmd-state: String that specifies the ctrl state for sending dcs brightness commands. +- qcom,bl-dcs-cmd-state: String that specifies the ctrl state for sending dcs brightness commands. "dsi_hs_mode" = DSI high speed mode (default) "dsi_lp_mode" = DSI low power mode If the string was not set, dsi_hs_mode will be set as default mode. From 42d5550ff51cf0c09221149183ae32f856bd5f04 Mon Sep 17 00:00:00 2001 From: Ayushi Makhija Date: Tue, 13 Dec 2022 23:43:22 +0530 Subject: [PATCH 05/46] ARM: dts: msm: correct typo of qcom,bl-dsc-cmd-state property name DCS is misspelled as DSC in qcom, bl-dsc-cmd-state property. Correct it as qcom,bl-dcs-cmd-state to avoid confusion between display command set and display stream compression in all platform files. Change-Id: I26cadaeba1d4920abfd419fdfbf99594d3c0e2c6 --- display/kalama-sde-display-cdp.dtsi | 2 +- display/kalama-sde-display-hdk.dtsi | 2 +- display/kalama-sde-display-hhg.dtsi | 2 +- display/kalama-sde-display-mtp.dtsi | 2 +- display/kalama-sde-display-qrd.dtsi | 2 +- display/trustedvm-kalama-sde-display-cdp.dtsi | 2 +- display/trustedvm-kalama-sde-display-mtp.dtsi | 2 +- display/trustedvm-waipio-sde-display-cdp.dtsi | 2 +- display/waipio-sde-display-cdp.dtsi | 2 +- display/waipio-sde-display-mtp.dtsi | 2 +- display/waipio-sde-display-qrd.dtsi | 2 +- display/waipio-sde-display-waipio-lemur.dtsi | 2 +- 12 files changed, 12 insertions(+), 12 deletions(-) diff --git a/display/kalama-sde-display-cdp.dtsi b/display/kalama-sde-display-cdp.dtsi index 81abedf2..32daf823 100644 --- a/display/kalama-sde-display-cdp.dtsi +++ b/display/kalama-sde-display-cdp.dtsi @@ -178,7 +178,7 @@ &dsi_dual_sim_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,bl-dsc-cmd-state = "dsi_lp_mode"; + qcom,bl-dcs-cmd-state = "dsi_lp_mode"; }; &dsi_dual_sim_dsc_375_cmd { diff --git a/display/kalama-sde-display-hdk.dtsi b/display/kalama-sde-display-hdk.dtsi index c5cf18d7..2ac6c675 100644 --- a/display/kalama-sde-display-hdk.dtsi +++ b/display/kalama-sde-display-hdk.dtsi @@ -80,7 +80,7 @@ &dsi_dual_sim_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,bl-dsc-cmd-state = "dsi_lp_mode"; + qcom,bl-dcs-cmd-state = "dsi_lp_mode"; }; &dsi_dual_sim_dsc_375_cmd { diff --git a/display/kalama-sde-display-hhg.dtsi b/display/kalama-sde-display-hhg.dtsi index 4b9efde5..a06d3c7c 100644 --- a/display/kalama-sde-display-hhg.dtsi +++ b/display/kalama-sde-display-hhg.dtsi @@ -158,7 +158,7 @@ &dsi_dual_sim_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,bl-dsc-cmd-state = "dsi_lp_mode"; + qcom,bl-dcs-cmd-state = "dsi_lp_mode"; }; &dsi_dual_sim_dsc_375_cmd { diff --git a/display/kalama-sde-display-mtp.dtsi b/display/kalama-sde-display-mtp.dtsi index 0ee965ab..183bda6e 100644 --- a/display/kalama-sde-display-mtp.dtsi +++ b/display/kalama-sde-display-mtp.dtsi @@ -158,7 +158,7 @@ &dsi_dual_sim_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,bl-dsc-cmd-state = "dsi_lp_mode"; + qcom,bl-dcs-cmd-state = "dsi_lp_mode"; }; &dsi_dual_sim_dsc_375_cmd { diff --git a/display/kalama-sde-display-qrd.dtsi b/display/kalama-sde-display-qrd.dtsi index 4b9efde5..a06d3c7c 100644 --- a/display/kalama-sde-display-qrd.dtsi +++ b/display/kalama-sde-display-qrd.dtsi @@ -158,7 +158,7 @@ &dsi_dual_sim_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,bl-dsc-cmd-state = "dsi_lp_mode"; + qcom,bl-dcs-cmd-state = "dsi_lp_mode"; }; &dsi_dual_sim_dsc_375_cmd { diff --git a/display/trustedvm-kalama-sde-display-cdp.dtsi b/display/trustedvm-kalama-sde-display-cdp.dtsi index 000da1a1..e9cbda7c 100644 --- a/display/trustedvm-kalama-sde-display-cdp.dtsi +++ b/display/trustedvm-kalama-sde-display-cdp.dtsi @@ -135,7 +135,7 @@ &dsi_dual_sim_cmd { qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,bl-dsc-cmd-state = "dsi_lp_mode"; + qcom,bl-dcs-cmd-state = "dsi_lp_mode"; }; &dsi_dual_sim_dsc_375_cmd { diff --git a/display/trustedvm-kalama-sde-display-mtp.dtsi b/display/trustedvm-kalama-sde-display-mtp.dtsi index 0d5c866d..a450ef0a 100644 --- a/display/trustedvm-kalama-sde-display-mtp.dtsi +++ b/display/trustedvm-kalama-sde-display-mtp.dtsi @@ -116,7 +116,7 @@ &dsi_dual_sim_cmd { qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,bl-dsc-cmd-state = "dsi_lp_mode"; + qcom,bl-dcs-cmd-state = "dsi_lp_mode"; }; &dsi_dual_sim_dsc_375_cmd { diff --git a/display/trustedvm-waipio-sde-display-cdp.dtsi b/display/trustedvm-waipio-sde-display-cdp.dtsi index c7c022dc..641022ba 100644 --- a/display/trustedvm-waipio-sde-display-cdp.dtsi +++ b/display/trustedvm-waipio-sde-display-cdp.dtsi @@ -100,7 +100,7 @@ &dsi_dual_sim_cmd { qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,platform-reset-gpio = <&tlmm 0 0>; - qcom,bl-dsc-cmd-state = "dsi_lp_mode"; + qcom,bl-dcs-cmd-state = "dsi_lp_mode"; }; &dsi_dual_sim_vid { diff --git a/display/waipio-sde-display-cdp.dtsi b/display/waipio-sde-display-cdp.dtsi index a510b99f..ec33a4ef 100644 --- a/display/waipio-sde-display-cdp.dtsi +++ b/display/waipio-sde-display-cdp.dtsi @@ -198,7 +198,7 @@ &dsi_dual_sim_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,bl-dsc-cmd-state = "dsi_lp_mode"; + qcom,bl-dcs-cmd-state = "dsi_lp_mode"; }; &dsi_dual_sim_vid { diff --git a/display/waipio-sde-display-mtp.dtsi b/display/waipio-sde-display-mtp.dtsi index 463ce5ce..7264fc6b 100644 --- a/display/waipio-sde-display-mtp.dtsi +++ b/display/waipio-sde-display-mtp.dtsi @@ -180,7 +180,7 @@ &dsi_dual_sim_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,bl-dsc-cmd-state = "dsi_lp_mode"; + qcom,bl-dcs-cmd-state = "dsi_lp_mode"; }; &dsi_dual_sim_vid { diff --git a/display/waipio-sde-display-qrd.dtsi b/display/waipio-sde-display-qrd.dtsi index a129f9ca..c8a33c48 100644 --- a/display/waipio-sde-display-qrd.dtsi +++ b/display/waipio-sde-display-qrd.dtsi @@ -170,7 +170,7 @@ &dsi_dual_sim_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,bl-dsc-cmd-state = "dsi_lp_mode"; + qcom,bl-dcs-cmd-state = "dsi_lp_mode"; }; &dsi_dual_sim_vid { diff --git a/display/waipio-sde-display-waipio-lemur.dtsi b/display/waipio-sde-display-waipio-lemur.dtsi index 70d5d5ee..5f8d7fa6 100644 --- a/display/waipio-sde-display-waipio-lemur.dtsi +++ b/display/waipio-sde-display-waipio-lemur.dtsi @@ -140,7 +140,7 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,platform-reset-gpio = <&tlmm 0 0>; - qcom,bl-dsc-cmd-state = "dsi_lp_mode"; + qcom,bl-dcs-cmd-state = "dsi_lp_mode"; }; &dsi_dual_sim_vid { From 93755c111b70afdb18aba59a83b2fe6a1e5cb7f2 Mon Sep 17 00:00:00 2001 From: Deven Solanki Date: Thu, 29 Dec 2022 11:54:25 +0530 Subject: [PATCH 06/46] ARM: dts: msm: add support for Kalama SoC variant Add display DT support for Kalama SoC variant. Change-Id: Ia0c072e7d11dc0aa223335e12d721e2c422570b9 --- display/kalama-sde-display-cdp-nfc-overlay.dts | 3 ++- display/kalama-sde-display-cdp-overlay.dts | 3 ++- display/kalama-sde-display-cdp-wsa883x-overlay.dts | 3 ++- display/kalama-sde-display-hdk-overlay.dts | 3 +-- display/kalama-sde-display-mtp-nfc-overlay.dts | 3 ++- display/kalama-sde-display-mtp-overlay.dts | 3 ++- 6 files changed, 11 insertions(+), 7 deletions(-) diff --git a/display/kalama-sde-display-cdp-nfc-overlay.dts b/display/kalama-sde-display-cdp-nfc-overlay.dts index 3c8ad708..8380deb1 100644 --- a/display/kalama-sde-display-cdp-nfc-overlay.dts +++ b/display/kalama-sde-display-cdp-nfc-overlay.dts @@ -6,6 +6,7 @@ / { model = "Qualcomm Technologies, Inc. Kalama CDP ST54K NFC"; compatible = "qcom,kalama-cdp", "qcom,kalama", "qcom,cdp"; - qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>; + qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>, + <603 0x20000>, <604 0x20000>; qcom,board-id = <0x02010001 0>; }; diff --git a/display/kalama-sde-display-cdp-overlay.dts b/display/kalama-sde-display-cdp-overlay.dts index 49138b93..23517280 100644 --- a/display/kalama-sde-display-cdp-overlay.dts +++ b/display/kalama-sde-display-cdp-overlay.dts @@ -6,6 +6,7 @@ / { model = "Qualcomm Technologies, Inc. Kalama CDP"; compatible = "qcom,kalama-cdp", "qcom,kalama", "qcom,cdp"; - qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>; + qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>, + <603 0x20000>, <604 0x20000>; qcom,board-id = <0x10001 0>, <0x03010001 0x3>; }; diff --git a/display/kalama-sde-display-cdp-wsa883x-overlay.dts b/display/kalama-sde-display-cdp-wsa883x-overlay.dts index 3e10b962..bf21c80d 100644 --- a/display/kalama-sde-display-cdp-wsa883x-overlay.dts +++ b/display/kalama-sde-display-cdp-wsa883x-overlay.dts @@ -6,6 +6,7 @@ / { model = "Qualcomm Technologies, Inc. Kalama CDP - WSA883X"; compatible = "qcom,kalama-cdp", "qcom,kalama", "qcom,cdp"; - qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>; + qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>, + <603 0x20000>, <604 0x20000>; qcom,board-id = <0x1010001 0>; }; diff --git a/display/kalama-sde-display-hdk-overlay.dts b/display/kalama-sde-display-hdk-overlay.dts index d59f1b54..40ab26f9 100644 --- a/display/kalama-sde-display-hdk-overlay.dts +++ b/display/kalama-sde-display-hdk-overlay.dts @@ -7,7 +7,6 @@ model = "Qualcomm Technologies, Inc. Kalama HDK"; compatible = "qcom,kalama-hdk", "qcom,kalama", "qcom,hdk", "qcom,kalamap"; - qcom,msm-id = <536 0x10000>, <536 0x20000>, <603 0x20000>, - <604 0x20000>; + qcom,msm-id = <536 0x10000>, <536 0x20000>, <603 0x20000>; qcom,board-id = <0x1001f 0>; }; diff --git a/display/kalama-sde-display-mtp-nfc-overlay.dts b/display/kalama-sde-display-mtp-nfc-overlay.dts index 66db5c2d..6d82858a 100644 --- a/display/kalama-sde-display-mtp-nfc-overlay.dts +++ b/display/kalama-sde-display-mtp-nfc-overlay.dts @@ -6,6 +6,7 @@ / { model = "Qualcomm Technologies, Inc. Kalama MTP ST54K NFC"; compatible = "qcom,kalama-mtp", "qcom,kalama", "qcom,mtp"; - qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>; + qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>, + <604 0x20000>; qcom,board-id = <0x1010008 0>; }; diff --git a/display/kalama-sde-display-mtp-overlay.dts b/display/kalama-sde-display-mtp-overlay.dts index f34fc315..15e8f63a 100644 --- a/display/kalama-sde-display-mtp-overlay.dts +++ b/display/kalama-sde-display-mtp-overlay.dts @@ -6,6 +6,7 @@ / { model = "Qualcomm Technologies, Inc. Kalama MTP"; compatible = "qcom,kalama-mtp", "qcom,kalama", "qcom,mtp"; - qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>; + qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>, + <604 0x20000>; qcom,board-id = <0x10008 0>, <0x02010008 0x2>; }; From 332e90db87e9aac686001979989a1f5046c2f702 Mon Sep 17 00:00:00 2001 From: Jyothi bommidi Date: Tue, 7 Feb 2023 17:03:17 +0530 Subject: [PATCH 07/46] ARM: dts: msm: enable DFPS for sharp QHD plus video mode panel on Kalama Enable DFPS for sharp QHD plus video mode panel on Kalama. Change-Id: I89d4607d29193e2d947e49f1e2cdb0e7e5ce5ea0 --- display/kalama-sde-display-common.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/display/kalama-sde-display-common.dtsi b/display/kalama-sde-display-common.dtsi index 559e1326..2228f947 100644 --- a/display/kalama-sde-display-common.dtsi +++ b/display/kalama-sde-display-common.dtsi @@ -436,6 +436,11 @@ &dsi_sharp_qhd_plus_dsc_video { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,dsi-supported-dfps-list = <120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,mdss-dsi-display-timings { timing@0 { /* 120 FPS */ qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07 From 16fa717b996c64c959dc08525d8c386d2359ddae Mon Sep 17 00:00:00 2001 From: Anand Tarakh Date: Tue, 2 May 2023 17:00:12 +0530 Subject: [PATCH 08/46] ARM: dts: msm: add display platform overlay for crow target Add display platform overlay for crow target. Change-Id: I2b879ab6f18691d194e444f5782d97b21814209d --- display/crow-sde-display-atp-overlay.dts | 11 + display/crow-sde-display-atp.dtsi | 1 + display/crow-sde-display-common.dtsi | 414 +++++++++++++++++++ display/crow-sde-display-idp-overlay.dts | 11 + display/crow-sde-display-idp-wcd-overlay.dts | 11 + display/crow-sde-display-idp-wcd.dtsi | 1 + display/crow-sde-display-idp.dtsi | 76 ++++ display/crow-sde-display-pinctrl.dtsi | 58 +++ display/crow-sde-display-qrd-overlay.dts | 11 + display/crow-sde-display-qrd.dtsi | 5 + display/crow-sde-display.dtsi | 95 +++++ 11 files changed, 694 insertions(+) create mode 100644 display/crow-sde-display-atp-overlay.dts create mode 100644 display/crow-sde-display-atp.dtsi create mode 100644 display/crow-sde-display-common.dtsi create mode 100644 display/crow-sde-display-idp-overlay.dts create mode 100644 display/crow-sde-display-idp-wcd-overlay.dts create mode 100644 display/crow-sde-display-idp-wcd.dtsi create mode 100644 display/crow-sde-display-idp.dtsi create mode 100644 display/crow-sde-display-pinctrl.dtsi create mode 100644 display/crow-sde-display-qrd-overlay.dts create mode 100644 display/crow-sde-display-qrd.dtsi create mode 100644 display/crow-sde-display.dtsi diff --git a/display/crow-sde-display-atp-overlay.dts b/display/crow-sde-display-atp-overlay.dts new file mode 100644 index 00000000..d14db9a9 --- /dev/null +++ b/display/crow-sde-display-atp-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "crow-sde-display-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Crow ATP"; + compatible = "qcom,crow-atp", "qcom,crow", "qcom,atp"; + qcom,msm-id = <608 0x10000>; + qcom,board-id = <33 0>; +}; diff --git a/display/crow-sde-display-atp.dtsi b/display/crow-sde-display-atp.dtsi new file mode 100644 index 00000000..98b1c464 --- /dev/null +++ b/display/crow-sde-display-atp.dtsi @@ -0,0 +1 @@ +#include "crow-sde-display-idp.dtsi" diff --git a/display/crow-sde-display-common.dtsi b/display/crow-sde-display-common.dtsi new file mode 100644 index 00000000..31e839a1 --- /dev/null +++ b/display/crow-sde-display-common.dtsi @@ -0,0 +1,414 @@ +#include "dsi-panel-sim-cmd.dtsi" +#include "dsi-panel-sim-video.dtsi" +#include "dsi-panel-sim-dsc375-cmd.dtsi" +#include "dsi-panel-sim-dsc-10bit-cmd.dtsi" +#include "dsi-panel-sim-cmd-au.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi" +#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi" + +#include "crow-sde-display-pinctrl.dtsi" + +&soc { + dsi_panel_pwr_supply_sim: dsi_panel_pwr_supply_sim { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "dummy"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <200000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <200000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <299000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "vci"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <10000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + }; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0>; + qcom,dsi-phy = <&mdss_dsi_phy0>; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 122 0>; + qcom,panel-te-source = <0>; + + qcom,mdp = <&mdss_mdp>; + qcom,demura-panel-id = <0x0122e700 0x00000471>; + }; + +}; + +/* PHY TIMINGS REVISION YL with reduced margins */ +&dsi_vtdr6130_amoled_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + timing@3 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_panel_au { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,poms-align-panel-vsync; + qcom,mdss-dsi-display-timings { + timing@0 { /* WQHD 60FPS cmd-vid mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 + 07 07 02 04 00 16 0c]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@1 { /* WQHD 60FPS vid mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 + 07 07 02 04 00 16 0c]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@2 { /* FHD+ 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 25 0a 0a 1b 24 0a + 0a 0a 02 04 00 1f 0f]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@3 { /* HD 60FPS cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 29 0a 0b 1b 26 0a + 0b 0a 02 04 00 21 10]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@4 { /* FHD+ 90FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 39 0f 0e 21 2a 0e + 0f 0d 02 04 00 2d 13]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@5 { /* FHD+ 180 FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 69 1d 1d 35 2f 1b + 1d 18 02 04 00 51 21]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* FHD+ 240 FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 89 26 27 42 39 25 + 27 1f 02 04 00 69 2a]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@7 { /* FHD+ 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 4a 13 14 28 24 12 + 14 11 02 04 00 39 18]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@8 { /* FHD+ 1FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 04 00 00 0d 18 01 + 00 01 02 04 00 05 05]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@9 { /* FHD+ 5FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 06 00 00 0d 1a 01 + 00 01 02 04 00 06 05]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@10 { /* FHD+ 10FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01 + 01 01 02 04 00 07 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@11 { /* FHD+ 24FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 09 01 01 0e 1b 02 + 01 01 02 04 00 08 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@12 { /* FHD+ 30FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 0e 1b 02 + 02 01 02 04 00 09 07]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@13 { /* FHD+ 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + }; +}; + +&dsi_sim_vid { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01 + 01 01 02 04 00 06 06]; + qcom,display-topology = <1 0 1>, + <2 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_375_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* 1080p */ + qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 14 1f 05 + 05 06 02 04 00 13 0a]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* qhd */ + qcom,mdss-dsi-panel-phy-timings = [00 0c 02 02 10 1c 03 + 03 02 02 04 00 0b 08]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* QHD 60fps */ + qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 14 1f 05 + 05 06 02 04 00 13 0a]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + + timing@1 { /* FHD+ 60fps cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 1d 03 + 03 02 02 04 00 0c 08]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + + timing@2 { /* QHD 90fps */ + qcom,mdss-dsi-panel-phy-timings = [00 1d 08 07 17 22 08 + 08 08 02 04 00 19 0d]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + + timing@3 { /* FHD+ 180FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1f 08 07 18 16 08 + 08 08 02 04 00 1a 0d]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* FHD+ 240FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* FHD+ 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06 + 06 06 02 04 00 13 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* FHD+ 1FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 04 00 00 0d 18 01 + 00 01 02 04 00 05 05]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@7 { /* FHD+ 10FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01 + 01 01 02 04 00 07 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@8 { /* FHD+ 24FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 09 01 01 0e 1b 02 + 01 01 02 04 00 08 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@9 { /* FHD+ 30FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 0e 1b 02 + 02 01 02 04 00 09 07]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@10 { /* FHD+ 90FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 39 0f 0e 21 2a 0e + 0f 0d 02 04 00 2d 13]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@11 { /* FHD+ 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/crow-sde-display-idp-overlay.dts b/display/crow-sde-display-idp-overlay.dts new file mode 100644 index 00000000..e50c54ac --- /dev/null +++ b/display/crow-sde-display-idp-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "crow-sde-display-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Crow IDP"; + compatible = "qcom,crow-idp", "qcom,crow", "qcom,idp"; + qcom,msm-id = <608 0x10000>; + qcom,board-id = <34 0>; +}; diff --git a/display/crow-sde-display-idp-wcd-overlay.dts b/display/crow-sde-display-idp-wcd-overlay.dts new file mode 100644 index 00000000..67ab0753 --- /dev/null +++ b/display/crow-sde-display-idp-wcd-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "crow-sde-display-idp-wcd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Crow IDP WCD"; + compatible = "qcom,crow-idp", "qcom,crow", "qcom,idp"; + qcom,msm-id = <608 0x10000>; + qcom,board-id = <34 1>, <34 2>, <34 3>; +}; diff --git a/display/crow-sde-display-idp-wcd.dtsi b/display/crow-sde-display-idp-wcd.dtsi new file mode 100644 index 00000000..98b1c464 --- /dev/null +++ b/display/crow-sde-display-idp-wcd.dtsi @@ -0,0 +1 @@ +#include "crow-sde-display-idp.dtsi" diff --git a/display/crow-sde-display-idp.dtsi b/display/crow-sde-display-idp.dtsi new file mode 100644 index 00000000..52a7ba71 --- /dev/null +++ b/display/crow-sde-display-idp.dtsi @@ -0,0 +1,76 @@ +#include "crow-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_sim_panel_au { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_video>; +}; + diff --git a/display/crow-sde-display-pinctrl.dtsi b/display/crow-sde-display-pinctrl.dtsi new file mode 100644 index 00000000..3361c2b0 --- /dev/null +++ b/display/crow-sde-display-pinctrl.dtsi @@ -0,0 +1,58 @@ +&tlmm { + pmx_sde: pmx_sde { + sde_dsi_active: sde_dsi_active { + mux { + pins = "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio127"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + + sde_dsi_suspend: sde_dsi_suspend { + mux { + pins = "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio127"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + pmx_sde_te: pmx_sde_te { + sde_te_active: sde_te_active { + mux { + pins = "gpio122"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio122"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te_suspend: sde_te_suspend { + mux { + pins = "gpio122"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio122"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; +}; + diff --git a/display/crow-sde-display-qrd-overlay.dts b/display/crow-sde-display-qrd-overlay.dts new file mode 100644 index 00000000..377dee99 --- /dev/null +++ b/display/crow-sde-display-qrd-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "crow-sde-display-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Crow QRD"; + compatible = "qcom,crow-qrd", "qcom,crow", "qcom,qrd"; + qcom,msm-id = <608 0x10000>; + qcom,board-id = <11 0>; +}; diff --git a/display/crow-sde-display-qrd.dtsi b/display/crow-sde-display-qrd.dtsi new file mode 100644 index 00000000..db8a80bb --- /dev/null +++ b/display/crow-sde-display-qrd.dtsi @@ -0,0 +1,5 @@ +#include "crow-sde-display-idp.dtsi" + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; +}; diff --git a/display/crow-sde-display.dtsi b/display/crow-sde-display.dtsi new file mode 100644 index 00000000..686a670f --- /dev/null +++ b/display/crow-sde-display.dtsi @@ -0,0 +1,95 @@ +#include +#include "crow-sde-display-common.dtsi" + +&soc { + sde_wb: qcom,wb-display@0 { + compatible = "qcom,wb-display"; + cell-index = <0>; + label = "wb_display"; + }; +}; + +&sde_dsi { + clocks = <&mdss_dsi_phy0 0>, + <&mdss_dsi_phy0 1>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "mdp_core_clk"; + vddio-supply = <&L9B>; + vci-supply = <&L19B>; + vdd-supply = <&L3D>; +}; + +&mdss_mdp { + connectors = <&sde_dsi &smmu_sde_unsec &smmu_sde_sec &sde_wb>; +}; + +&dsi_vtdr6130_amoled_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@3 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + }; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,ulps-enabled; +}; + +&dsi_sim_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { /* WQHD 60FPS cmd vid mode*/ + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; + }; + timing@2 { /* FHD 60FPS cmd mode*/ + qcom,panel-roi-alignment = <540 40 540 40 540 40>; + qcom,partial-update-enabled = "single_roi"; + }; + timing@3 { /* HD 60FPS cmd mode*/ + qcom,panel-roi-alignment = <360 20 360 20 360 20>; + qcom,partial-update-enabled = "single_roi"; + }; + }; +}; + +&dsi_sim_dsc_375_cmd { + qcom,ulps-enabled; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,ulps-enabled; +}; From 3aa4f122721cae80fead8e6cb389abee94e181d2 Mon Sep 17 00:00:00 2001 From: Karthik Date: Mon, 10 Apr 2023 12:27:21 +0530 Subject: [PATCH 09/46] ARM: dts: msm: add display dt node for crow target Add display dt node for crow target. Change-Id: I13f98ec0bb7ae562b861b7be23ff6e7f4a1333d4 --- Kbuild | 4 + display/crow-sde-common.dtsi | 370 +++++++++++++++++++++++++++++++++++ display/crow-sde.dts | 9 + display/crow-sde.dtsi | 116 +++++++++++ 4 files changed, 499 insertions(+) create mode 100644 display/crow-sde-common.dtsi create mode 100644 display/crow-sde.dts create mode 100644 display/crow-sde.dtsi diff --git a/Kbuild b/Kbuild index 18c1f424..5a3410f7 100644 --- a/Kbuild +++ b/Kbuild @@ -22,6 +22,10 @@ dtbo-$(CONFIG_ARCH_KALAMA) += display/trustedvm-kalama-sde-display-mtp-overlay.d display/trustedvm-kalama-sde-display-atp-overlay.dtbo endif +ifneq ($(CONFIG_ARCH_QTI_VM), y) +dtbo-$(CONFIG_ARCH_CROW) += display/crow-sde.dtbo +endif + ifeq ($(CONFIG_ARCH_SA8155), y) dtbo-y += display/sa8155-adp-star-display.dtbo endif diff --git a/display/crow-sde-common.dtsi b/display/crow-sde-common.dtsi new file mode 100644 index 00000000..83cfa8b2 --- /dev/null +++ b/display/crow-sde-common.dtsi @@ -0,0 +1,370 @@ +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@ae00000 { + compatible = "qcom,sde-kms"; + reg = <0x0ae00000 0x84000>, + <0x0aeb0000 0x2008>, + <0x0aeac000 0x800>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys"; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + #cooling-cells = <2>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x488>; + + qcom,sde-ctl-off = <0x16000 0x17000 0x18000 + 0x19000>; + qcom,sde-ctl-size = <0x290>; + qcom,sde-ctl-display-pref = "primary", "none", "none", + "none"; + + qcom,sde-mixer-off = <0x45000 0x46000 0x47000 + 0x48000 + 0x0f0f 0x0f0f>; + qcom,sde-mixer-size = <0x400>; + qcom,sde-mixer-display-pref = "primary", "primary", "none", + "none", "none", "none"; + + qcom,sde-mixer-dcwb-pref = "none", "none", "none", "none", + "dcwb", "dcwb"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000 0x57000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-dspp-rc-version = <0x00010001>; + qcom,sde-dspp-rc-off = <0x15800 0x14800>; + qcom,sde-dspp-rc-size = <0x38>; + qcom,sde-dspp-rc-mem-size = <2720>; + qcom,sde-dspp-rc-min-region-width = <20>; + + qcom,sde-dest-scaler-top-off = <0x00061000>; + qcom,sde-dest-scaler-top-size = <0x1c>; + qcom,sde-dest-scaler-off = <0x0 0x1000>; + qcom,sde-dest-scaler-size = <0x800>; + + qcom,sde-wb-off = <0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-wb-id = <2>; + + qcom,sde-intf-off = <0x35000 0x36000 + 0x38000 0x3a000>; + qcom,sde-intf-size = <0x300>; + qcom,sde-intf-type = "dp", "dsi", "dp", "dp"; + qcom,sde-intf-tear-irq-off = <0 0x36800 0 0>; + + qcom,sde-pp-off = <0x6a000 0x6b000 0x6c000 0x6d000 + 0x67000 0x67400>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0>; + qcom,sde-pp-size = <0x4>; + qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2>; + + qcom,sde-merge-3d-off = <0x4f000 0x50000 0x67700>; + qcom,sde-merge-3d-size = <0x8>; + qcom,sde-pp-cwb = <0x0 0x0 0x0 0x0 0x1 0x1>; + + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x220>; + + qcom,sde-dsc-off = <0x81000 0x81000>; + qcom,sde-dsc-size = <0x4>; + qcom,sde-dsc-pair-mask = <2 1>; + qcom,sde-dsc-hw-rev = "dsc_1_2"; + qcom,sde-dsc-enc = <0x100 0x200>; + qcom,sde-dsc-enc-size = <0x9c>; + qcom,sde-dsc-ctl = <0xF00 0xF80>; + qcom,sde-dsc-ctl-size = <0x24>; + qcom,sde-dsc-native422-supp = <1 1>; + + qcom,sde-dither-off = <0xe0 0xe0 0xe0 + 0xe0 0xe0 0xe0>; + qcom,sde-cwb-dither = <0x0 0x0 0x0 0x0 0x1 0x1>; + qcom,sde-dither-version = <0x00020000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "vig", + "dma", "dma", "dma", "dma"; + qcom,sde-sspp-off = <0x5000 0x7000 + 0x25000 0x27000 0x29000 0x2b000>; + qcom,sde-sspp-src-size = <0x344>; + + qcom,sde-sspp-xin-id = <0 4 1 5 9 13>; + qcom,sde-sspp-excl-rect = <1 1 1 1 1 1>; + qcom,sde-sspp-smart-dma-priority = <5 6 1 2 3 4>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <2 1 4 3 6 5>; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-max-per-pipe-bw-kbps = <4300000 4300000 + 4300000 4300000 + 4300000 4300000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = + <0x4330 0>, <0x6330 0>, + <0x24330 0>, <0x26330 0>, <0x28330 0>, <0x2a330 0>; + qcom,sde-sspp-clk-status = + <0x4334 0>, <0x6334 0>, + <0x24334 0>, <0x26334 0>, <0x28334 0>, <0x2a334 0>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; + qcom,sde-qseed-scalar-version = <0x3002>; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <4096>; + qcom,sde-vig-sspp-linewidth = <5120>; + qcom,sde-wb-linewidth = <4096>; + qcom,sde-dsc-linewidth = <2560>; + qcom,sde-max-dest-scaler-input-linewidth = <2048>; + qcom,sde-max-dest-scaler-output-linewidth = <2560>; + qcom,sde-wb-linewidth-linear = <5120>; + qcom,sde-mixer-blendstages = <0xb>; + qcom,sde-highest-bank-bit = <0x8 0x2>, + <0x7 0x1>; + qcom,sde-ubwc-version = <0x40000002>; + qcom,sde-ubwc-swizzle = <0x6>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-ubwc-static = <0x1>; + qcom,sde-macrotile-mode = <0x1>; + qcom,sde-smart-panel-align-mode = <0xc>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-has-dest-scaler; + qcom,sde-max-trusted-vm-displays = <1>; + + qcom,sde-max-bw-low-kbps = <5200000>; + qcom,sde-max-bw-high-kbps = <10400000>; + qcom,sde-min-core-ib-kbps = <2500000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <800000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + qcom,sde-num-ddr-channels = <2>; + + qcom,sde-dspp-spr-off = <0x15400 0x14400>; + qcom,sde-dspp-spr-size = <0x100>; + qcom,sde-dspp-spr-version = <0x00010000>; + + qcom,sde-dspp-demura-off = <0x15600 0x14600>; + qcom,sde-dspp-demura-size = <0xe4>; + qcom,sde-dspp-demura-version = <0x00010000>; + + qcom,sde-lm-noise-off = <0x320>; + qcom,sde-lm-noise-version = <0x00010000>; + + qcom,sde-uidle-off = <0x80000>; + qcom,sde-uidle-size = <0x80>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x1074>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3 3 3>; + + qcom,sde-vbif-default-ot-rd-limit = <40>; + qcom,sde-vbif-default-ot-wr-limit = <32>; + qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2 124416000 6 497664000 16>; + + qcom,sde-vbif-qos-rt-remap = <4 4 5 5 5 5 6 6 4 4 5 5 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cwb-remap = <4 4 4 4 4 5 6 6 4 4 4 4 4 5 6 6>; + qcom,sde-vbif-qos-lutdma-remap = <4 4 5 5 5 5 6 6 4 4 5 5 5 5 6 6>; + qcom,sde-vbif-qos-offline-wb-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cnoc-remap = <3 3 4 4 5 5 5 5 3 3 3 3 3 3 3 3>; + + qcom,sde-danger-lut = <0xffff 0xffff 0xffff 0xffff 0x0 0x0 0x0 0x0 + 0x0 0x0 0xffff 0xffff 0xffff 0xffff 0x0 0x0>; + + qcom,sde-safe-lut = <0xff00 0xfff0 0xff00 0xfff0 0xffff 0xffff 0x0001 0x0001 + 0x03ff 0x03ff 0xff00 0xfff0 0xff00 0xfff0 0xffff 0xffff>; + + qcom,sde-creq-lut = <0x00112233 0x44556666 0x00112233 0x66666666 + 0x00112233 0x44556666 0x00112233 0x66666666 + 0x0 0x0 0x0 0x0 + 0x77776666 0x66666540 0x77776666 0x66666540 + 0x77776541 0x0 0x77776541 0x0 + 0x00112233 0x44556666 0x00112233 0x66666666 + 0x00112233 0x44556666 0x00112233 0x66666666 + 0x0 0x0 0x0 0x0>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-mask-performance = <0xf>; + qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-reg-dma-off = <0 0x400>; + qcom,sde-reg-dma-id = <0 1>; + qcom,sde-reg-dma-version = <0x00020000>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + qcom,sde-reg-dma-xin-id = <7>; + qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + + qcom,sde-secure-sid-mask = <0x0001c01>; + + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 57000>, + <0 590000>, + <0 1190000>; + + qcom,sde-sspp-vig-blocks { + vcm@0 { + cell-index = <0>; + qcom,sde-vig-top-off = <0xa00>; + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xe0>; + qcom,sde-vig-gamut = <0x1d00 0x00060001>; + qcom,sde-vig-igc = <0x1d00 0x00060000>; + qcom,sde-vig-inverse-pma; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + }; + + vcm@1 { + cell-index = <1>; + qcom,sde-fp16-igc = <0x280 0x00010000>; + qcom,sde-fp16-unmult = <0x280 0x00010000>; + qcom,sde-fp16-gc = <0x280 0x00010000>; + qcom,sde-fp16-csc = <0x280 0x00010000>; + }; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + cell-index = <0>; + qcom,sde-dma-top-off = <0x800>; + qcom,sde-dma-igc = <0xa00 0x00050000>; + qcom,sde-dma-gc = <0xc00 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x800>; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + }; + + dgm@1 { + cell-index = <1>; + qcom,sde-dma-igc = <0x1a00 0x00050000>; + qcom,sde-dma-gc = <0xc00 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x1800>; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + }; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x1260 0x00040000>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone = <0x900 0x00020000>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-gamut = <0x1000 0x00040003>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { + compatible = "qcom,dsi-ctrl-hw-v2.7"; + label = "dsi-ctrl-0"; + cell-index = <0>; + frame-threshold-time-us = <800>; + reg = <0xae94000 0x1000>, + <0xaf0f000 0x4>, + <0x0ae36000 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <16800>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae95500 { + compatible = "qcom,dsi-phy-v5.2"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0xae95000 0xa00>, + <0xae95500 0x400>, + <0xae94200 0xa0>; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; + pll-label = "dsi_pll_4nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <98400>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + dsi_pll_codes_data:dsi_pll_codes { + reg = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + label = "dsi_pll_codes"; + }; +}; diff --git a/display/crow-sde.dts b/display/crow-sde.dts new file mode 100644 index 00000000..cf38e39b --- /dev/null +++ b/display/crow-sde.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "crow-sde.dtsi" + +/ { + qcom,msm-id = <608 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/display/crow-sde.dtsi b/display/crow-sde.dtsi new file mode 100644 index 00000000..24c03bab --- /dev/null +++ b/display/crow-sde.dtsi @@ -0,0 +1,116 @@ +#include +#include +#include +#include +#include +#include +#include "crow-sde-common.dtsi" + +&soc { + sde_rscc: qcom,sde_rscc@af20000 { + cell-index = <0>; + compatible = "qcom,sde-rsc"; + status = "disabled"; + reg = <0xaf20000 0x4d68>, + <0xaf30000 0x3fd4>; + reg-names = "drv", "wrapper"; + qcom,sde-rsc-version = <5>; + + qcom,sde-dram-channels = <2>; + + vdd-supply = <&disp_cc_mdss_core_gdsc>; + clocks = <&dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>, + <&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>; + clock-names = "vsync_clk", "gdsc_clk", "iface_clk"; + + qcom,msm-bus,active-only; + interconnects = + <&mmss_noc MASTER_MDP_DISP &mc_virt SLAVE_EBI1_DISP>; + interconnect-names = "qcom,sde-data-bus0"; + }; + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x1c00 0x2>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + dma-coherent; + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x1c01 0x0>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + }; +}; + +&mdss_mdp { + clocks = + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "gcc_bus", + "iface_clk", "branch_clk", "core_clk", "vsync_clk", + "lut_clk"; + clock-rate = <0 0 520000000 520000000 19200000 520000000>; + clock-max-rate = <0 0 520000000 520000000 19200000 520000000>; + vdd-supply = <&disp_cc_mdss_core_gdsc>; + + /* data and reg bus scale settings */ + interconnects = <&mmss_noc MASTER_MDP &gem_noc SLAVE_LLCC>, + <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", + "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; + + qcom,sde-ib-bw-vote = <2500000 0 800000>; + qcom,sde-has-idle-pc; + qcom,sde-dspp-ltm-version = <0x00010002>; + /* offsets are based off dspp 0 and 1 */ + qcom,sde-dspp-ltm-off = <0x15300 0x14300>; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; +}; + +&mdss_dsi0 { + vdda-1p2-supply = <&L4B>; + qcom,split-link-supported; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&L2B>; + qcom,panel-allow-phy-poweroff; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + pll_codes_region = <&dsi_pll_codes_data>; + +}; From e821575a5e4b0314787c67aed82c9d3df0ab2d97 Mon Sep 17 00:00:00 2001 From: Anand Tarakh Date: Mon, 22 May 2023 13:22:21 +0530 Subject: [PATCH 10/46] ARM: dts: msm: enable touch support for crow target Enable touch support for crow on ATP, QRD, IDP and IDP WCD platforms. Change-Id: I9a40b983eb063fd855b5f1cf655ee1e4a722c2b9 --- display/crow-sde-display-atp.dtsi | 7 +++++++ display/crow-sde-display-idp.dtsi | 6 ++++++ 2 files changed, 13 insertions(+) diff --git a/display/crow-sde-display-atp.dtsi b/display/crow-sde-display-atp.dtsi index 98b1c464..66afdf31 100644 --- a/display/crow-sde-display-atp.dtsi +++ b/display/crow-sde-display-atp.dtsi @@ -1 +1,8 @@ #include "crow-sde-display-idp.dtsi" + +&qupv3_se0_i2c { + goodix-berlin@5d { + panel = <&dsi_vtdr6130_amoled_cmd + &dsi_vtdr6130_amoled_video>; + }; +}; diff --git a/display/crow-sde-display-idp.dtsi b/display/crow-sde-display-idp.dtsi index 52a7ba71..04b2c15f 100644 --- a/display/crow-sde-display-idp.dtsi +++ b/display/crow-sde-display-idp.dtsi @@ -74,3 +74,9 @@ qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_video>; }; +&qupv3_se0_spi { + goodix-berlin@0 { + panel = <&dsi_vtdr6130_amoled_cmd + &dsi_vtdr6130_amoled_video>; + }; +}; From 2d11ee02ba5adaa802943b81e3571240ebfa0874 Mon Sep 17 00:00:00 2001 From: Kashish Jain Date: Wed, 10 May 2023 11:42:16 +0530 Subject: [PATCH 11/46] ARM: dts: msm: add link_parent clock in DP Add link_parent clock in DP which is used by byte2_ops. Change-Id: I074fa5bf1a33e1596f2cb65bad087954e9a95799 --- display/kalama-sde.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/display/kalama-sde.dtsi b/display/kalama-sde.dtsi index f4b48d6e..d8beca73 100644 --- a/display/kalama-sde.dtsi +++ b/display/kalama-sde.dtsi @@ -57,6 +57,7 @@ <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&sde_dp 0>, <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, <&sde_dp 1>, <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, @@ -64,7 +65,7 @@ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_usb_ref_clk_src", "core_usb_pipe_clk", "link_clk", "link_clk_src", "link_iface_clk", - "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg", + "link_parent", "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; qcom,pll-revision = "4nm-v1.1"; From b4661575e250161152d94088d2da25bccd37b960 Mon Sep 17 00:00:00 2001 From: Anand Tarakh Date: Fri, 19 May 2023 14:25:14 +0530 Subject: [PATCH 12/46] ARM: dts: msm: enable compilation of display platforms for crow target Add support for rumi platform for crow. Enable compilation of ATP, QRD, RUMI, IDP and IDP WCD platform for crow target. Change-Id: I87dd8a3aa66f4c46e83ae8fe09e317ecb5e60bf4 --- Kbuild | 7 +++++- display/crow-sde-display-rumi-overlay.dts | 11 +++++++++ display/crow-sde-display-rumi.dtsi | 30 +++++++++++++++++++++++ 3 files changed, 47 insertions(+), 1 deletion(-) create mode 100644 display/crow-sde-display-rumi-overlay.dts create mode 100644 display/crow-sde-display-rumi.dtsi diff --git a/Kbuild b/Kbuild index 5a3410f7..ac432cde 100644 --- a/Kbuild +++ b/Kbuild @@ -23,7 +23,12 @@ dtbo-$(CONFIG_ARCH_KALAMA) += display/trustedvm-kalama-sde-display-mtp-overlay.d endif ifneq ($(CONFIG_ARCH_QTI_VM), y) -dtbo-$(CONFIG_ARCH_CROW) += display/crow-sde.dtbo +dtbo-$(CONFIG_ARCH_CROW) += display/crow-sde.dtbo \ + display/crow-sde-display-idp-overlay.dtbo \ + display/crow-sde-display-idp-wcd-overlay.dtbo \ + display/crow-sde-display-atp-overlay.dtbo \ + display/crow-sde-display-rumi-overlay.dtbo \ + display/crow-sde-display-qrd-overlay.dtbo endif ifeq ($(CONFIG_ARCH_SA8155), y) diff --git a/display/crow-sde-display-rumi-overlay.dts b/display/crow-sde-display-rumi-overlay.dts new file mode 100644 index 00000000..05e27166 --- /dev/null +++ b/display/crow-sde-display-rumi-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "crow-sde-display-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Crow RUMI"; + compatible = "qcom,crow-rumi", "qcom,crow", "qcom,rumi"; + qcom,msm-id = <608 0x10000>; + qcom,board-id = <15 0>; +}; diff --git a/display/crow-sde-display-rumi.dtsi b/display/crow-sde-display-rumi.dtsi new file mode 100644 index 00000000..9777a164 --- /dev/null +++ b/display/crow-sde-display-rumi.dtsi @@ -0,0 +1,30 @@ +#include "crow-sde-display.dtsi" + +&mdss_mdp { + qcom,sde-emulated-env; +}; + +&mdss_dsi0 { + qcom,dsi-phy-isolation-enabled; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_sim_vid>; + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mdp_core_clk"; +}; + +&dsi_sim_vid { + qcom,dsi-select-clocks = ""; + qcom,mdss-dsi-te-using-wd; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; +}; + +&dsi_sim_cmd { + qcom,dsi-select-clocks = ""; + /delete-property/ qcom,mdss-dsi-lane-3-state; + /delete-property/ qcom,poms-align-panel-vsync; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; +}; From 28950426a3d3b217149f94e8d71c5c69ef7b0870 Mon Sep 17 00:00:00 2001 From: Deven Solanki Date: Mon, 22 May 2023 16:46:29 +0530 Subject: [PATCH 13/46] ARM: dts: msm: add support for Kalama RCM platform Add soc ids of Kalama IoT QCS, QCM to RCM overlay. Change-Id: I5356c3ea8ce386a1a5c3adc9eb00e56f681d1c5e --- display/kalama-sde-display-rcm-overlay.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/display/kalama-sde-display-rcm-overlay.dts b/display/kalama-sde-display-rcm-overlay.dts index 43014e00..e0868ffb 100644 --- a/display/kalama-sde-display-rcm-overlay.dts +++ b/display/kalama-sde-display-rcm-overlay.dts @@ -6,6 +6,7 @@ / { model = "Qualcomm Technologies, Inc. Kalama RCM"; compatible = "qcom,kalama-rcm", "qcom,kalama", "qcom,rcm"; - qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>; + qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, + <536 0x20000>, <603 0x20000>, <604 0x20000>; qcom,board-id = <0x10015 0>; }; From 23c5cfd894a02b9bf8c6e716ff5b194694554085 Mon Sep 17 00:00:00 2001 From: Karthik Date: Tue, 9 May 2023 16:19:41 +0530 Subject: [PATCH 14/46] ARM: dts: msm: add trusted vm dt changes for crow This change includes display dt trusted vm changes for crow target. Change-Id: I98cd9ffb5657b925c076a0395743a92639d5e489 --- display/trustedvm-crow-sde.dtsi | 62 +++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 display/trustedvm-crow-sde.dtsi diff --git a/display/trustedvm-crow-sde.dtsi b/display/trustedvm-crow-sde.dtsi new file mode 100644 index 00000000..ef9daead --- /dev/null +++ b/display/trustedvm-crow-sde.dtsi @@ -0,0 +1,62 @@ +#include +#include +#include "crow-sde-common.dtsi" + +&soc { + /* dummy display clock provider */ + clock_cpucc: qcom,cpucc { + compatible = "qcom,dummycc"; + clock-output-names = "cpucc_clocks"; + #clock-cells = <1>; + }; + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x1c04 0x2>, + <&apps_smmu 0x1c03 0x0>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + dma-coherent; + }; +}; + +&mdss_mdp { + reg = <0x0ae00000 0x84000>, + <0x0aeb0000 0x2008>, + <0x0aeac000 0x800>, + <0x0ae8f000 0x02c>; + + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "sid_phys"; + + qcom,sde-vm-exclude-reg-names = "sid_phys"; + + qcom,sde-hw-version =<0x90060000>; + + clocks = <&clock_cpucc GCC_DISP_HF_AXI_CLK>, + <&clock_cpucc DISP_CC_MDSS_AHB_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "gcc_bus", "iface_clk", "branch_clk", + "core_clk", "vsync_clk", "lut_clk"; + qcom,sde-trusted-vm-env; +}; + +&mdss_dsi0 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi_phy0 { + qcom,dsi-pll-in-trusted-vm; +}; From 67b24384251634922f288694ddf485d492077e52 Mon Sep 17 00:00:00 2001 From: Soutrik Mukhopadhyay Date: Tue, 9 May 2023 15:49:50 +0530 Subject: [PATCH 15/46] ARM: dts: msm: Add DP node for crow target Changes to add a DP node for crow target. Change-Id: I760677de3a1c5b7bdf7dd6bbc94d6025af4049db --- display/crow-sde.dtsi | 145 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 145 insertions(+) diff --git a/display/crow-sde.dtsi b/display/crow-sde.dtsi index 24c03bab..4f55d3bf 100644 --- a/display/crow-sde.dtsi +++ b/display/crow-sde.dtsi @@ -7,6 +7,151 @@ #include "crow-sde-common.dtsi" &soc { + ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; + + qcom_msmhdcp: qcom,msm_hdcp { + compatible = "qcom,msm-hdcp"; + }; + + sde_dp: qcom,dp_display@ae90000 { + status = "disabled"; + cell-index = <0>; + compatible = "qcom,dp-display"; + + //usb-phy = <&usb_qmp_dp_phy>; + //qcom,dp-aux-switch = <&fsa4480>; + qcom,ext-disp = <&ext_disp>; + //qcom,altmode-dev = <&altmode 0>; + usb-controller = <&usb0>; + + reg = <0xae90000 0x0fc>, + <0xae90200 0x0c0>, + <0xae90400 0x770>, + <0xae91000 0x098>, + <0x88eaa00 0x200>, + <0x88ea200 0x200>, + <0x88ea600 0x200>, + <0x88ea000 0x200>, + <0x88e8000 0x20>, + <0x0aee1000 0x034>, + <0xae91400 0x098>, + <0xaf09000 0x14>; + reg-names = "dp_ahb", "dp_aux", "dp_link", + "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_pll", "usb3_dp_com", "hdcp_physical", + "dp_p1", "gdsc"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <12 0>; + + #clock-cells = <1>; + clocks = <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&tcsrcc TCSR_USB3_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&sde_dp 0>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&sde_dp 1>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; + clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_usb_ref_clk_src", + "core_usb_pipe_clk", "link_clk", "link_clk_src", "link_iface_clk", + "link_parent", "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg", + "strm0_pixel_clk", "strm1_pixel_clk"; + + qcom,pll-revision = "4nm-v1.1"; + qcom,phy-version = <0x600>; + qcom,aux-cfg0-settings = [20 00]; + qcom,aux-cfg1-settings = [24 13]; + qcom,aux-cfg2-settings = [28 A4]; + qcom,aux-cfg3-settings = [2c 00]; + qcom,aux-cfg4-settings = [30 0a]; + qcom,aux-cfg5-settings = [34 26]; + qcom,aux-cfg6-settings = [38 0a]; + qcom,aux-cfg7-settings = [3c 03]; + qcom,aux-cfg8-settings = [40 b7]; + qcom,aux-cfg9-settings = [44 03]; + + qcom,max-pclk-frequency-khz = <675000>; + + qcom,widebus-enable; + qcom,dsc-feature-enable; + qcom,fec-feature-enable; + qcom,dsc-continuous-pps; + + qcom,qos-cpu-mask = <0xf>; + qcom,qos-cpu-latency-us = <300>; + + vdda-1p2-supply = <&L4B>; + vdda-0p9-supply = <&L3B>; + vdda_usb-0p9-supply = <&L2B>; + vdd_mx-supply = <&VDD_MXA_LEVEL>; + dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <30100>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <912000>; + qcom,supply-max-voltage = <912000>; + qcom,supply-enable-load = <115000>; + qcom,supply-disable-load = <0>; + }; + + qcom,phy-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdda_usb-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <323000>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,pll-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,pll-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd_mx"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + sde_rscc: qcom,sde_rscc@af20000 { cell-index = <0>; compatible = "qcom,sde-rsc"; From b5a8bbc62f31bc4e20028d09b88f7a2aeca2a990 Mon Sep 17 00:00:00 2001 From: Anand Tarakh Date: Thu, 11 May 2023 14:14:52 +0530 Subject: [PATCH 16/46] ARM: dts: msm: add trustedvm display platform overlay for crow target Add trustedvm display platform overlay for crow target. Change-Id: I0d77e10ac16a6503d0523a7c60b7d233610967fa --- Kbuild | 6 ++ ...trustedvm-crow-sde-display-atp-overlay.dts | 12 ++++ display/trustedvm-crow-sde-display-atp.dtsi | 1 + ...trustedvm-crow-sde-display-idp-overlay.dts | 12 ++++ ...tedvm-crow-sde-display-idp-wcd-overlay.dts | 12 ++++ .../trustedvm-crow-sde-display-idp-wcd.dtsi | 1 + display/trustedvm-crow-sde-display-idp.dtsi | 55 +++++++++++++++++++ ...trustedvm-crow-sde-display-qrd-overlay.dts | 12 ++++ display/trustedvm-crow-sde-display-qrd.dtsi | 5 ++ ...rustedvm-crow-sde-display-rumi-overlay.dts | 12 ++++ display/trustedvm-crow-sde-display-rumi.dtsi | 13 +++++ display/trustedvm-crow-sde-display.dtsi | 12 ++++ 12 files changed, 153 insertions(+) create mode 100644 display/trustedvm-crow-sde-display-atp-overlay.dts create mode 100644 display/trustedvm-crow-sde-display-atp.dtsi create mode 100644 display/trustedvm-crow-sde-display-idp-overlay.dts create mode 100644 display/trustedvm-crow-sde-display-idp-wcd-overlay.dts create mode 100644 display/trustedvm-crow-sde-display-idp-wcd.dtsi create mode 100644 display/trustedvm-crow-sde-display-idp.dtsi create mode 100644 display/trustedvm-crow-sde-display-qrd-overlay.dts create mode 100644 display/trustedvm-crow-sde-display-qrd.dtsi create mode 100644 display/trustedvm-crow-sde-display-rumi-overlay.dts create mode 100644 display/trustedvm-crow-sde-display-rumi.dtsi create mode 100644 display/trustedvm-crow-sde-display.dtsi diff --git a/Kbuild b/Kbuild index ac432cde..c22dae65 100644 --- a/Kbuild +++ b/Kbuild @@ -29,6 +29,12 @@ dtbo-$(CONFIG_ARCH_CROW) += display/crow-sde.dtbo \ display/crow-sde-display-atp-overlay.dtbo \ display/crow-sde-display-rumi-overlay.dtbo \ display/crow-sde-display-qrd-overlay.dtbo +else +dtbo-$(CONFIG_ARCH_CROW) += display/trustedvm-crow-sde-display-idp-overlay.dtbo \ + display/trustedvm-crow-sde-display-idp-wcd-overlay.dtbo \ + display/trustedvm-crow-sde-display-atp-overlay.dtbo \ + display/trustedvm-crow-sde-display-rumi-overlay.dtbo \ + display/trustedvm-crow-sde-display-qrd-overlay.dtbo endif ifeq ($(CONFIG_ARCH_SA8155), y) diff --git a/display/trustedvm-crow-sde-display-atp-overlay.dts b/display/trustedvm-crow-sde-display-atp-overlay.dts new file mode 100644 index 00000000..dcf1c7f9 --- /dev/null +++ b/display/trustedvm-crow-sde-display-atp-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include "trustedvm-crow-sde.dtsi" +#include "trustedvm-crow-sde-display-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Crow ATP - TrustedVM"; + compatible = "qcom,crow-atp", "qcom,crow", "qcom,atp"; + qcom,msm-id = <608 0x10000>; + qcom,board-id = <33 0>; +}; diff --git a/display/trustedvm-crow-sde-display-atp.dtsi b/display/trustedvm-crow-sde-display-atp.dtsi new file mode 100644 index 00000000..f41d7801 --- /dev/null +++ b/display/trustedvm-crow-sde-display-atp.dtsi @@ -0,0 +1 @@ +#include "trustedvm-crow-sde-display-idp.dtsi" diff --git a/display/trustedvm-crow-sde-display-idp-overlay.dts b/display/trustedvm-crow-sde-display-idp-overlay.dts new file mode 100644 index 00000000..74f8d8b6 --- /dev/null +++ b/display/trustedvm-crow-sde-display-idp-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include "trustedvm-crow-sde.dtsi" +#include "trustedvm-crow-sde-display-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Crow IDP - TrustedVM"; + compatible = "qcom,crow-idp", "qcom,crow", "qcom,idp"; + qcom,msm-id = <608 0x10000>; + qcom,board-id = <34 0>; +}; diff --git a/display/trustedvm-crow-sde-display-idp-wcd-overlay.dts b/display/trustedvm-crow-sde-display-idp-wcd-overlay.dts new file mode 100644 index 00000000..dc39160b --- /dev/null +++ b/display/trustedvm-crow-sde-display-idp-wcd-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include "trustedvm-crow-sde.dtsi" +#include "trustedvm-crow-sde-display-idp-wcd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Crow IDP WCD - TrustedVM"; + compatible = "qcom,crow-idp", "qcom,crow", "qcom,idp"; + qcom,msm-id = <608 0x10000>; + qcom,board-id = <34 1>, <34 2>, <34 3>; +}; diff --git a/display/trustedvm-crow-sde-display-idp-wcd.dtsi b/display/trustedvm-crow-sde-display-idp-wcd.dtsi new file mode 100644 index 00000000..f41d7801 --- /dev/null +++ b/display/trustedvm-crow-sde-display-idp-wcd.dtsi @@ -0,0 +1 @@ +#include "trustedvm-crow-sde-display-idp.dtsi" diff --git a/display/trustedvm-crow-sde-display-idp.dtsi b/display/trustedvm-crow-sde-display-idp.dtsi new file mode 100644 index 00000000..51a9fd18 --- /dev/null +++ b/display/trustedvm-crow-sde-display-idp.dtsi @@ -0,0 +1,55 @@ +#include "trustedvm-crow-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_video>; +}; diff --git a/display/trustedvm-crow-sde-display-qrd-overlay.dts b/display/trustedvm-crow-sde-display-qrd-overlay.dts new file mode 100644 index 00000000..67531de0 --- /dev/null +++ b/display/trustedvm-crow-sde-display-qrd-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include "trustedvm-crow-sde.dtsi" +#include "trustedvm-crow-sde-display-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Crow QRD - TrustedVM"; + compatible = "qcom,crow-qrd", "qcom,crow", "qcom,qrd"; + qcom,msm-id = <608 0x10000>; + qcom,board-id = <11 0>; +}; diff --git a/display/trustedvm-crow-sde-display-qrd.dtsi b/display/trustedvm-crow-sde-display-qrd.dtsi new file mode 100644 index 00000000..58daa025 --- /dev/null +++ b/display/trustedvm-crow-sde-display-qrd.dtsi @@ -0,0 +1,5 @@ +#include "trustedvm-crow-sde-display-idp.dtsi" + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; +}; diff --git a/display/trustedvm-crow-sde-display-rumi-overlay.dts b/display/trustedvm-crow-sde-display-rumi-overlay.dts new file mode 100644 index 00000000..46176c81 --- /dev/null +++ b/display/trustedvm-crow-sde-display-rumi-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include "trustedvm-crow-sde.dtsi" +#include "trustedvm-crow-sde-display-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Crow RUMI - TrustedVM"; + compatible = "qcom,crow-rumi", "qcom,crow", "qcom,rumi"; + qcom,msm-id = <608 0x10000>; + qcom,board-id = <15 0>; +}; diff --git a/display/trustedvm-crow-sde-display-rumi.dtsi b/display/trustedvm-crow-sde-display-rumi.dtsi new file mode 100644 index 00000000..04d54ca7 --- /dev/null +++ b/display/trustedvm-crow-sde-display-rumi.dtsi @@ -0,0 +1,13 @@ +#include "trustedvm-crow-sde-display.dtsi" + +&dsi_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_sim_vid>; +}; diff --git a/display/trustedvm-crow-sde-display.dtsi b/display/trustedvm-crow-sde-display.dtsi new file mode 100644 index 00000000..7aefbb73 --- /dev/null +++ b/display/trustedvm-crow-sde-display.dtsi @@ -0,0 +1,12 @@ +#include "crow-sde-display-common.dtsi" + +&sde_dsi { + clocks = <&clock_cpucc 0>, + <&clock_cpucc 1>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0"; +}; + +&mdss_mdp { + connectors = <&sde_dsi &smmu_sde_unsec>; +}; + From a1c6def4750f496010c25ff15c1dbd6dfe1a9ec5 Mon Sep 17 00:00:00 2001 From: Anand Tarakh Date: Wed, 31 May 2023 14:37:33 +0530 Subject: [PATCH 17/46] ARM: dts: msm: update max voltage of phy supply with pmic max value Update max voltage of phy supply vdda-0p9 with pmic regulator max value. Change-Id: I79c5fcf031c728c870cb162358b96d310b017b41 --- display/crow-sde-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/crow-sde-common.dtsi b/display/crow-sde-common.dtsi index 83cfa8b2..5d659025 100644 --- a/display/crow-sde-common.dtsi +++ b/display/crow-sde-common.dtsi @@ -349,7 +349,7 @@ reg = <0>; qcom,supply-name = "vdda-0p9"; qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <880000>; + qcom,supply-max-voltage = <912000>; qcom,supply-enable-load = <98400>; qcom,supply-disable-load = <0>; }; From 5c126313bc363160c657155ac88cd95f0fd76761 Mon Sep 17 00:00:00 2001 From: Anand Tarakh Date: Thu, 4 May 2023 14:47:55 +0530 Subject: [PATCH 18/46] ARM: dts: msm: enable vtdr6130 panel features on Crow Enable vtdr6130 panel features on Crow. Change-Id: Ied67b3b3f417a99f68779f7fcc651d40cfe51f95 --- display/crow-sde-display-common.dtsi | 53 ++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/display/crow-sde-display-common.dtsi b/display/crow-sde-display-common.dtsi index 31e839a1..ecd9a686 100644 --- a/display/crow-sde-display-common.dtsi +++ b/display/crow-sde-display-common.dtsi @@ -85,30 +85,45 @@ &dsi_vtdr6130_amoled_cmd { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-dyn-clk-enable; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; qcom,display-topology = <1 1 1>; qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; }; timing@1 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; qcom,display-topology = <1 1 1>; qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; }; timing@2 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; qcom,display-topology = <1 1 1>; qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; }; timing@3 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; qcom,display-topology = <1 1 1>; qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; }; }; }; @@ -128,12 +143,32 @@ &dsi_vtdr6130_amoled_video { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-supported-dfps-list = <144 120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; + + qcom,qsync-enable; + qcom,dsi-supported-qsync-min-fps-list = <80 70 60 50>; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; qcom,display-topology = <1 1 1>; qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <847480320 844537680 841595040>; }; }; }; @@ -141,6 +176,15 @@ &dsi_vtdr6130_amoled_qsync_144hz_cmd { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 @@ -154,6 +198,15 @@ &dsi_vtdr6130_amoled_qsync_144hz_video { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 From 1e5263210167ce5511261396a3225a3136c3343c Mon Sep 17 00:00:00 2001 From: Anand Tarakh Date: Thu, 1 Jun 2023 11:51:44 +0530 Subject: [PATCH 19/46] ARM: dts: msm: add 120hz 90hz vtdr panel support in crow target Add 120hz command, 120hz video and 90hz video vtdr panel support in crow target. Change-Id: I3cea4dcab64513fa24a725239a42e712f0475759 --- display/crow-sde-display-atp.dtsi | 7 +- display/crow-sde-display-common.dtsi | 81 ++++ display/crow-sde-display-idp.dtsi | 37 +- ...panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi | 446 ++++++++++++++++++ ...nel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi | 124 +++++ ...anel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi | 124 +++++ 6 files changed, 817 insertions(+), 2 deletions(-) create mode 100644 display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi create mode 100644 display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi create mode 100644 display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi diff --git a/display/crow-sde-display-atp.dtsi b/display/crow-sde-display-atp.dtsi index 66afdf31..e2f22db3 100644 --- a/display/crow-sde-display-atp.dtsi +++ b/display/crow-sde-display-atp.dtsi @@ -3,6 +3,11 @@ &qupv3_se0_i2c { goodix-berlin@5d { panel = <&dsi_vtdr6130_amoled_cmd - &dsi_vtdr6130_amoled_video>; + &dsi_vtdr6130_amoled_video + &dsi_vtdr6130_amoled_120hz_cmd + &dsi_vtdr6130_amoled_120hz_video + &dsi_vtdr6130_amoled_qsync_144hz_cmd + &dsi_vtdr6130_amoled_qsync_144hz_video + &dsi_vtdr6130_amoled_90hz_video>; }; }; diff --git a/display/crow-sde-display-common.dtsi b/display/crow-sde-display-common.dtsi index ecd9a686..5c330ac2 100644 --- a/display/crow-sde-display-common.dtsi +++ b/display/crow-sde-display-common.dtsi @@ -7,6 +7,9 @@ #include "dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi" #include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi" #include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi" #include "crow-sde-display-pinctrl.dtsi" @@ -173,6 +176,84 @@ }; }; +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,dsi-supported-dfps-list = <120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_vtdr6130_amoled_qsync_144hz_cmd { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; diff --git a/display/crow-sde-display-idp.dtsi b/display/crow-sde-display-idp.dtsi index 04b2c15f..2732d7af 100644 --- a/display/crow-sde-display-idp.dtsi +++ b/display/crow-sde-display-idp.dtsi @@ -10,6 +10,16 @@ qcom,platform-reset-gpio = <&tlmm 127 0>; }; +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 127 0>; +}; + &dsi_vtdr6130_amoled_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -30,6 +40,26 @@ qcom,platform-reset-gpio = <&tlmm 127 0>; }; +&dsi_vtdr6130_amoled_120hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 127 0>; +}; + &dsi_vtdr6130_amoled_qsync_144hz_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -77,6 +107,11 @@ &qupv3_se0_spi { goodix-berlin@0 { panel = <&dsi_vtdr6130_amoled_cmd - &dsi_vtdr6130_amoled_video>; + &dsi_vtdr6130_amoled_video + &dsi_vtdr6130_amoled_120hz_cmd + &dsi_vtdr6130_amoled_120hz_video + &dsi_vtdr6130_amoled_qsync_144hz_cmd + &dsi_vtdr6130_amoled_qsync_144hz_video + &dsi_vtdr6130_amoled_90hz_video>; }; }; diff --git a/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi b/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi new file mode 100644 index 00000000..57c497c6 --- /dev/null +++ b/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi @@ -0,0 +1,446 @@ +&mdss_mdp { + dsi_vtdr6130_amoled_120hz_cmd: qcom,mdss_dsi_vtdr6130_fhd_plus_120hz_cmd { + qcom,mdss-dsi-panel-name = + "vtdr6130 amoled cmd mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-panel-mode-switch; + + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-cmd-mode; + qcom,mdss-dsi-video-mode; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <706233600>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 6c 01 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 ce 0a e1 0a e1 0a + 81 09 92 06 c5 00 48 00 3e 00 2b 00 + 0c 00 0c 05 00 3f + ]; + + qcom,cmd-on-commands = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 00 + 39 01 00 00 00 00 02 6c 01 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 02 65 16 + 39 01 00 00 00 00 03 EB 00 00 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 ce 0a e1 0a e1 0a + 81 09 92 06 c5 00 48 00 3e 00 2b 00 + 0c 00 0c 05 00 3f + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,vid-on-commands = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 00 + 39 01 00 00 00 00 02 6C 01 + 39 01 00 00 00 00 02 6D 00 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 5F 70 12 00 00 AB 30 + 80 09 60 04 38 00 28 02 1C 02 1C 02 + 00 02 0E 00 20 03 DD 00 07 00 0C 02 + 77 02 8B 18 00 10 F0 07 10 20 00 06 + 0F 0F 33 0E 1C 2A 38 46 54 62 69 70 + 77 79 7B 7D 7E 02 02 22 00 2A 40 2A + BE 3A FC 3A FA 3A F8 3B 38 3B 78 3B + B6 4B B6 4B F4 4B F4 6C 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 F0 AA 10 + 39 01 00 00 00 00 02 65 16 + 39 01 00 00 00 00 03 EB 00 00 + 39 01 00 00 00 00 16 B1 01 38 00 14 00 + 1C 00 01 66 00 14 00 14 00 01 66 00 + 14 05 CC 00 + 39 01 00 00 00 00 03 F0 AA 13 + 39 01 00 00 00 00 18 CE 09 11 09 11 08 + C1 07 FA 05 A4 00 3C 00 34 00 24 00 + 0C 00 0C 04 00 35 + 39 01 00 00 00 00 03 F0 AA 14 + 39 01 00 00 00 00 03 B2 03 33 + 39 01 00 00 00 00 0D B4 00 33 00 00 00 + 3E 00 00 00 3E 00 00 + 39 01 00 00 00 00 0A B5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 B9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0D BC 10 00 00 06 11 + 09 3B 09 47 09 47 00 + 39 01 00 00 00 00 0D BE 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 FF 5A 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 FA 08 08 08 + 39 01 00 00 00 00 03 FF 5A 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 F3 0F + 39 01 00 00 00 00 03 F0 AA 00 + 39 01 00 00 00 00 03 FF 5A 82 + 39 01 00 00 00 00 02 F9 00 + 39 01 00 00 00 00 03 FF 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 F8 00 + 39 01 00 00 00 00 03 FF 5A 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 F4 9A + 39 01 00 00 00 00 03 FF 5A 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,cmd-mode-switch-out-commands = [ + 39 01 00 00 00 00 02 6f 07 + ]; + qcom,cmd-mode-switch-out-commands-state = + "dsi_lp_mode"; + + qcom,video-mode-switch-in-commands = [ + 39 01 00 00 00 00 02 6f 01 + ]; + qcom,video-mode-switch-in-commands-state = + "dsi_lp_mode"; + + qcom,video-mode-switch-out-commands = [ + 39 01 00 00 00 00 02 6f 03 + 39 01 00 00 00 00 02 6f 02 + ]; + qcom,video-mode-switch-out-commands-state = + "dsi_lp_mode"; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + cell-index = <1>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <706233600>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 00 14 00 01 66 00 + 14 05 cc 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 0e 81 0e 81 0e + 01 0c c3 09 06 00 60 00 53 00 3a 00 + 0c 00 0c 07 00 54 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 00 + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 02 65 16 + 39 01 00 00 00 00 03 EB 00 00 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 00 14 00 01 66 00 + 14 05 cc 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 0e 81 0e 81 0e + 01 0c c3 09 06 00 60 00 53 00 3a 00 + 0c 00 0c 07 00 54 + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2 { + cell-index = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <706233600>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 15 c2 15 c2 15 + 02 13 25 0d 8a 00 90 00 7d 00 57 00 + 0c 00 0c 0b 00 7e + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 00 + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 02 65 16 + 39 01 00 00 00 00 03 EB 00 00 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 15 c2 15 c2 15 + 02 13 25 0d 8a 00 90 00 7d 00 57 00 + 0c 00 0c 0b 00 7e + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi b/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi new file mode 100644 index 00000000..cfce2835 --- /dev/null +++ b/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi @@ -0,0 +1,124 @@ +&mdss_mdp { + dsi_vtdr6130_amoled_120hz_video: qcom,mdss_dsi_vtdr6130_fhd_plus_120hz_vid { + qcom,mdss-dsi-panel-name = + "vtdr6130 amoled video mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 00 + 39 01 00 00 00 00 02 6C 01 + 39 01 00 00 00 00 02 6D 00 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 5F 70 12 00 00 AB 30 + 80 09 60 04 38 00 28 02 1C 02 1C 02 + 00 02 0E 00 20 03 DD 00 07 00 0C 02 + 77 02 8B 18 00 10 F0 07 10 20 00 06 + 0F 0F 33 0E 1C 2A 38 46 54 62 69 70 + 77 79 7B 7D 7E 02 02 22 00 2A 40 2A + BE 3A FC 3A FA 3A F8 3B 38 3B 78 3B + B6 4B B6 4B F4 4B F4 6C 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 F0 AA 10 + 39 01 00 00 00 00 02 65 16 + 39 01 00 00 00 00 03 EB 00 00 + 39 01 00 00 00 00 16 B1 01 38 00 14 00 + 1C 00 01 66 00 14 00 14 00 01 66 00 + 14 05 CC 00 + 39 01 00 00 00 00 03 F0 AA 13 + 39 01 00 00 00 00 18 CE 09 11 09 11 08 + C1 07 FA 05 A4 00 3C 00 34 00 24 00 + 0C 00 0C 04 00 35 + 39 01 00 00 00 00 03 F0 AA 14 + 39 01 00 00 00 00 03 B2 03 33 + 39 01 00 00 00 00 0D B4 00 33 00 00 00 + 3E 00 00 00 3E 00 00 + 39 01 00 00 00 00 0A B5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 B9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0D BC 10 00 00 06 11 + 09 3B 09 47 09 47 00 + 39 01 00 00 00 00 0D BE 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 FF 5A 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 FA 08 08 08 + 39 01 00 00 00 00 03 FF 5A 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 F3 0F + 39 01 00 00 00 00 03 F0 AA 00 + 39 01 00 00 00 00 03 FF 5A 82 + 39 01 00 00 00 00 02 F9 00 + 39 01 00 00 00 00 03 FF 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 F8 00 + 39 01 00 00 00 00 03 FF 5A 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 F4 9A + 39 01 00 00 00 00 03 FF 5A 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi b/display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi new file mode 100644 index 00000000..fe0832a5 --- /dev/null +++ b/display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi @@ -0,0 +1,124 @@ +&mdss_mdp { + dsi_vtdr6130_amoled_90hz_video: qcom,mdss_dsi_vtdr6130_fhd_plus_90hz_vid { + qcom,mdss-dsi-panel-name = + "vtdr6130 amoled video mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 00 + 39 01 00 00 00 00 02 6C 01 + 39 01 00 00 00 00 02 6D 00 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 5F 70 12 00 00 AB 30 + 80 09 60 04 38 00 28 02 1C 02 1C 02 + 00 02 0E 00 20 03 DD 00 07 00 0C 02 + 77 02 8B 18 00 10 F0 07 10 20 00 06 + 0F 0F 33 0E 1C 2A 38 46 54 62 69 70 + 77 79 7B 7D 7E 02 02 22 00 2A 40 2A + BE 3A FC 3A FA 3A F8 3B 38 3B 78 3B + B6 4B B6 4B F4 4B F4 6C 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 F0 AA 10 + 39 01 00 00 00 00 02 65 16 + 39 01 00 00 00 00 03 EB 00 00 + 39 01 00 00 00 00 16 B1 01 38 00 14 00 + 1C 00 01 66 00 14 00 14 00 01 66 00 + 14 05 CC 00 + 39 01 00 00 00 00 03 F0 AA 13 + 39 01 00 00 00 00 18 CE 09 11 09 11 08 + C1 07 FA 05 A4 00 3C 00 34 00 24 00 + 0C 00 0C 04 00 35 + 39 01 00 00 00 00 03 F0 AA 14 + 39 01 00 00 00 00 03 B2 03 33 + 39 01 00 00 00 00 0D B4 00 33 00 00 00 + 3E 00 00 00 3E 00 00 + 39 01 00 00 00 00 0A B5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 B9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0D BC 10 00 00 06 11 + 09 3B 09 47 09 47 00 + 39 01 00 00 00 00 0D BE 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 FF 5A 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 FA 08 08 08 + 39 01 00 00 00 00 03 FF 5A 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 F3 0F + 39 01 00 00 00 00 03 F0 AA 00 + 39 01 00 00 00 00 03 FF 5A 82 + 39 01 00 00 00 00 02 F9 00 + 39 01 00 00 00 00 03 FF 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 F8 00 + 39 01 00 00 00 00 03 FF 5A 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 F4 9A + 39 01 00 00 00 00 03 FF 5A 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; From 2f7b4f3f645645ac42632c88785986b1fd43e97c Mon Sep 17 00:00:00 2001 From: Anand Tarakh Date: Wed, 7 Jun 2023 16:41:45 +0530 Subject: [PATCH 20/46] ARM: dts: msm: add display support for crow IDPS platform Add display support for IDPS with Tanggu and IDPS with harmonium platform on crow target. Change-Id: Iaaba2499faa17cad9685cc345cbcb15bdf533921 --- Kbuild | 4 +- display/crow-sde-display-idp-wcd-overlay.dts | 2 +- display/crow-sde-display-idps-overlay.dts | 11 ++ display/crow-sde-display-idps-wcd-overlay.dts | 11 ++ display/crow-sde-display-idps-wcd.dtsi | 1 + display/crow-sde-display-idps.dtsi | 149 ++++++++++++++++++ 6 files changed, 176 insertions(+), 2 deletions(-) create mode 100644 display/crow-sde-display-idps-overlay.dts create mode 100644 display/crow-sde-display-idps-wcd-overlay.dts create mode 100644 display/crow-sde-display-idps-wcd.dtsi create mode 100644 display/crow-sde-display-idps.dtsi diff --git a/Kbuild b/Kbuild index c22dae65..3010a3e5 100644 --- a/Kbuild +++ b/Kbuild @@ -28,7 +28,9 @@ dtbo-$(CONFIG_ARCH_CROW) += display/crow-sde.dtbo \ display/crow-sde-display-idp-wcd-overlay.dtbo \ display/crow-sde-display-atp-overlay.dtbo \ display/crow-sde-display-rumi-overlay.dtbo \ - display/crow-sde-display-qrd-overlay.dtbo + display/crow-sde-display-qrd-overlay.dtbo \ + display/crow-sde-display-idps-overlay.dtbo \ + display/crow-sde-display-idps-wcd-overlay.dtbo else dtbo-$(CONFIG_ARCH_CROW) += display/trustedvm-crow-sde-display-idp-overlay.dtbo \ display/trustedvm-crow-sde-display-idp-wcd-overlay.dtbo \ diff --git a/display/crow-sde-display-idp-wcd-overlay.dts b/display/crow-sde-display-idp-wcd-overlay.dts index 67ab0753..8350514b 100644 --- a/display/crow-sde-display-idp-wcd-overlay.dts +++ b/display/crow-sde-display-idp-wcd-overlay.dts @@ -7,5 +7,5 @@ model = "Qualcomm Technologies, Inc. Crow IDP WCD"; compatible = "qcom,crow-idp", "qcom,crow", "qcom,idp"; qcom,msm-id = <608 0x10000>; - qcom,board-id = <34 1>, <34 2>, <34 3>; + qcom,board-id = <34 1>, <34 3>; }; diff --git a/display/crow-sde-display-idps-overlay.dts b/display/crow-sde-display-idps-overlay.dts new file mode 100644 index 00000000..4fd883a1 --- /dev/null +++ b/display/crow-sde-display-idps-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "crow-sde-display-idps.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Crow IDPS"; + compatible = "qcom,crow-idp", "qcom,crow", "qcom,idp"; + qcom,msm-id = <608 0x10000>; + qcom,board-id = <34 4>; +}; diff --git a/display/crow-sde-display-idps-wcd-overlay.dts b/display/crow-sde-display-idps-wcd-overlay.dts new file mode 100644 index 00000000..d16bf2bd --- /dev/null +++ b/display/crow-sde-display-idps-wcd-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "crow-sde-display-idps-wcd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Crow IDPS WCD"; + compatible = "qcom,crow-idp", "qcom,crow", "qcom,idp"; + qcom,msm-id = <608 0x10000>; + qcom,board-id = <34 2>; +}; diff --git a/display/crow-sde-display-idps-wcd.dtsi b/display/crow-sde-display-idps-wcd.dtsi new file mode 100644 index 00000000..f822ab5d --- /dev/null +++ b/display/crow-sde-display-idps-wcd.dtsi @@ -0,0 +1 @@ +#include "crow-sde-display-idps.dtsi" diff --git a/display/crow-sde-display-idps.dtsi b/display/crow-sde-display-idps.dtsi new file mode 100644 index 00000000..263b0f26 --- /dev/null +++ b/display/crow-sde-display-idps.dtsi @@ -0,0 +1,149 @@ +#include "crow-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 127 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@1 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@2 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@3 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + }; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 127 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@1 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@2 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + }; +}; + +&dsi_vtdr6130_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_sim_panel_au { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; +}; + +&qupv3_se0_spi { + goodix-berlin@0 { + panel = <&dsi_vtdr6130_amoled_cmd + &dsi_vtdr6130_amoled_video + &dsi_vtdr6130_amoled_120hz_cmd + &dsi_vtdr6130_amoled_120hz_video + &dsi_vtdr6130_amoled_qsync_144hz_cmd + &dsi_vtdr6130_amoled_qsync_144hz_video + &dsi_vtdr6130_amoled_90hz_video>; + }; +}; From 9a36021949adba974c6f6f2c830661a18fe9bc8e Mon Sep 17 00:00:00 2001 From: Akash Gajjar Date: Fri, 9 Jun 2023 14:16:21 +0530 Subject: [PATCH 21/46] ARM: dts: msm: update QoS table for crow target Update the QoS danger/safe/creq LUT configs and VBIF remapper configs for crow target. Change-Id: Id7f5108c7b8282f3763cfafca36a10cc51622c16 --- bindings/sde.txt | 36 +++++++++++++++++++++--------------- display/crow-sde-common.dtsi | 19 +++++++++++++------ 2 files changed, 34 insertions(+), 21 deletions(-) diff --git a/bindings/sde.txt b/bindings/sde.txt index 0b4fa143..0a006b35 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -471,24 +471,30 @@ Optional properties: - qcom,sde-downscaling-prefill-lines: A u32 value indicates the latency of downscaling in lines. - qcom,sde-max-per-pipe-bw-kbps: Array of u32 value indicates the max per pipe bandwidth in Kbps. - qcom,sde-amortizable-threshold: This value indicates the min for traffic shaping in lines. -- qcom,sde-vbif-qos-rt-remap: This u32 array is used to program vbif qos remapper register - priority for realtime clients. First 8 entries are for rp_remap and - the next 8 entries are for lvl_remap. -- qcom,sde-vbif-qos-nrt-remap: This u32 array is used to program vbif qos remapper register - priority for non-realtime clients. First 8 entries are for rp_remap and - the next 8 entries are for lvl_remap. +- qcom,sde-ddr-type: A u32 array indicates per pipe bandwidth and vbif qos + configurations for different ddr types. +- qcom,sde-vbif-qos-rt-remap: This u32 array is used to program the target vbif qos remapper + register priority for realtime clients based on ddr-type. + First 8 entries are for rp_remap and the next 8 entries are + for lvl_remap. +- qcom,sde-vbif-qos-nrt-remap: This u32 array is used to program the target vbif qos remapper + register priority for non-realtime clients based on ddr-type. + First 8 entries are for rp_remap and the next 8 entries are + for lvl_remap. - qcom,sde-vbif-qos-cwb-remap: This u32 array is used to program vbif qos remapper register - priority for concurrent writeback clients. First 8 entries are + priority for concurrent writeback clients based on ddr-type. + First 8 entries are for rp_remap and the next 8 entries are + for lvl_remap. +- qcom,sde-vbif-qos-lutdma-remap: This u32 array is used to program vbif qos remapper + register priority for lutdma client based on ddr-type. + First 8 entries are for rp_remap and the next 8 entries are + for lvl_remap. +- qcom,sde-vbif-qos-cnoc-remap: This u32 array is used to program vbif qos remapper register + priority for cnoc clients based on ddr-type. First 8 entries are for rp_remap and the next 8 entries are for lvl_remap. -- qcom,sde-vbif-qos-lutdma-remap: This u32 array is used to program vbif qos remapper register - priority for lutdma client. First 8 entries are for rp_remap and - the next 8 entries are for lvl_remap. -- qcom,sde-vbif-qos-cnoc-remap: This u32 array is used to program vbif qos remapper register - priority for cnoc clients. First 8 entries are for rp_remap and - the next 8 entries are for lvl_remap. - qcom,sde-vbif-qos-offline-wb-remap: This u32 array is used to program vbif qos remapper register - priority for offline-wb clients. First 8 entries are for rp_remap - and the next 8 entries are for lvl_remap. + priority for offline-wb clients based on ddr-type. First 8 entries + are for rp_remap and the next 8 entries are for lvl_remap. - qcom,sde-qos-refresh-rates: This u32 array indicates danger, safe and creq luts qos configuration for different refresh rates. - qcom,sde-danger-lut: This u32 array of 16 cell property, with a format of diff --git a/display/crow-sde-common.dtsi b/display/crow-sde-common.dtsi index 5d659025..c8bbb3a3 100644 --- a/display/crow-sde-common.dtsi +++ b/display/crow-sde-common.dtsi @@ -182,12 +182,19 @@ qcom,sde-vbif-default-ot-wr-limit = <32>; qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2 124416000 6 497664000 16>; - qcom,sde-vbif-qos-rt-remap = <4 4 5 5 5 5 6 6 4 4 5 5 5 5 6 6>; - qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; - qcom,sde-vbif-qos-cwb-remap = <4 4 4 4 4 5 6 6 4 4 4 4 4 5 6 6>; - qcom,sde-vbif-qos-lutdma-remap = <4 4 5 5 5 5 6 6 4 4 5 5 5 5 6 6>; - qcom,sde-vbif-qos-offline-wb-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; - qcom,sde-vbif-qos-cnoc-remap = <3 3 4 4 5 5 5 5 3 3 3 3 3 3 3 3>; + qcom,sde-ddr-type = <0x8 0x7>; + qcom,sde-vbif-qos-rt-remap = <4 4 5 5 6 6 6 6 4 4 5 5 6 6 6 6>, + <4 4 5 5 5 5 6 6 4 4 5 5 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>, + <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cwb-remap = <4 4 5 5 5 5 6 6 4 4 5 5 5 5 6 6>, + <4 4 4 4 4 5 6 6 4 4 4 4 4 5 6 6>; + qcom,sde-vbif-qos-lutdma-remap = <4 4 5 5 5 5 6 6 4 4 5 5 5 5 6 6>, + <4 4 5 5 5 5 6 6 4 4 5 5 5 5 6 6>; + qcom,sde-vbif-qos-offline-wb-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>, + <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cnoc-remap = <3 3 4 4 5 5 5 5 3 3 3 3 3 3 3 3>, + <3 3 4 4 5 5 5 5 3 3 3 3 3 3 3 3>; qcom,sde-danger-lut = <0xffff 0xffff 0xffff 0xffff 0x0 0x0 0x0 0x0 0x0 0x0 0xffff 0xffff 0xffff 0xffff 0x0 0x0>; From c48cb2b2db4ae5e260c7787dda7d1b7a3486e820 Mon Sep 17 00:00:00 2001 From: Akash Gajjar Date: Thu, 15 Jun 2023 18:02:13 +0530 Subject: [PATCH 22/46] ARM: dts: msm: update max low/high bandwidth for crow target Update the maximum low/high bandwidth value for the crow target according to the DDR type. Change-Id: Id8ff51f98a0cbb31aa8ccd067410046737865015 --- display/crow-sde-common.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/display/crow-sde-common.dtsi b/display/crow-sde-common.dtsi index 5d659025..cf481d9a 100644 --- a/display/crow-sde-common.dtsi +++ b/display/crow-sde-common.dtsi @@ -149,8 +149,8 @@ qcom,sde-has-dest-scaler; qcom,sde-max-trusted-vm-displays = <1>; - qcom,sde-max-bw-low-kbps = <5200000>; - qcom,sde-max-bw-high-kbps = <10400000>; + qcom,sde-max-bw-low-kbps = <8000000>; + qcom,sde-max-bw-high-kbps = <12600000>; qcom,sde-min-core-ib-kbps = <2500000>; qcom,sde-min-llcc-ib-kbps = <0>; qcom,sde-min-dram-ib-kbps = <800000>; From 8e7159d7a53321e8e0f255abee793f0b2b7841ec Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Fri, 9 Jun 2023 17:11:56 +0530 Subject: [PATCH 23/46] ARM: dts: msm: remove DSI split link support DSI split link is NPOR on Kalama and Crow targets. Change-Id: Ie016e7a133a46266f6bd70d1fa4cd797b9363e0a --- display/crow-sde.dtsi | 2 +- display/kalama-sde.dtsi | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/display/crow-sde.dtsi b/display/crow-sde.dtsi index 4f55d3bf..0985455b 100644 --- a/display/crow-sde.dtsi +++ b/display/crow-sde.dtsi @@ -239,7 +239,7 @@ &mdss_dsi0 { vdda-1p2-supply = <&L4B>; - qcom,split-link-supported; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, diff --git a/display/kalama-sde.dtsi b/display/kalama-sde.dtsi index d8beca73..31fa55b1 100644 --- a/display/kalama-sde.dtsi +++ b/display/kalama-sde.dtsi @@ -251,7 +251,7 @@ &mdss_dsi0 { vdda-1p2-supply = <&L3E>; - qcom,split-link-supported; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, @@ -265,7 +265,7 @@ &mdss_dsi1 { vdda-1p2-supply = <&L3E>; - qcom,split-link-supported; + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, From e585ac56e832b5f3dae75207f1c8ecfc9de504da Mon Sep 17 00:00:00 2001 From: Anand Tarakh Date: Wed, 7 Jun 2023 16:41:45 +0530 Subject: [PATCH 24/46] ARM: dts: msm: add display support for crow IDPS platform Add display support for IDPS with Tanggu and IDPS with harmonium platform on crow target. Change-Id: Iaaba2499faa17cad9685cc345cbcb15bdf533921 --- Kbuild | 4 +- display/crow-sde-display-idp-wcd-overlay.dts | 2 +- display/crow-sde-display-idps-overlay.dts | 11 ++ display/crow-sde-display-idps-wcd-overlay.dts | 11 ++ display/crow-sde-display-idps-wcd.dtsi | 1 + display/crow-sde-display-idps.dtsi | 149 ++++++++++++++++++ 6 files changed, 176 insertions(+), 2 deletions(-) create mode 100644 display/crow-sde-display-idps-overlay.dts create mode 100644 display/crow-sde-display-idps-wcd-overlay.dts create mode 100644 display/crow-sde-display-idps-wcd.dtsi create mode 100644 display/crow-sde-display-idps.dtsi diff --git a/Kbuild b/Kbuild index c22dae65..3010a3e5 100644 --- a/Kbuild +++ b/Kbuild @@ -28,7 +28,9 @@ dtbo-$(CONFIG_ARCH_CROW) += display/crow-sde.dtbo \ display/crow-sde-display-idp-wcd-overlay.dtbo \ display/crow-sde-display-atp-overlay.dtbo \ display/crow-sde-display-rumi-overlay.dtbo \ - display/crow-sde-display-qrd-overlay.dtbo + display/crow-sde-display-qrd-overlay.dtbo \ + display/crow-sde-display-idps-overlay.dtbo \ + display/crow-sde-display-idps-wcd-overlay.dtbo else dtbo-$(CONFIG_ARCH_CROW) += display/trustedvm-crow-sde-display-idp-overlay.dtbo \ display/trustedvm-crow-sde-display-idp-wcd-overlay.dtbo \ diff --git a/display/crow-sde-display-idp-wcd-overlay.dts b/display/crow-sde-display-idp-wcd-overlay.dts index 67ab0753..8350514b 100644 --- a/display/crow-sde-display-idp-wcd-overlay.dts +++ b/display/crow-sde-display-idp-wcd-overlay.dts @@ -7,5 +7,5 @@ model = "Qualcomm Technologies, Inc. Crow IDP WCD"; compatible = "qcom,crow-idp", "qcom,crow", "qcom,idp"; qcom,msm-id = <608 0x10000>; - qcom,board-id = <34 1>, <34 2>, <34 3>; + qcom,board-id = <34 1>, <34 3>; }; diff --git a/display/crow-sde-display-idps-overlay.dts b/display/crow-sde-display-idps-overlay.dts new file mode 100644 index 00000000..4fd883a1 --- /dev/null +++ b/display/crow-sde-display-idps-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "crow-sde-display-idps.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Crow IDPS"; + compatible = "qcom,crow-idp", "qcom,crow", "qcom,idp"; + qcom,msm-id = <608 0x10000>; + qcom,board-id = <34 4>; +}; diff --git a/display/crow-sde-display-idps-wcd-overlay.dts b/display/crow-sde-display-idps-wcd-overlay.dts new file mode 100644 index 00000000..d16bf2bd --- /dev/null +++ b/display/crow-sde-display-idps-wcd-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "crow-sde-display-idps-wcd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Crow IDPS WCD"; + compatible = "qcom,crow-idp", "qcom,crow", "qcom,idp"; + qcom,msm-id = <608 0x10000>; + qcom,board-id = <34 2>; +}; diff --git a/display/crow-sde-display-idps-wcd.dtsi b/display/crow-sde-display-idps-wcd.dtsi new file mode 100644 index 00000000..f822ab5d --- /dev/null +++ b/display/crow-sde-display-idps-wcd.dtsi @@ -0,0 +1 @@ +#include "crow-sde-display-idps.dtsi" diff --git a/display/crow-sde-display-idps.dtsi b/display/crow-sde-display-idps.dtsi new file mode 100644 index 00000000..263b0f26 --- /dev/null +++ b/display/crow-sde-display-idps.dtsi @@ -0,0 +1,149 @@ +#include "crow-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 127 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@1 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@2 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@3 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + }; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 127 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@1 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@2 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + }; +}; + +&dsi_vtdr6130_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_sim_panel_au { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; +}; + +&qupv3_se0_spi { + goodix-berlin@0 { + panel = <&dsi_vtdr6130_amoled_cmd + &dsi_vtdr6130_amoled_video + &dsi_vtdr6130_amoled_120hz_cmd + &dsi_vtdr6130_amoled_120hz_video + &dsi_vtdr6130_amoled_qsync_144hz_cmd + &dsi_vtdr6130_amoled_qsync_144hz_video + &dsi_vtdr6130_amoled_90hz_video>; + }; +}; From d16c1b107f7bdc08cdf1eac4a53f6fd9317c1806 Mon Sep 17 00:00:00 2001 From: Anand Tarakh Date: Thu, 22 Jun 2023 11:24:03 +0530 Subject: [PATCH 25/46] ARM: dts: msm: update display reset gpio for Crow target Update display reset gpio for Crow target. Change-Id: I32a17d7d61dcceefb07be8e2c9e990e96c176e9f --- display/crow-sde-display-idp.dtsi | 16 ++++++++-------- display/crow-sde-display-idps.dtsi | 16 ++++++++-------- display/crow-sde-display-pinctrl.dtsi | 8 ++++---- display/trustedvm-crow-sde-display-idp.dtsi | 8 ++++---- 4 files changed, 24 insertions(+), 24 deletions(-) diff --git a/display/crow-sde-display-idp.dtsi b/display/crow-sde-display-idp.dtsi index 2732d7af..6ecbf67c 100644 --- a/display/crow-sde-display-idp.dtsi +++ b/display/crow-sde-display-idp.dtsi @@ -7,7 +7,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_vtdr6130_amoled_120hz_cmd { @@ -17,7 +17,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_vtdr6130_amoled_video { @@ -27,7 +27,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_sim_panel_au { @@ -37,7 +37,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_vtdr6130_amoled_120hz_video { @@ -47,7 +47,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_vtdr6130_amoled_90hz_video { @@ -57,7 +57,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_vtdr6130_amoled_qsync_144hz_cmd { @@ -67,7 +67,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_vtdr6130_amoled_qsync_144hz_video { @@ -77,7 +77,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_sim_cmd { diff --git a/display/crow-sde-display-idps.dtsi b/display/crow-sde-display-idps.dtsi index 263b0f26..fa37ddc7 100644 --- a/display/crow-sde-display-idps.dtsi +++ b/display/crow-sde-display-idps.dtsi @@ -7,7 +7,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; qcom,mdss-dsi-display-timings { timing@0 { @@ -35,7 +35,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; qcom,mdss-dsi-display-timings { timing@0 { @@ -59,7 +59,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_sim_panel_au { @@ -69,7 +69,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_vtdr6130_amoled_120hz_video { @@ -79,7 +79,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_vtdr6130_amoled_90hz_video { @@ -89,7 +89,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_vtdr6130_amoled_qsync_144hz_cmd { @@ -99,7 +99,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_vtdr6130_amoled_qsync_144hz_video { @@ -109,7 +109,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_sim_cmd { diff --git a/display/crow-sde-display-pinctrl.dtsi b/display/crow-sde-display-pinctrl.dtsi index 3361c2b0..08a16f92 100644 --- a/display/crow-sde-display-pinctrl.dtsi +++ b/display/crow-sde-display-pinctrl.dtsi @@ -2,12 +2,12 @@ pmx_sde: pmx_sde { sde_dsi_active: sde_dsi_active { mux { - pins = "gpio127"; + pins = "gpio29"; function = "gpio"; }; config { - pins = "gpio127"; + pins = "gpio29"; drive-strength = <8>; /* 8 mA */ bias-disable = <0>; /* no pull */ }; @@ -15,12 +15,12 @@ sde_dsi_suspend: sde_dsi_suspend { mux { - pins = "gpio127"; + pins = "gpio29"; function = "gpio"; }; config { - pins = "gpio127"; + pins = "gpio29"; drive-strength = <2>; /* 2 mA */ bias-pull-down; /* PULL DOWN */ }; diff --git a/display/trustedvm-crow-sde-display-idp.dtsi b/display/trustedvm-crow-sde-display-idp.dtsi index 51a9fd18..0419d8fa 100644 --- a/display/trustedvm-crow-sde-display-idp.dtsi +++ b/display/trustedvm-crow-sde-display-idp.dtsi @@ -7,7 +7,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_vtdr6130_amoled_video { @@ -17,7 +17,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_vtdr6130_amoled_qsync_144hz_cmd { @@ -26,7 +26,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_vtdr6130_amoled_qsync_144hz_video { @@ -35,7 +35,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_sim_cmd { From 00fe631d67bc51660fae30278cc05f3dc46d77b6 Mon Sep 17 00:00:00 2001 From: Anand Tarakh Date: Fri, 23 Jun 2023 16:46:42 +0530 Subject: [PATCH 26/46] ARM: dts: msm: update default panel to vtdr6130 command for Crow Update default panel to vtdr6130 command on idp platform for Crow Change-Id: If573b818e8262f9bf9f5f6c60998bd1ed0a9e514 --- display/crow-sde-display-idp.dtsi | 2 +- display/trustedvm-crow-sde-display-idp.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/display/crow-sde-display-idp.dtsi b/display/crow-sde-display-idp.dtsi index 2732d7af..7d4f803d 100644 --- a/display/crow-sde-display-idp.dtsi +++ b/display/crow-sde-display-idp.dtsi @@ -101,7 +101,7 @@ }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_video>; + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; }; &qupv3_se0_spi { diff --git a/display/trustedvm-crow-sde-display-idp.dtsi b/display/trustedvm-crow-sde-display-idp.dtsi index 51a9fd18..83a7c54e 100644 --- a/display/trustedvm-crow-sde-display-idp.dtsi +++ b/display/trustedvm-crow-sde-display-idp.dtsi @@ -51,5 +51,5 @@ }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_video>; + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; }; From a1e6091a0b0e05b521a9e63bd1c1182cb3c4bc6c Mon Sep 17 00:00:00 2001 From: Anand Tarakh Date: Thu, 22 Jun 2023 11:24:03 +0530 Subject: [PATCH 27/46] ARM: dts: msm: update display reset gpio for Crow target Update display reset gpio for Crow target. Change-Id: I32a17d7d61dcceefb07be8e2c9e990e96c176e9f --- display/crow-sde-display-idp.dtsi | 16 ++++++++-------- display/crow-sde-display-idps.dtsi | 16 ++++++++-------- display/crow-sde-display-pinctrl.dtsi | 8 ++++---- display/trustedvm-crow-sde-display-idp.dtsi | 8 ++++---- 4 files changed, 24 insertions(+), 24 deletions(-) diff --git a/display/crow-sde-display-idp.dtsi b/display/crow-sde-display-idp.dtsi index 2732d7af..6ecbf67c 100644 --- a/display/crow-sde-display-idp.dtsi +++ b/display/crow-sde-display-idp.dtsi @@ -7,7 +7,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_vtdr6130_amoled_120hz_cmd { @@ -17,7 +17,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_vtdr6130_amoled_video { @@ -27,7 +27,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_sim_panel_au { @@ -37,7 +37,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_vtdr6130_amoled_120hz_video { @@ -47,7 +47,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_vtdr6130_amoled_90hz_video { @@ -57,7 +57,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_vtdr6130_amoled_qsync_144hz_cmd { @@ -67,7 +67,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_vtdr6130_amoled_qsync_144hz_video { @@ -77,7 +77,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_sim_cmd { diff --git a/display/crow-sde-display-idps.dtsi b/display/crow-sde-display-idps.dtsi index 263b0f26..fa37ddc7 100644 --- a/display/crow-sde-display-idps.dtsi +++ b/display/crow-sde-display-idps.dtsi @@ -7,7 +7,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; qcom,mdss-dsi-display-timings { timing@0 { @@ -35,7 +35,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; qcom,mdss-dsi-display-timings { timing@0 { @@ -59,7 +59,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_sim_panel_au { @@ -69,7 +69,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_vtdr6130_amoled_120hz_video { @@ -79,7 +79,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_vtdr6130_amoled_90hz_video { @@ -89,7 +89,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_vtdr6130_amoled_qsync_144hz_cmd { @@ -99,7 +99,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_vtdr6130_amoled_qsync_144hz_video { @@ -109,7 +109,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_sim_cmd { diff --git a/display/crow-sde-display-pinctrl.dtsi b/display/crow-sde-display-pinctrl.dtsi index 3361c2b0..08a16f92 100644 --- a/display/crow-sde-display-pinctrl.dtsi +++ b/display/crow-sde-display-pinctrl.dtsi @@ -2,12 +2,12 @@ pmx_sde: pmx_sde { sde_dsi_active: sde_dsi_active { mux { - pins = "gpio127"; + pins = "gpio29"; function = "gpio"; }; config { - pins = "gpio127"; + pins = "gpio29"; drive-strength = <8>; /* 8 mA */ bias-disable = <0>; /* no pull */ }; @@ -15,12 +15,12 @@ sde_dsi_suspend: sde_dsi_suspend { mux { - pins = "gpio127"; + pins = "gpio29"; function = "gpio"; }; config { - pins = "gpio127"; + pins = "gpio29"; drive-strength = <2>; /* 2 mA */ bias-pull-down; /* PULL DOWN */ }; diff --git a/display/trustedvm-crow-sde-display-idp.dtsi b/display/trustedvm-crow-sde-display-idp.dtsi index 51a9fd18..0419d8fa 100644 --- a/display/trustedvm-crow-sde-display-idp.dtsi +++ b/display/trustedvm-crow-sde-display-idp.dtsi @@ -7,7 +7,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_vtdr6130_amoled_video { @@ -17,7 +17,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_vtdr6130_amoled_qsync_144hz_cmd { @@ -26,7 +26,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_vtdr6130_amoled_qsync_144hz_video { @@ -35,7 +35,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; - qcom,platform-reset-gpio = <&tlmm 127 0>; + qcom,platform-reset-gpio = <&tlmm 29 0>; }; &dsi_sim_cmd { From 641f70494175e1b21dd5ac4b42b8b2c658e3df90 Mon Sep 17 00:00:00 2001 From: Anand Tarakh Date: Sat, 24 Jun 2023 16:11:08 +0530 Subject: [PATCH 28/46] ARM: dts: msm: remove unsupported timings from cmd sim panels on crow Crow supports maximum resolution of WQHD, FHD+ and maximum FPS of 180. Remove all timings with unsupported resolutions and frame rates from command mode sim panels. This will otherwise lead to Surface Flinger failures. Change-Id: I7dc81bb7700d8fe03332ba6e60508109874ad233 --- display/crow-sde-display-common.dtsi | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/display/crow-sde-display-common.dtsi b/display/crow-sde-display-common.dtsi index 5c330ac2..c752914e 100644 --- a/display/crow-sde-display-common.dtsi +++ b/display/crow-sde-display-common.dtsi @@ -349,14 +349,10 @@ qcom,default-topology-index = <0>; }; - timing@6 { /* FHD+ 240 FPS cmd mode*/ - qcom,mdss-dsi-panel-phy-timings = [00 89 26 27 42 39 25 - 27 1f 02 04 00 69 2a]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; + /delete-node/ timing@6; /* FHD+ 240 FPS cmd mode*/ timing@7 { /* FHD+ 120FPS cmd mode*/ + cell-index = <6>; qcom,mdss-dsi-panel-phy-timings = [00 4a 13 14 28 24 12 14 11 02 04 00 39 18]; qcom,display-topology = <1 1 1>, @@ -365,6 +361,7 @@ }; timing@8 { /* FHD+ 1FPS cmd mode*/ + cell-index = <7>; qcom,mdss-dsi-panel-phy-timings = [03 04 00 00 0d 18 01 00 01 02 04 00 05 05]; qcom,display-topology = <1 1 1>, @@ -373,6 +370,7 @@ }; timing@9 { /* FHD+ 5FPS cmd mode*/ + cell-index = <8>; qcom,mdss-dsi-panel-phy-timings = [03 06 00 00 0d 1a 01 00 01 02 04 00 06 05]; qcom,display-topology = <1 1 1>, @@ -381,6 +379,7 @@ }; timing@10 { /* FHD+ 10FPS cmd mode*/ + cell-index = <9>; qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01 01 01 02 04 00 07 06]; qcom,display-topology = <1 1 1>, @@ -389,6 +388,7 @@ }; timing@11 { /* FHD+ 24FPS cmd mode*/ + cell-index = <10>; qcom,mdss-dsi-panel-phy-timings = [00 09 01 01 0e 1b 02 01 01 02 04 00 08 06]; qcom,display-topology = <1 1 1>, @@ -397,6 +397,7 @@ }; timing@12 { /* FHD+ 30FPS cmd mode*/ + cell-index = <11>; qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 0e 1b 02 02 01 02 04 00 09 07]; qcom,display-topology = <1 1 1>, @@ -405,6 +406,7 @@ }; timing@13 { /* FHD+ 144FPS cmd mode*/ + cell-index = <12>; qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 06 07 02 04 00 16 0b]; qcom,display-topology = <1 1 1>, @@ -485,14 +487,10 @@ qcom,default-topology-index = <0>; }; - timing@4 { /* FHD+ 240FPS cmd mode*/ - qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a - 0b 0a 02 04 00 21 0f]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; + /delete-node/ timing@4; /* FHD+ 240FPS cmd mode*/ timing@5 { /* FHD+ 120FPS cmd mode*/ + cell-index = <4>; qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06 06 06 02 04 00 13 0b]; qcom,display-topology = <2 2 1>; @@ -500,6 +498,7 @@ }; timing@6 { /* FHD+ 1FPS cmd mode*/ + cell-index = <5>; qcom,mdss-dsi-panel-phy-timings = [03 04 00 00 0d 18 01 00 01 02 04 00 05 05]; qcom,display-topology = <1 1 1>, @@ -508,6 +507,7 @@ }; timing@7 { /* FHD+ 10FPS cmd mode*/ + cell-index = <6>; qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01 01 01 02 04 00 07 06]; qcom,display-topology = <1 1 1>, @@ -516,6 +516,7 @@ }; timing@8 { /* FHD+ 24FPS cmd mode*/ + cell-index = <7>; qcom,mdss-dsi-panel-phy-timings = [00 09 01 01 0e 1b 02 01 01 02 04 00 08 06]; qcom,display-topology = <1 1 1>, @@ -524,6 +525,7 @@ }; timing@9 { /* FHD+ 30FPS cmd mode*/ + cell-index = <8>; qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 0e 1b 02 02 01 02 04 00 09 07]; qcom,display-topology = <1 1 1>, @@ -532,6 +534,7 @@ }; timing@10 { /* FHD+ 90FPS cmd mode*/ + cell-index = <9>; qcom,mdss-dsi-panel-phy-timings = [00 39 0f 0e 21 2a 0e 0f 0d 02 04 00 2d 13]; qcom,display-topology = <2 2 1>; @@ -539,6 +542,7 @@ }; timing@11 { /* FHD+ 144FPS cmd mode*/ + cell-index = <10>; qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 06 07 02 04 00 16 0b]; qcom,display-topology = <2 2 1>; From 2c708417f8ace11f655787c83f3106e338eb26fd Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Fri, 23 Jun 2023 17:15:02 +0530 Subject: [PATCH 29/46] ARM: dts: msm: reserve memory region for continuous splash This change reserves memory region to enable continuous splash on crow target. Change-Id: Ie443e7205cdeb51f1b7a86beb352a988c6aa076b --- display/crow-sde-display.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/display/crow-sde-display.dtsi b/display/crow-sde-display.dtsi index 686a670f..0b98ad0d 100644 --- a/display/crow-sde-display.dtsi +++ b/display/crow-sde-display.dtsi @@ -9,6 +9,13 @@ }; }; +&reserved_memory { + splash_memory: splash_region { + reg = <0x0 0xb8000000 0x0 0x02b00000>; + label = "cont_splash_region"; + }; +}; + &sde_dsi { clocks = <&mdss_dsi_phy0 0>, <&mdss_dsi_phy0 1>, From 403f1f2dc1c2f8fe4b93a48c35cca9636510f848 Mon Sep 17 00:00:00 2001 From: Anand Tarakh Date: Tue, 27 Jun 2023 15:32:52 +0530 Subject: [PATCH 30/46] ARM: dts: msm: update display topology to 221 for vtdr6130 panel on Crow Update display topology to 221 for vtdr6130 panel on Crow target. Change-Id: Ib812fd114622d8fdeeced80363fe501d3e14b222 --- display/crow-sde-display-common.dtsi | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/display/crow-sde-display-common.dtsi b/display/crow-sde-display-common.dtsi index c752914e..124f8ef8 100644 --- a/display/crow-sde-display-common.dtsi +++ b/display/crow-sde-display-common.dtsi @@ -103,28 +103,28 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <1 1 1>; + qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; }; timing@1 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <1 1 1>; + qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; }; timing@2 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <1 1 1>; + qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; }; timing@3 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <1 1 1>; + qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; }; @@ -169,7 +169,7 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <1 1 1>; + qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; qcom,dsi-dyn-clk-list = <847480320 844537680 841595040>; }; @@ -190,21 +190,21 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 06 07 02 04 00 16 0b]; - qcom,display-topology = <1 1 1>; + qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; timing@1 { qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 06 07 02 04 00 16 0b]; - qcom,display-topology = <1 1 1>; + qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; timing@2 { qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 06 07 02 04 00 16 0b]; - qcom,display-topology = <1 1 1>; + qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; }; @@ -228,7 +228,7 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 06 07 02 04 00 16 0b]; - qcom,display-topology = <1 1 1>; + qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; }; @@ -248,7 +248,7 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 05 06 02 04 00 12 0a]; - qcom,display-topology = <1 1 1>; + qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; }; @@ -270,7 +270,7 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <1 1 1>; + qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; }; @@ -292,7 +292,7 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <1 1 1>; + qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; }; From 6dde1104373a6475d72349b13e85a323faec5450 Mon Sep 17 00:00:00 2001 From: Kashish Jain Date: Sat, 1 Jul 2023 23:24:38 +0530 Subject: [PATCH 31/46] ARM: dts: msm: change to enable dp on crow target Change to enable dp on crow target. Change-Id: Ic760d0afb4284206d258a4679909c6b36749784b --- display/crow-sde-display-idp-wcd.dtsi | 4 ++++ display/crow-sde-display-idp.dtsi | 4 ++++ display/crow-sde-display-idps-wcd.dtsi | 4 ++++ display/crow-sde-display-idps.dtsi | 4 ++++ display/crow-sde-display-rumi.dtsi | 4 ++++ display/crow-sde-display.dtsi | 2 +- display/crow-sde.dtsi | 8 +++----- 7 files changed, 24 insertions(+), 6 deletions(-) diff --git a/display/crow-sde-display-idp-wcd.dtsi b/display/crow-sde-display-idp-wcd.dtsi index 98b1c464..7dedb896 100644 --- a/display/crow-sde-display-idp-wcd.dtsi +++ b/display/crow-sde-display-idp-wcd.dtsi @@ -1 +1,5 @@ #include "crow-sde-display-idp.dtsi" + +&sde_dp { + qcom,dp-aux-switch = <&wcd_usbss>; +}; diff --git a/display/crow-sde-display-idp.dtsi b/display/crow-sde-display-idp.dtsi index 4a04992e..3f07c708 100644 --- a/display/crow-sde-display-idp.dtsi +++ b/display/crow-sde-display-idp.dtsi @@ -1,5 +1,9 @@ #include "crow-sde-display.dtsi" +&sde_dp { + qcom,dp-aux-switch = <&fsa4480>; +}; + &dsi_vtdr6130_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/crow-sde-display-idps-wcd.dtsi b/display/crow-sde-display-idps-wcd.dtsi index f822ab5d..45056c4f 100644 --- a/display/crow-sde-display-idps-wcd.dtsi +++ b/display/crow-sde-display-idps-wcd.dtsi @@ -1 +1,5 @@ #include "crow-sde-display-idps.dtsi" + +&sde_dp { + qcom,dp-aux-switch = <&wcd_usbss>; +}; diff --git a/display/crow-sde-display-idps.dtsi b/display/crow-sde-display-idps.dtsi index fa37ddc7..782912ff 100644 --- a/display/crow-sde-display-idps.dtsi +++ b/display/crow-sde-display-idps.dtsi @@ -1,5 +1,9 @@ #include "crow-sde-display.dtsi" +&sde_dp { + qcom,dp-aux-switch = <&fsa4480>; +}; + &dsi_vtdr6130_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/crow-sde-display-rumi.dtsi b/display/crow-sde-display-rumi.dtsi index 9777a164..9ea7a1cf 100644 --- a/display/crow-sde-display-rumi.dtsi +++ b/display/crow-sde-display-rumi.dtsi @@ -2,8 +2,12 @@ &mdss_mdp { qcom,sde-emulated-env; + connectors = <&sde_dsi &smmu_sde_unsec &smmu_sde_sec &sde_wb>; }; +&sde_dp { + status="disabled"; +}; &mdss_dsi0 { qcom,dsi-phy-isolation-enabled; }; diff --git a/display/crow-sde-display.dtsi b/display/crow-sde-display.dtsi index 0b98ad0d..afc78610 100644 --- a/display/crow-sde-display.dtsi +++ b/display/crow-sde-display.dtsi @@ -43,7 +43,7 @@ }; &mdss_mdp { - connectors = <&sde_dsi &smmu_sde_unsec &smmu_sde_sec &sde_wb>; + connectors = <&sde_dsi &smmu_sde_unsec &smmu_sde_sec &sde_wb &sde_dp>; }; &dsi_vtdr6130_amoled_cmd { diff --git a/display/crow-sde.dtsi b/display/crow-sde.dtsi index 0985455b..413ce0a6 100644 --- a/display/crow-sde.dtsi +++ b/display/crow-sde.dtsi @@ -20,14 +20,12 @@ }; sde_dp: qcom,dp_display@ae90000 { - status = "disabled"; cell-index = <0>; compatible = "qcom,dp-display"; - //usb-phy = <&usb_qmp_dp_phy>; - //qcom,dp-aux-switch = <&fsa4480>; + usb-phy = <&usb_qmp_dp_phy>; qcom,ext-disp = <&ext_disp>; - //qcom,altmode-dev = <&altmode 0>; + qcom,altmode-dev = <&altmode 0>; usb-controller = <&usb0>; reg = <0xae90000 0x0fc>, @@ -69,7 +67,7 @@ "link_parent", "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; - qcom,pll-revision = "4nm-v1.1"; + qcom,pll-revision = "4nm-v1"; qcom,phy-version = <0x600>; qcom,aux-cfg0-settings = [20 00]; qcom,aux-cfg1-settings = [24 13]; From 80735f8464e62faf53cc852b2895167c1c71489d Mon Sep 17 00:00:00 2001 From: Anand Tarakh Date: Mon, 3 Jul 2023 17:16:13 +0530 Subject: [PATCH 32/46] ARM: dts: msm: enable ulps for vtdr6130 120hz panel on crow Enable ulps for vtdr6130 120hz command mode panel on crow target. Change-Id: I5a6d2cad9760a619a13cca913bb6ea8dfe444529 --- display/crow-sde-display.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/display/crow-sde-display.dtsi b/display/crow-sde-display.dtsi index 0b98ad0d..2b29f1c5 100644 --- a/display/crow-sde-display.dtsi +++ b/display/crow-sde-display.dtsi @@ -75,6 +75,10 @@ qcom,ulps-enabled; }; +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,ulps-enabled; +}; + &dsi_sim_cmd { qcom,ulps-enabled; qcom,mdss-dsi-display-timings { From 97e49c1e265ee0bc11daa988ced9bc8061b3da55 Mon Sep 17 00:00:00 2001 From: SAMPURNA BOLLOJU Date: Mon, 3 Jul 2023 19:20:15 +0530 Subject: [PATCH 33/46] ARM: dts: msm: enable sde rscc on crow target This change enables sde rscc on crow target. Change-Id: I15c47e2e8dc480d59b877d16477b1a35f17de9e2 --- display/crow-sde-display.dtsi | 2 +- display/crow-sde.dtsi | 21 ++++++--------------- display/trustedvm-crow-sde.dtsi | 2 ++ 3 files changed, 9 insertions(+), 16 deletions(-) diff --git a/display/crow-sde-display.dtsi b/display/crow-sde-display.dtsi index afc78610..4b4955d8 100644 --- a/display/crow-sde-display.dtsi +++ b/display/crow-sde-display.dtsi @@ -43,7 +43,7 @@ }; &mdss_mdp { - connectors = <&sde_dsi &smmu_sde_unsec &smmu_sde_sec &sde_wb &sde_dp>; + connectors = <&sde_dsi &smmu_sde_unsec &smmu_sde_sec &sde_wb &sde_dp &sde_rscc>; }; &dsi_vtdr6130_amoled_cmd { diff --git a/display/crow-sde.dtsi b/display/crow-sde.dtsi index 413ce0a6..5060ee94 100644 --- a/display/crow-sde.dtsi +++ b/display/crow-sde.dtsi @@ -153,8 +153,7 @@ sde_rscc: qcom,sde_rscc@af20000 { cell-index = <0>; compatible = "qcom,sde-rsc"; - status = "disabled"; - reg = <0xaf20000 0x4d68>, + reg = <0xaf20000 0x4d6c>, <0xaf30000 0x3fd4>; reg-names = "drv", "wrapper"; qcom,sde-rsc-version = <5>; @@ -204,7 +203,6 @@ "lut_clk"; clock-rate = <0 0 520000000 520000000 19200000 520000000>; clock-max-rate = <0 0 520000000 520000000 19200000 520000000>; - vdd-supply = <&disp_cc_mdss_core_gdsc>; /* data and reg bus scale settings */ interconnects = <&mmss_noc MASTER_MDP &gem_noc SLAVE_LLCC>, @@ -219,19 +217,12 @@ qcom,sde-dspp-ltm-version = <0x00010002>; /* offsets are based off dspp 0 and 1 */ qcom,sde-dspp-ltm-off = <0x15300 0x14300>; +}; - qcom,platform-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,platform-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdd"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; +&disp_rsc_drv0 { + sde_rsc_rpmh { + compatible = "qcom,sde-rsc-rpmh"; + cell-index = <0>; }; }; diff --git a/display/trustedvm-crow-sde.dtsi b/display/trustedvm-crow-sde.dtsi index ef9daead..e1e836f1 100644 --- a/display/trustedvm-crow-sde.dtsi +++ b/display/trustedvm-crow-sde.dtsi @@ -32,6 +32,8 @@ "sid_phys"; qcom,sde-vm-exclude-reg-names = "sid_phys"; + qcom,tvm-include-reg = <0xaf20000 0x4d6c>, + <0xaf30000 0x3fd4>; qcom,sde-hw-version =<0x90060000>; From 7ec6c1176fb2a81a33dce0c74756505f38414c02 Mon Sep 17 00:00:00 2001 From: Anand Tarakh Date: Tue, 27 Jun 2023 15:32:52 +0530 Subject: [PATCH 34/46] ARM: dts: msm: update display topology to 221 for vtdr6130 panel on Crow Update display topology to 221 for vtdr6130 panel on Crow target. Change-Id: Ib812fd114622d8fdeeced80363fe501d3e14b222 --- display/crow-sde-display-common.dtsi | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/display/crow-sde-display-common.dtsi b/display/crow-sde-display-common.dtsi index c752914e..124f8ef8 100644 --- a/display/crow-sde-display-common.dtsi +++ b/display/crow-sde-display-common.dtsi @@ -103,28 +103,28 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <1 1 1>; + qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; }; timing@1 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <1 1 1>; + qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; }; timing@2 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <1 1 1>; + qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; }; timing@3 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <1 1 1>; + qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; }; @@ -169,7 +169,7 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <1 1 1>; + qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; qcom,dsi-dyn-clk-list = <847480320 844537680 841595040>; }; @@ -190,21 +190,21 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 06 07 02 04 00 16 0b]; - qcom,display-topology = <1 1 1>; + qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; timing@1 { qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 06 07 02 04 00 16 0b]; - qcom,display-topology = <1 1 1>; + qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; timing@2 { qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 06 07 02 04 00 16 0b]; - qcom,display-topology = <1 1 1>; + qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; }; @@ -228,7 +228,7 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 06 07 02 04 00 16 0b]; - qcom,display-topology = <1 1 1>; + qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; }; @@ -248,7 +248,7 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 05 06 02 04 00 12 0a]; - qcom,display-topology = <1 1 1>; + qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; }; @@ -270,7 +270,7 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <1 1 1>; + qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; }; @@ -292,7 +292,7 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <1 1 1>; + qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; }; From 7e5960c83c279c041fdbb5825340ed56ba6aa4c5 Mon Sep 17 00:00:00 2001 From: Andhavarapu Karthik Date: Fri, 23 Jun 2023 17:15:02 +0530 Subject: [PATCH 35/46] ARM: dts: msm: reserve memory region for continuous splash This change reserves memory region to enable continuous splash on crow target. Change-Id: Ie443e7205cdeb51f1b7a86beb352a988c6aa076b --- display/crow-sde-display.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/display/crow-sde-display.dtsi b/display/crow-sde-display.dtsi index 686a670f..0b98ad0d 100644 --- a/display/crow-sde-display.dtsi +++ b/display/crow-sde-display.dtsi @@ -9,6 +9,13 @@ }; }; +&reserved_memory { + splash_memory: splash_region { + reg = <0x0 0xb8000000 0x0 0x02b00000>; + label = "cont_splash_region"; + }; +}; + &sde_dsi { clocks = <&mdss_dsi_phy0 0>, <&mdss_dsi_phy0 1>, From 92bdb9aade2dfe3f21007667eb3ea0c2cc3a0297 Mon Sep 17 00:00:00 2001 From: Kashish Jain Date: Sat, 1 Jul 2023 23:24:38 +0530 Subject: [PATCH 36/46] ARM: dts: msm: change to enable dp on crow target Change to enable dp on crow target. Change-Id: Ic760d0afb4284206d258a4679909c6b36749784b --- display/crow-sde-display-idp-wcd.dtsi | 4 ++++ display/crow-sde-display-idp.dtsi | 4 ++++ display/crow-sde-display-idps-wcd.dtsi | 4 ++++ display/crow-sde-display-idps.dtsi | 4 ++++ display/crow-sde-display-rumi.dtsi | 4 ++++ display/crow-sde-display.dtsi | 2 +- display/crow-sde.dtsi | 8 +++----- 7 files changed, 24 insertions(+), 6 deletions(-) diff --git a/display/crow-sde-display-idp-wcd.dtsi b/display/crow-sde-display-idp-wcd.dtsi index 98b1c464..7dedb896 100644 --- a/display/crow-sde-display-idp-wcd.dtsi +++ b/display/crow-sde-display-idp-wcd.dtsi @@ -1 +1,5 @@ #include "crow-sde-display-idp.dtsi" + +&sde_dp { + qcom,dp-aux-switch = <&wcd_usbss>; +}; diff --git a/display/crow-sde-display-idp.dtsi b/display/crow-sde-display-idp.dtsi index 4a04992e..3f07c708 100644 --- a/display/crow-sde-display-idp.dtsi +++ b/display/crow-sde-display-idp.dtsi @@ -1,5 +1,9 @@ #include "crow-sde-display.dtsi" +&sde_dp { + qcom,dp-aux-switch = <&fsa4480>; +}; + &dsi_vtdr6130_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/crow-sde-display-idps-wcd.dtsi b/display/crow-sde-display-idps-wcd.dtsi index f822ab5d..45056c4f 100644 --- a/display/crow-sde-display-idps-wcd.dtsi +++ b/display/crow-sde-display-idps-wcd.dtsi @@ -1 +1,5 @@ #include "crow-sde-display-idps.dtsi" + +&sde_dp { + qcom,dp-aux-switch = <&wcd_usbss>; +}; diff --git a/display/crow-sde-display-idps.dtsi b/display/crow-sde-display-idps.dtsi index fa37ddc7..782912ff 100644 --- a/display/crow-sde-display-idps.dtsi +++ b/display/crow-sde-display-idps.dtsi @@ -1,5 +1,9 @@ #include "crow-sde-display.dtsi" +&sde_dp { + qcom,dp-aux-switch = <&fsa4480>; +}; + &dsi_vtdr6130_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/crow-sde-display-rumi.dtsi b/display/crow-sde-display-rumi.dtsi index 9777a164..9ea7a1cf 100644 --- a/display/crow-sde-display-rumi.dtsi +++ b/display/crow-sde-display-rumi.dtsi @@ -2,8 +2,12 @@ &mdss_mdp { qcom,sde-emulated-env; + connectors = <&sde_dsi &smmu_sde_unsec &smmu_sde_sec &sde_wb>; }; +&sde_dp { + status="disabled"; +}; &mdss_dsi0 { qcom,dsi-phy-isolation-enabled; }; diff --git a/display/crow-sde-display.dtsi b/display/crow-sde-display.dtsi index 686a670f..e66f66c4 100644 --- a/display/crow-sde-display.dtsi +++ b/display/crow-sde-display.dtsi @@ -36,7 +36,7 @@ }; &mdss_mdp { - connectors = <&sde_dsi &smmu_sde_unsec &smmu_sde_sec &sde_wb>; + connectors = <&sde_dsi &smmu_sde_unsec &smmu_sde_sec &sde_wb &sde_dp>; }; &dsi_vtdr6130_amoled_cmd { diff --git a/display/crow-sde.dtsi b/display/crow-sde.dtsi index 0985455b..413ce0a6 100644 --- a/display/crow-sde.dtsi +++ b/display/crow-sde.dtsi @@ -20,14 +20,12 @@ }; sde_dp: qcom,dp_display@ae90000 { - status = "disabled"; cell-index = <0>; compatible = "qcom,dp-display"; - //usb-phy = <&usb_qmp_dp_phy>; - //qcom,dp-aux-switch = <&fsa4480>; + usb-phy = <&usb_qmp_dp_phy>; qcom,ext-disp = <&ext_disp>; - //qcom,altmode-dev = <&altmode 0>; + qcom,altmode-dev = <&altmode 0>; usb-controller = <&usb0>; reg = <0xae90000 0x0fc>, @@ -69,7 +67,7 @@ "link_parent", "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; - qcom,pll-revision = "4nm-v1.1"; + qcom,pll-revision = "4nm-v1"; qcom,phy-version = <0x600>; qcom,aux-cfg0-settings = [20 00]; qcom,aux-cfg1-settings = [24 13]; From ea81d9022dc9f56ba1c4d5007f502fd79b080a4d Mon Sep 17 00:00:00 2001 From: Anand Tarakh Date: Tue, 11 Jul 2023 15:13:45 +0530 Subject: [PATCH 37/46] ARM: dts: msm: update default panel to vtdr6130 120hz on Crow IDPS Update default panel to vtdr6130 120hz on Crow IDPS platform. Change-Id: I0de11b285f9b6db3cbfe97c4e6fb32f1e49bc9eb --- display/crow-sde-display-idps.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/crow-sde-display-idps.dtsi b/display/crow-sde-display-idps.dtsi index 782912ff..1761a883 100644 --- a/display/crow-sde-display-idps.dtsi +++ b/display/crow-sde-display-idps.dtsi @@ -137,7 +137,7 @@ }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_120hz_cmd>; }; &qupv3_se0_spi { From e0530d81ab4af0c143386fb64d375733d452e472 Mon Sep 17 00:00:00 2001 From: Yojana Juadi Date: Tue, 18 Jul 2023 16:11:42 +0530 Subject: [PATCH 38/46] ARM: dts: msm: add ramdump display region for crow This change adds memory region node reserved for display in ramdump mode on crow target. Change-Id: I52898fd754afe2844bff4082f89f667dbae256b8 --- display/crow-sde-display.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/display/crow-sde-display.dtsi b/display/crow-sde-display.dtsi index 98ed336d..3014d4d1 100644 --- a/display/crow-sde-display.dtsi +++ b/display/crow-sde-display.dtsi @@ -7,6 +7,11 @@ cell-index = <0>; label = "wb_display"; }; + + disp_rdump_memory: disp_rdump_region@b8000000 { + reg = <0xb8000000 0x00800000>; + label = "disp_rdump_region"; + }; }; &reserved_memory { From 208d787ff4181c68bfa74d8cb45b6b002c0de2dd Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Tue, 18 Jul 2023 12:23:49 +0530 Subject: [PATCH 39/46] ARM: dts: qcom: add panel information for ECM driver for crow Add panel information in amoled-ecm device node so that the driver can receive display off/on notification and disable/re-enable ECM accordingly. Change-Id: I777b8267d06676a79e538eb39852ab97eff68c98 --- display/crow-sde-display-atp.dtsi | 12 ++++++++++++ display/crow-sde-display-idp.dtsi | 12 ++++++++++++ display/crow-sde-display-idps.dtsi | 12 ++++++++++++ 3 files changed, 36 insertions(+) diff --git a/display/crow-sde-display-atp.dtsi b/display/crow-sde-display-atp.dtsi index e2f22db3..4e7cf0e5 100644 --- a/display/crow-sde-display-atp.dtsi +++ b/display/crow-sde-display-atp.dtsi @@ -11,3 +11,15 @@ &dsi_vtdr6130_amoled_90hz_video>; }; }; + +&spmi_bus { + pm7550ba_amoled_ecm { + display-panels = <&dsi_vtdr6130_amoled_cmd + &dsi_vtdr6130_amoled_video + &dsi_vtdr6130_amoled_120hz_cmd + &dsi_vtdr6130_amoled_120hz_video + &dsi_vtdr6130_amoled_qsync_144hz_cmd + &dsi_vtdr6130_amoled_qsync_144hz_video + &dsi_vtdr6130_amoled_90hz_video>; + }; +}; diff --git a/display/crow-sde-display-idp.dtsi b/display/crow-sde-display-idp.dtsi index 3f07c708..3490c0ee 100644 --- a/display/crow-sde-display-idp.dtsi +++ b/display/crow-sde-display-idp.dtsi @@ -119,3 +119,15 @@ &dsi_vtdr6130_amoled_90hz_video>; }; }; + +&spmi_bus { + pm7550ba_amoled_ecm { + display-panels = <&dsi_vtdr6130_amoled_cmd + &dsi_vtdr6130_amoled_video + &dsi_vtdr6130_amoled_120hz_cmd + &dsi_vtdr6130_amoled_120hz_video + &dsi_vtdr6130_amoled_qsync_144hz_cmd + &dsi_vtdr6130_amoled_qsync_144hz_video + &dsi_vtdr6130_amoled_90hz_video>; + }; +}; diff --git a/display/crow-sde-display-idps.dtsi b/display/crow-sde-display-idps.dtsi index 1761a883..30cf837f 100644 --- a/display/crow-sde-display-idps.dtsi +++ b/display/crow-sde-display-idps.dtsi @@ -151,3 +151,15 @@ &dsi_vtdr6130_amoled_90hz_video>; }; }; + +&spmi_bus { + pm7550ba_amoled_ecm { + display-panels = <&dsi_vtdr6130_amoled_cmd + &dsi_vtdr6130_amoled_video + &dsi_vtdr6130_amoled_120hz_cmd + &dsi_vtdr6130_amoled_120hz_video + &dsi_vtdr6130_amoled_qsync_144hz_cmd + &dsi_vtdr6130_amoled_qsync_144hz_video + &dsi_vtdr6130_amoled_90hz_video>; + }; +}; From 92c76a59d7199429d50b18ab1fe9b17705864dd2 Mon Sep 17 00:00:00 2001 From: Anand Tarakh Date: Fri, 21 Jul 2023 12:39:19 +0530 Subject: [PATCH 40/46] ARM: dts: msm: Update power ON/OFF sequence of vtdr6130 panel on Crow Update power ON/OFF sequence for vtdr6130 panal as per panel datasheet on Crow platform. Change-Id: I2d2d80fc8601debcbf70db7bca67aa2a94e6bc0d --- display/crow-sde-display-common.dtsi | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/display/crow-sde-display-common.dtsi b/display/crow-sde-display-common.dtsi index 124f8ef8..fc0e54f4 100644 --- a/display/crow-sde-display-common.dtsi +++ b/display/crow-sde-display-common.dtsi @@ -45,22 +45,24 @@ qcom,panel-supply-entry@1 { reg = <1>; + qcom,supply-name = "vci"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <10000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <1>; + qcom,supply-post-off-sleep = <2>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; qcom,supply-name = "vdd"; qcom,supply-min-voltage = <1200000>; qcom,supply-max-voltage = <1200000>; qcom,supply-enable-load = <299000>; qcom,supply-disable-load = <0>; qcom,supply-post-on-sleep = <0>; - }; - - qcom,panel-supply-entry@2 { - reg = <2>; - qcom,supply-name = "vci"; - qcom,supply-min-voltage = <3000000>; - qcom,supply-max-voltage = <3000000>; - qcom,supply-enable-load = <10000>; - qcom,supply-disable-load = <0>; - qcom,supply-post-on-sleep = <0>; + qcom,supply-post-off-sleep = <2>; }; }; From 11e3bfef92402caf42708d2dec4a6381dc32ee09 Mon Sep 17 00:00:00 2001 From: Yojana Juadi Date: Tue, 18 Jul 2023 16:11:42 +0530 Subject: [PATCH 41/46] ARM: dts: msm: add ramdump display region for crow This change adds memory region node reserved for display in ramdump mode on crow target. Change-Id: I52898fd754afe2844bff4082f89f667dbae256b8 --- display/crow-sde-display.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/display/crow-sde-display.dtsi b/display/crow-sde-display.dtsi index 98ed336d..3014d4d1 100644 --- a/display/crow-sde-display.dtsi +++ b/display/crow-sde-display.dtsi @@ -7,6 +7,11 @@ cell-index = <0>; label = "wb_display"; }; + + disp_rdump_memory: disp_rdump_region@b8000000 { + reg = <0xb8000000 0x00800000>; + label = "disp_rdump_region"; + }; }; &reserved_memory { From cea0b29616b0667fb5141088024a345dd45d702b Mon Sep 17 00:00:00 2001 From: Anand Tarakh Date: Fri, 21 Jul 2023 12:39:19 +0530 Subject: [PATCH 42/46] ARM: dts: msm: Update power ON/OFF sequence of vtdr6130 panel on Crow Update power ON/OFF sequence for vtdr6130 panal as per panel datasheet on Crow platform. Change-Id: I2d2d80fc8601debcbf70db7bca67aa2a94e6bc0d --- display/crow-sde-display-common.dtsi | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/display/crow-sde-display-common.dtsi b/display/crow-sde-display-common.dtsi index 124f8ef8..fc0e54f4 100644 --- a/display/crow-sde-display-common.dtsi +++ b/display/crow-sde-display-common.dtsi @@ -45,22 +45,24 @@ qcom,panel-supply-entry@1 { reg = <1>; + qcom,supply-name = "vci"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <10000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <1>; + qcom,supply-post-off-sleep = <2>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; qcom,supply-name = "vdd"; qcom,supply-min-voltage = <1200000>; qcom,supply-max-voltage = <1200000>; qcom,supply-enable-load = <299000>; qcom,supply-disable-load = <0>; qcom,supply-post-on-sleep = <0>; - }; - - qcom,panel-supply-entry@2 { - reg = <2>; - qcom,supply-name = "vci"; - qcom,supply-min-voltage = <3000000>; - qcom,supply-max-voltage = <3000000>; - qcom,supply-enable-load = <10000>; - qcom,supply-disable-load = <0>; - qcom,supply-post-on-sleep = <0>; + qcom,supply-post-off-sleep = <2>; }; }; From 95605511f523c9c3f63396520e0ad6d49dd34bd0 Mon Sep 17 00:00:00 2001 From: Yojana Date: Wed, 9 Aug 2023 13:22:17 +0530 Subject: [PATCH 43/46] ARM: dts: msm: update dma addr pool for display for crow target As DMA addr pool for display unsecure context bank includes cont splah region it can be used by first commit. If we try to unmap the cont splash region after splash handoff while it is being used, SMMU faults are seen. This change leaves a hole at the cont splash in DMA address pool to avoid using this region for unsec_fbs. Change-Id: Ifc7e1875d5def8bde0b94589b37e78007a0312b6 --- display/crow-sde.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/crow-sde.dtsi b/display/crow-sde.dtsi index 5060ee94..97681ffd 100644 --- a/display/crow-sde.dtsi +++ b/display/crow-sde.dtsi @@ -175,7 +175,7 @@ smmu_sde_unsec: qcom,smmu_sde_unsec_cb { compatible = "qcom,smmu_sde_unsec"; iommus = <&apps_smmu 0x1c00 0x2>; - qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-dma-addr-pool = <0x00020000 0xb7fe0000 0xbab00000 0x45500000>; qcom,iommu-faults = "non-fatal"; qcom,iommu-earlymap; /* for cont-splash */ dma-coherent; From 0e437fb0a3084b5a3e44145aa4c2de6ddaa2ee40 Mon Sep 17 00:00:00 2001 From: Anand Tarakh Date: Wed, 16 Aug 2023 11:57:32 +0530 Subject: [PATCH 44/46] ARM: dts: msm: Enable PU for 120hz VTDR6130 panel on Crow Enable PU for 120hz VTDR6130 panel on Crow. Change-Id: Ia956ff765aaa16a073f984eda7fed5767de09d5c --- display/crow-sde-display.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/display/crow-sde-display.dtsi b/display/crow-sde-display.dtsi index 3014d4d1..0e9fc33f 100644 --- a/display/crow-sde-display.dtsi +++ b/display/crow-sde-display.dtsi @@ -82,6 +82,22 @@ &dsi_vtdr6130_amoled_120hz_cmd { qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + }; }; &dsi_sim_cmd { From f0571f6a5c9cb8d33292e58492d86eef5d5e0609 Mon Sep 17 00:00:00 2001 From: Anand Tarakh Date: Wed, 16 Aug 2023 10:51:54 +0530 Subject: [PATCH 45/46] ARM: dts: msm: Enable HDR in 120hz & 90hz vtdr6130 panel on crow Enable HDR support in 120hz & 90hz vtdr6130 panel on Crow platform. Change-Id: I4496de0f242a47176d98355ca2216eeb92a088d7 --- display/crow-sde-display-common.dtsi | 6 ++++++ display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi | 5 +++++ display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi | 5 +++++ display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi | 5 +++++ 4 files changed, 21 insertions(+) diff --git a/display/crow-sde-display-common.dtsi b/display/crow-sde-display-common.dtsi index fc0e54f4..21ffbbe3 100644 --- a/display/crow-sde-display-common.dtsi +++ b/display/crow-sde-display-common.dtsi @@ -188,6 +188,8 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 @@ -226,6 +228,8 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 @@ -246,6 +250,8 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 diff --git a/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi b/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi index 57c497c6..ad8726cf 100644 --- a/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi +++ b/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi @@ -30,6 +30,11 @@ qcom,mdss-dsi-mdp-trigger = "none"; qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,mdss-dsi-te-pin-select = <1>; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; diff --git a/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi b/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi index cfce2835..bc2c7673 100644 --- a/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi +++ b/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi @@ -23,6 +23,11 @@ qcom,mdss-dsi-mdp-trigger = "none"; qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,mdss-dsi-display-timings { diff --git a/display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi b/display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi index fe0832a5..c9d19603 100644 --- a/display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi +++ b/display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi @@ -23,6 +23,11 @@ qcom,mdss-dsi-mdp-trigger = "none"; qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,mdss-dsi-display-timings { From cb7a441f5e079fc57cd869e0d92359f6346f7fe9 Mon Sep 17 00:00:00 2001 From: Yojana Date: Tue, 5 Sep 2023 12:37:21 +0530 Subject: [PATCH 46/46] ARM: dts: msm: update UBWC version for kalama Update UBWC version supported for kalama. Change-Id: I1b341f6027b9b41ce18bbc3e4f32d3e3fac4268d (cherry picked from commit d2becead1d1410a7e88cf380d39405f64214f278) --- display/kalama-sde-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/kalama-sde-common.dtsi b/display/kalama-sde-common.dtsi index 996b1dda..fcb9f856 100644 --- a/display/kalama-sde-common.dtsi +++ b/display/kalama-sde-common.dtsi @@ -154,7 +154,7 @@ qcom,sde-mixer-blendstages = <0xb>; qcom,sde-highest-bank-bit = <0x8 0x3>, <0x7 0x2>; - qcom,sde-ubwc-version = <0x40000002>; + qcom,sde-ubwc-version = <0x40030001>; qcom,sde-ubwc-swizzle = <0x6>; qcom,sde-ubwc-bw-calc-version = <0x1>; qcom,sde-ubwc-static = <0x1>;