diff --git a/qcom/cinder-pinctrl.dtsi b/qcom/cinder-pinctrl.dtsi
index 1a970061..02c402dc 100644
--- a/qcom/cinder-pinctrl.dtsi
+++ b/qcom/cinder-pinctrl.dtsi
@@ -26,4 +26,54 @@
 			};
 		};
 	};
+
+	sdc1_on: sdc1_on {
+		clk {
+			pins = "sdc1_clk";
+			bias-disable;
+			drive-strength = <16>;
+		};
+
+		cmd {
+			pins = "sdc1_cmd";
+			bias-pull-up;
+			drive-strength = <10>;
+		};
+
+		data {
+			pins = "sdc1_data";
+			bias-pull-up;
+			drive-strength = <10>;
+		};
+
+		rclk {
+			pins = "sdc1_rclk";
+			bias-pull-down;
+		};
+	};
+
+	sdc1_off: sdc1_off {
+		clk {
+			pins = "sdc1_clk";
+			bias-disable;
+			drive-strength = <2>;
+		};
+
+		cmd {
+			pins = "sdc1_cmd";
+			bias-pull-up;
+			drive-strength = <2>;
+		};
+
+		data {
+			pins = "sdc1_data";
+			bias-pull-up;
+			drive-strength = <2>;
+		};
+
+		rclk {
+			pins = "sdc1_rclk";
+			bias-pull-down;
+		};
+	};
 };
diff --git a/qcom/cinder-rumi.dtsi b/qcom/cinder-rumi.dtsi
index 71e94a0a..7f76faf9 100644
--- a/qcom/cinder-rumi.dtsi
+++ b/qcom/cinder-rumi.dtsi
@@ -17,3 +17,27 @@
 &qupv3_se7_2uart {
 	qcom,rumi_platform;
 };
+
+&sdhc_1 {
+	status = "ok";
+	vdd-supply = <&L10A>;
+	qcom,vdd-voltage-level = <2960000 2960000>;
+	qcom,vdd-current-level = <0 570000>;
+
+	vdd-io-supply = <&L7A>;
+	qcom,vdd-io-always-on;
+	qcom,vdd-io-lpm-sup;
+	qcom,vdd-io-voltage-level = <1800000 1800000>;
+	qcom,vdd-io-current-level = <0 325000>;
+
+	/delete-property/ mmc-ddr-1_8v;
+	/delete-property/ mmc-hs200-1_8v;
+	/delete-property/ mmc-hs400-1_8v;
+	/delete-property/ mmc-hs400-enhanced-strobe;
+
+	max-frequency = <100000000>;
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc1_on>;
+	pinctrl-1 = <&sdc1_off>;
+};
diff --git a/qcom/cinder.dtsi b/qcom/cinder.dtsi
index 69b5c696..4daf977e 100644
--- a/qcom/cinder.dtsi
+++ b/qcom/cinder.dtsi
@@ -15,6 +15,7 @@
 
 	aliases {
 		serial0 = &qupv3_se7_2uart;
+		mmc0 = &sdhc_1; /*SDC1 eMMC slot*/
 	};
 
 	firmware: firmware { };
@@ -364,6 +365,53 @@
 		#mbox-cells = <1>;
 	};
 
+	sdhc_1: sdhci@8804000 {
+		status = "disabled";
+
+		compatible = "qcom,sdhci-msm-v5";
+		reg = <0x08804000 0x1000>, <0x08805000 0x1000>;
+		reg-names = "hc", "cqhci";
+
+		interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "hc_irq", "pwr_irq";
+
+		bus-width = <8>;
+		non-removable;
+		supports-cqe;
+
+		no-sd;
+		no-sdio;
+		qcom,restore-after-cx-collapse;
+
+		mmc-ddr-1_8v;
+		mmc-hs200-1_8v;
+		mmc-hs400-1_8v;
+		mmc-hs400-enhanced-strobe;
+
+		cap-mmc-hw-reset;
+
+		clocks = <&gcc GCC_SDCC5_AHB_CLK>,
+			<&gcc GCC_SDCC5_APPS_CLK>,
+			<&gcc GCC_SDCC5_ICE_CORE_CLK>;
+		clock-names = "iface", "core", "ice_core";
+
+		qcom,ice-clk-rates = <300000000 300000000>;
+
+		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
+		qcom,dll-hsr-list = <0x000F642C 0x0 0x01
+					0x2C010800 0x80040868>;
+
+		/* Add dt entry for gcc hw reset */
+		resets = <&gcc GCC_SDCC5_BCR>;
+		reset-names = "core_reset";
+
+		qos0 {
+			mask = <0x0f>;
+			vote = <44>;
+		};
+	};
+
 	qcom,chd {
 		compatible = "qcom,core-hang-detect";
 		label = "core";