diff --git a/qcom/cinder-usb.dtsi b/qcom/cinder-usb.dtsi
index 4a71b027..2a445056 100644
--- a/qcom/cinder-usb.dtsi
+++ b/qcom/cinder-usb.dtsi
@@ -106,102 +106,101 @@
 		reset-names = "phy_reset", "phy_phy_reset";
 
 		qcom,qmp-phy-init-seq =
-				/* <reg_offset, value, delay> */
-				<USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL	0x1A 0
-				USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL	0x11 0
-				USB3_UNI_QSERDES_COM_HSCLK_SEL	0x01 0
-				USB3_UNI_QSERDES_COM_DEC_START_MODE0	0x82 0
-				USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0	0xAB 0
-				USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0	0xEA 0
-				USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0	0x02 0
-				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0	0xCA 0
-				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0	0x1E 0
-				USB3_UNI_QSERDES_COM_CP_CTRL_MODE0	0x06 0
-				USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0	0x16 0
-				USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0	0x36 0
-				USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0	0x24 0
-				USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0	0x34 0
-				USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0	0x14 0
-				USB3_UNI_QSERDES_COM_LOCK_CMP_EN	0x04 0
-				USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE	0x0A 0
-				USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1	0x02 0
-				USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1	0x24 0
-				USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1	0x08 0
-				USB3_UNI_QSERDES_COM_DEC_START_MODE1	0x82 0
-				USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1	0xAB 0
-				USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1	0xEA 0
-				USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1	0x02 0
-				USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1	0x82 0
-				USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1	0x34 0
-				USB3_UNI_QSERDES_COM_CP_CTRL_MODE1	0x06 0
-				USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1	0x16 0
-				USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1	0x36 0
-				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1	0xCA 0
-				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1	0x1E 0
-				USB3_UNI_QSERDES_COM_SSC_EN_CENTER	0x01 0
-				USB3_UNI_QSERDES_COM_SSC_PER1	0x31 0
-				USB3_UNI_QSERDES_COM_SSC_PER2	0x01 0
-				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1	0xDE 0
-				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1	0x07 0
-				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0	0xDE 0
-				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0	0x07 0
-				USB3_UNI_QSERDES_COM_VCO_TUNE_MAP	0x02 0
-				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4	0xDC 0
-				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3	0xBD 0
-				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2	0xFF 0
-				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH	0x7F 0
-				USB3_UNI_QSERDES_RX_RX_MODE_00_LOW	0xFF 0
-				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4	0xA9 0
-				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3	0x7B 0
-				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2	0xE4 0
-				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH	0x24 0
-				USB3_UNI_QSERDES_RX_RX_MODE_01_LOW	0x64 0
-				USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS	0x99 0
-				USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1	0x08 0
-				USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2	0x08 0
-				USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1	0x00 0
-				USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2	0x04 0
-				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN	0x2F 0
-				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW	0xFF 0
-				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH	0x0F 0
-				USB3_UNI_QSERDES_RX_UCDR_FO_GAIN	0x0A 0
-				USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1	0x54 0
-				USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2	0x0F 0
-				USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2	0x0F 0
-				USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4	0x0A 0
-				USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1	0x47 0
-				USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2	0x80 0
-				USB3_UNI_QSERDES_RX_SIGDET_CNTRL	0x04 0
-				USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL	0x0E 0
-				USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET	0x38 0
-				USB3_UNI_QSERDES_RX_UCDR_SO_GAIN	0x05 0
-				USB3_UNI_QSERDES_RX_GM_CAL	0x00 0
-				USB3_UNI_QSERDES_RX_SIGDET_ENABLES	0x00 0
-				USB3_UNI_QSERDES_TX_LANE_MODE_1	0xA5 0
-				USB3_UNI_QSERDES_TX_LANE_MODE_2	0x82 0
-				USB3_UNI_QSERDES_TX_LANE_MODE_3	0x3F 0
-				USB3_UNI_QSERDES_TX_LANE_MODE_4	0x3F 0
-				USB3_UNI_QSERDES_TX_PI_QEC_CTRL	0x21 0
-				USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX	0x10 0
-				USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX	0x0E 0
-				USB3_UNI_PCS_LOCK_DETECT_CONFIG1	0xC4 0
-				USB3_UNI_PCS_LOCK_DETECT_CONFIG2	0x89 0
-				USB3_UNI_PCS_LOCK_DETECT_CONFIG3	0x20 0
-				USB3_UNI_PCS_LOCK_DETECT_CONFIG6	0x13 0
-				USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L	0xE7 0
-				USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H	0x03 0
-				USB3_UNI_PCS_RX_SIGDET_LVL	0xAA 0
-				USB3_UNI_PCS_PCS_TX_RX_CONFIG	0x0C 0
-				USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2	0x07 0
-				USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL	0xF8 0
-				USB3_UNI_PCS_USB3_POWER_STATE_CONFIG1		0x6F 0
-				USB3_UNI_PCS_CDR_RESET_TIME	0x0A 0
-				USB3_UNI_PCS_ALIGN_DETECT_CONFIG1	0x88 0
-				USB3_UNI_PCS_ALIGN_DETECT_CONFIG2	0x13 0
-				USB3_UNI_PCS_EQ_CONFIG1	0x4B 0
-				USB3_UNI_PCS_EQ_CONFIG5	0x10 0
-				USB3_UNI_PCS_REFGEN_REQ_CONFIG1	0x21 0
-				0xffffffff 0xffffffff 0x00>;
+				/* <reg_offset, value> */
+				<USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL	0x1A
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL	0x11
+				USB3_UNI_QSERDES_COM_HSCLK_SEL	0x01
+				USB3_UNI_QSERDES_COM_DEC_START_MODE0	0x82
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0	0xAB
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0	0xEA
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0	0x02
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0	0xCA
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0	0x1E
+				USB3_UNI_QSERDES_COM_CP_CTRL_MODE0	0x06
+				USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0	0x16
+				USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0	0x36
+				USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0	0x24
+				USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0	0x34
+				USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0	0x14
+				USB3_UNI_QSERDES_COM_LOCK_CMP_EN	0x04
+				USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE	0x0A
+				USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1	0x02
+				USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1	0x24
+				USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1	0x08
+				USB3_UNI_QSERDES_COM_DEC_START_MODE1	0x82
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1	0xAB
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1	0xEA
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1	0x02
+				USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1	0x82
+				USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1	0x34
+				USB3_UNI_QSERDES_COM_CP_CTRL_MODE1	0x06
+				USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1	0x16
+				USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1	0x36
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1	0xCA
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1	0x1E
+				USB3_UNI_QSERDES_COM_SSC_EN_CENTER	0x01
+				USB3_UNI_QSERDES_COM_SSC_PER1	0x31
+				USB3_UNI_QSERDES_COM_SSC_PER2	0x01
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1	0xDE
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1	0x07
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0	0xDE
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0	0x07
+				USB3_UNI_QSERDES_COM_VCO_TUNE_MAP	0x02
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4	0xDC
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3	0xBD
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2	0xFF
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH	0x7F
+				USB3_UNI_QSERDES_RX_RX_MODE_00_LOW	0xFF
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4	0xA9
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3	0x7B
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2	0xE4
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH	0x24
+				USB3_UNI_QSERDES_RX_RX_MODE_01_LOW	0x64
+				USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS	0x99
+				USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1	0x08
+				USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2	0x08
+				USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1	0x00
+				USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2	0x04
+				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN	0x2F
+				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW	0xFF
+				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH	0x0F
+				USB3_UNI_QSERDES_RX_UCDR_FO_GAIN	0x0A
+				USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1	0x54
+				USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2	0x0F
+				USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2	0x0F
+				USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4	0x0A
+				USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1	0x47
+				USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2	0x80
+				USB3_UNI_QSERDES_RX_SIGDET_CNTRL	0x04
+				USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL	0x0E
+				USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET	0x38
+				USB3_UNI_QSERDES_RX_UCDR_SO_GAIN	0x05
+				USB3_UNI_QSERDES_RX_GM_CAL	0x00
+				USB3_UNI_QSERDES_RX_SIGDET_ENABLES	0x00
+				USB3_UNI_QSERDES_TX_LANE_MODE_1	0xA5
+				USB3_UNI_QSERDES_TX_LANE_MODE_2	0x82
+				USB3_UNI_QSERDES_TX_LANE_MODE_3	0x3F
+				USB3_UNI_QSERDES_TX_LANE_MODE_4	0x3F
+				USB3_UNI_QSERDES_TX_PI_QEC_CTRL	0x21
+				USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX	0x10
+				USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX	0x0E
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG1	0xC4
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG2	0x89
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG3	0x20
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG6	0x13
+				USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L	0xE7
+				USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H	0x03
+				USB3_UNI_PCS_RX_SIGDET_LVL	0xAA
+				USB3_UNI_PCS_PCS_TX_RX_CONFIG	0x0C
+				USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2	0x07
+				USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL	0xF8
+				USB3_UNI_PCS_USB3_POWER_STATE_CONFIG1		0x6F
+				USB3_UNI_PCS_CDR_RESET_TIME	0x0A
+				USB3_UNI_PCS_ALIGN_DETECT_CONFIG1	0x88
+				USB3_UNI_PCS_ALIGN_DETECT_CONFIG2	0x13
+				USB3_UNI_PCS_EQ_CONFIG1	0x4B
+				USB3_UNI_PCS_EQ_CONFIG5	0x10
+				USB3_UNI_PCS_REFGEN_REQ_CONFIG1	0x21>;
 
 		qcom,qmp-phy-reg-offset =
 				<USB3_UNI_PCS_PCS_STATUS1
diff --git a/qcom/kalama-usb.dtsi b/qcom/kalama-usb.dtsi
index c313dfdf..389fa141 100644
--- a/qcom/kalama-usb.dtsi
+++ b/qcom/kalama-usb.dtsi
@@ -176,173 +176,172 @@
 			 USB3_DP_PCS_AON_CLAMP_ENABLE>;
 
 		qcom,qmp-phy-init-seq =
-			/* <reg_offset, value, delay> */
-		       <USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xC0 0
-			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x01 0
-			USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x02 0
-			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0
-			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0
-			USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x04 0
-			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x16 0
-			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x41 0
-			USB3_DP_QSERDES_COM_DEC_START_MODE1 0x41 0
-			USB3_DP_QSERDES_COM_DEC_START_MSB_MODE1 0x00 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0x55 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0x75 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x01 0
-			USB3_DP_QSERDES_COM_HSCLK_SEL_1 0x01 0
-			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x25 0
-			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x5C 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x0F 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x5C 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x0F 0
-			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xC0 0
-			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x01 0
-			USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x02 0
-			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
-			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0
-			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x08 0
-			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x1A 0
-			USB3_DP_QSERDES_COM_DEC_START_MODE0 0x41 0
-			USB3_DP_QSERDES_COM_DEC_START_MSB_MODE0 0x00 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0x55 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0x75 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x01 0
-			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x25 0
-			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE0 0x02 0
-			USB3_DP_QSERDES_COM_BG_TIMER 0x0A 0
-			USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01 0
-			USB3_DP_QSERDES_COM_SSC_PER1 0x62 0
-			USB3_DP_QSERDES_COM_SSC_PER2 0x02 0
-			USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0C 0
-			USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A 0
-			USB3_DP_QSERDES_COM_LOCK_CMP_CFG 0x14 0
-			USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x04 0
-			USB3_DP_QSERDES_COM_CORE_CLK_EN 0x20 0
-			USB3_DP_QSERDES_COM_CMN_CONFIG_1 0x16 0
-			USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_1 0xB6 0
-			USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_2 0x4B 0
-			USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_3 0x37 0
-			USB3_DP_QSERDES_COM_ADDITIONAL_MISC 0x0C 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x00 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x00 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x1F 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x09 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_1 0xF5 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_3 0x3F 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_4 0x3F 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_5 0x5F 0
-			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0
-			USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x21 0
-			USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x0A 0
-			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x06 0
-			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F 0
-			USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
-			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
-			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
-			USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x0A 0
-			USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0 0
-			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54 0
-			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0F 0
-			USB3_DP_QSERDES_RXA_GM_CAL 0x13 0
-			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
-			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
-			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
-			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0x07 0
-			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00 0
-			USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0
-			USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04 0
-			USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0x3F 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0xBF 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xFF 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0xDF 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0xED 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0xDC 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x5C 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x9C 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x1D 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0x09 0
-			USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04 0
-			USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38 0
-			USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C 0
-			USB3_DP_QSERDES_RXA_VTH_CODE 0x10 0
-			USB3_DP_QSERDES_RXA_SIGDET_CAL_CTRL1 0x14 0
-			USB3_DP_QSERDES_RXA_SIGDET_CAL_TRIM 0x08 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x00 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x00 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x1F 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x09 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_1 0xF5 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_3 0x3F 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_4 0x3F 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_5 0x5F 0
-			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0
-			USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x05 0
-			USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x0A 0
-			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x06 0
-			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F 0
-			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
-			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
-			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
-			USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x0A 0
-			USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0 0
-			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54 0
-			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0F 0
-			USB3_DP_QSERDES_RXB_GM_CAL 0x13 0
-			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
-			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
-			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
-			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0x07 0
-			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00 0
-			USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0
-			USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04 0
-			USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0xBF 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0xBF 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xBF 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0xDF 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xFD 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0xDC 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x5C 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x9C 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x1D 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0x09 0
-			USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04 0
-			USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38 0
-			USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C 0
-			USB3_DP_QSERDES_RXB_VTH_CODE 0x10 0
-			USB3_DP_QSERDES_RXB_SIGDET_CAL_CTRL1 0x14 0
-			USB3_DP_QSERDES_RXB_SIGDET_CAL_TRIM 0x08 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xC4 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x89 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13 0
-			USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21 0
-			USB3_DP_PCS_RX_SIGDET_LVL 0x99 0
-			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7 0
-			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0
-			USB3_DP_PCS_CDR_RESET_TIME 0x0A 0
-			USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88 0
-			USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13 0
-			USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C 0
-			USB3_DP_PCS_EQ_CONFIG1 0x4B 0
-			USB3_DP_PCS_EQ_CONFIG5 0x10 0
-			USB3_DP_PCS_USB3_POWER_STATE_CONFIG1 0x68 0
-			USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0
-			USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0
-			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40 0
-			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x00 0
-			0xffffffff 0xffffffff 0x00>;
+			/* <reg_offset, value> */
+		       <USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xC0
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x01
+			USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x02
+			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16
+			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36
+			USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x04
+			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x16
+			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x41
+			USB3_DP_QSERDES_COM_DEC_START_MODE1 0x41
+			USB3_DP_QSERDES_COM_DEC_START_MSB_MODE1 0x00
+			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0x55
+			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0x75
+			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x01
+			USB3_DP_QSERDES_COM_HSCLK_SEL_1 0x01
+			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x25
+			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x5C
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x0F
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x5C
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x0F
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xC0
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x01
+			USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x02
+			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16
+			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36
+			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x08
+			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x1A
+			USB3_DP_QSERDES_COM_DEC_START_MODE0 0x41
+			USB3_DP_QSERDES_COM_DEC_START_MSB_MODE0 0x00
+			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0x55
+			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0x75
+			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x01
+			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x25
+			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE0 0x02
+			USB3_DP_QSERDES_COM_BG_TIMER 0x0A
+			USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01
+			USB3_DP_QSERDES_COM_SSC_PER1 0x62
+			USB3_DP_QSERDES_COM_SSC_PER2 0x02
+			USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0C
+			USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A
+			USB3_DP_QSERDES_COM_LOCK_CMP_CFG 0x14
+			USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x04
+			USB3_DP_QSERDES_COM_CORE_CLK_EN 0x20
+			USB3_DP_QSERDES_COM_CMN_CONFIG_1 0x16
+			USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_1 0xB6
+			USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_2 0x4B
+			USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_3 0x37
+			USB3_DP_QSERDES_COM_ADDITIONAL_MISC 0x0C
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x00
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x00
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x1F
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x09
+			USB3_DP_QSERDES_TXA_LANE_MODE_1 0xF5
+			USB3_DP_QSERDES_TXA_LANE_MODE_3 0x3F
+			USB3_DP_QSERDES_TXA_LANE_MODE_4 0x3F
+			USB3_DP_QSERDES_TXA_LANE_MODE_5 0x5F
+			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12
+			USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x21
+			USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x0A
+			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x06
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F
+			USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F
+			USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99
+			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08
+			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08
+			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00
+			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x0A
+			USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0
+			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54
+			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0F
+			USB3_DP_QSERDES_RXA_GM_CAL 0x13
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A
+			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0x07
+			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00
+			USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
+			USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04
+			USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E
+			USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0x3F
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0xBF
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xFF
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0xDF
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0xED
+			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0xDC
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x5C
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x9C
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x1D
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0x09
+			USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04
+			USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38
+			USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C
+			USB3_DP_QSERDES_RXA_VTH_CODE 0x10
+			USB3_DP_QSERDES_RXA_SIGDET_CAL_CTRL1 0x14
+			USB3_DP_QSERDES_RXA_SIGDET_CAL_TRIM 0x08
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x00
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x00
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x1F
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x09
+			USB3_DP_QSERDES_TXB_LANE_MODE_1 0xF5
+			USB3_DP_QSERDES_TXB_LANE_MODE_3 0x3F
+			USB3_DP_QSERDES_TXB_LANE_MODE_4 0x3F
+			USB3_DP_QSERDES_TXB_LANE_MODE_5 0x5F
+			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12
+			USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x05
+			USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x0A
+			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x06
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F
+			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F
+			USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99
+			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08
+			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08
+			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00
+			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x0A
+			USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0
+			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54
+			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0F
+			USB3_DP_QSERDES_RXB_GM_CAL 0x13
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A
+			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0x07
+			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00
+			USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
+			USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04
+			USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E
+			USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0xBF
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0xBF
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xBF
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0xDF
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xFD
+			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0xDC
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x5C
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x9C
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x1D
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0x09
+			USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04
+			USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38
+			USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C
+			USB3_DP_QSERDES_RXB_VTH_CODE 0x10
+			USB3_DP_QSERDES_RXB_SIGDET_CAL_CTRL1 0x14
+			USB3_DP_QSERDES_RXB_SIGDET_CAL_TRIM 0x08
+			USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xC4
+			USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x89
+			USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20
+			USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13
+			USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21
+			USB3_DP_PCS_RX_SIGDET_LVL 0x99
+			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7
+			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x03
+			USB3_DP_PCS_CDR_RESET_TIME 0x0A
+			USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88
+			USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13
+			USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C
+			USB3_DP_PCS_EQ_CONFIG1 0x4B
+			USB3_DP_PCS_EQ_CONFIG5 0x10
+			USB3_DP_PCS_USB3_POWER_STATE_CONFIG1 0x68
+			USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8
+			USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07
+			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40
+			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x00>;
 	};
 
 	usb_audio_qmi_dev {
diff --git a/qcom/khaje-usb.dtsi b/qcom/khaje-usb.dtsi
index b9fe6957..b5055461 100644
--- a/qcom/khaje-usb.dtsi
+++ b/qcom/khaje-usb.dtsi
@@ -164,152 +164,151 @@
 			 USB3_DP_PCS_CLAMP_ENABLE>;
 
 		qcom,qmp-phy-init-seq =
-			/* <reg_offset, value, delay> */
-			<USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01 0
-			USB3_DP_QSERDES_COM_SSC_PER1 0x31 0
-			USB3_DP_QSERDES_COM_SSC_PER2 0x01 0
-			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE 0
-			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0
-			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE 0
-			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0
-			USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A 0
-			USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20 0
-			USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06 0
-			USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06 0
-			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
-			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0
-			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0
-			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0
-			USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A 0
-			USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x04 0
-			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0
-			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0
-			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0
-			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0
-			USB3_DP_QSERDES_COM_DEC_START_MODE0 0x82 0
-			USB3_DP_QSERDES_COM_DEC_START_MODE1 0x82 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0
-			USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02 0
-			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0
-			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0
-			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0
-			USB3_DP_QSERDES_COM_HSCLK_SEL 0x01 0
-			USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x60 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x60 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x11 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x02 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_1 0xD5 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_2 0x00 0
-			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0
-			USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x40 0
-			USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x09 0
-			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x05 0
-			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F 0
-			USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
-			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
-			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
-			USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x04 0
-			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54 0
-			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0C 0
-			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
-			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
-			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
-			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xC0 0
-			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00 0
-			USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0
-			USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04 0
-			USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xFF 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x7F 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0x7F 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x7F 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0x97 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0xDC 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0xDC 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x5C 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x7B 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xB4 0
-			USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04 0
-			USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38 0
-			USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0 0
-			USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C 0
-			USB3_DP_QSERDES_RXA_GM_CAL 0x1F 0
-			USB3_DP_QSERDES_RXA_VTH_CODE 0x10 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x60 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x60 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x11 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x02 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_1 0xD5 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_2 0x00 0
-			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0
-			USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x54 0
-			USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x09 0
-			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x05 0
-			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F 0
-			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
-			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
-			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
-			USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x04 0
-			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54 0
-			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0C 0
-			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
-			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
-			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
-			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xC0 0
-			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00 0
-			USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0
-			USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04 0
-			USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0x7F 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0xFF 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0x3F 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x7F 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xA6 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0xDC 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0xDC 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x5C 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x7B 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xB4 0
-			USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04 0
-			USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38 0
-			USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0 0
-			USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C 0
-			USB3_DP_QSERDES_RXB_GM_CAL 0x1F 0
-			USB3_DP_QSERDES_RXB_VTH_CODE 0x10 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xD0 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x07 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13 0
-			USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21 0
-			USB3_DP_PCS_RX_SIGDET_LVL 0xA9 0
-			USB3_DP_PCS_CDR_RESET_TIME 0x0A 0
-			USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88 0
-			USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13 0
-			USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C 0
-			USB3_DP_PCS_EQ_CONFIG1 0x4B 0
-			USB3_DP_PCS_EQ_CONFIG5 0x10 0
-			USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0
-			USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0
-			0xffffffff 0xffffffff 0x00>;
+			/* <reg_offset, value> */
+			<USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01
+			USB3_DP_QSERDES_COM_SSC_PER1 0x31
+			USB3_DP_QSERDES_COM_SSC_PER2 0x01
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07
+			USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A
+			USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20
+			USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06
+			USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06
+			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16
+			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16
+			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36
+			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36
+			USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A
+			USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x04
+			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x14
+			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x34
+			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x34
+			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x82
+			USB3_DP_QSERDES_COM_DEC_START_MODE0 0x82
+			USB3_DP_QSERDES_COM_DEC_START_MODE1 0x82
+			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB
+			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA
+			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02
+			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB
+			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA
+			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02
+			USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02
+			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x24
+			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x24
+			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02
+			USB3_DP_QSERDES_COM_HSCLK_SEL 0x01
+			USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x08
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x60
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x60
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x11
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x02
+			USB3_DP_QSERDES_TXA_LANE_MODE_1 0xD5
+			USB3_DP_QSERDES_TXA_LANE_MODE_2 0x00
+			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12
+			USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x40
+			USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x09
+			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x05
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F
+			USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F
+			USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99
+			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08
+			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08
+			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00
+			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x04
+			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54
+			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0C
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A
+			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xC0
+			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00
+			USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77
+			USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04
+			USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E
+			USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xFF
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x7F
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0x7F
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x7F
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0x97
+			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0xDC
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0xDC
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x5C
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x7B
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xB4
+			USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04
+			USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38
+			USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0
+			USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C
+			USB3_DP_QSERDES_RXA_GM_CAL 0x1F
+			USB3_DP_QSERDES_RXA_VTH_CODE 0x10
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x60
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x60
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x11
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x02
+			USB3_DP_QSERDES_TXB_LANE_MODE_1 0xD5
+			USB3_DP_QSERDES_TXB_LANE_MODE_2 0x00
+			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12
+			USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x54
+			USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x09
+			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x05
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F
+			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F
+			USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99
+			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08
+			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08
+			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00
+			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x04
+			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54
+			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0C
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A
+			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xC0
+			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00
+			USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77
+			USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04
+			USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E
+			USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0x7F
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0xFF
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0x3F
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x7F
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xA6
+			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0xDC
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0xDC
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x5C
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x7B
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xB4
+			USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04
+			USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38
+			USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0
+			USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C
+			USB3_DP_QSERDES_RXB_GM_CAL 0x1F
+			USB3_DP_QSERDES_RXB_VTH_CODE 0x10
+			USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xD0
+			USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x07
+			USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20
+			USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13
+			USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21
+			USB3_DP_PCS_RX_SIGDET_LVL 0xA9
+			USB3_DP_PCS_CDR_RESET_TIME 0x0A
+			USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88
+			USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13
+			USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C
+			USB3_DP_PCS_EQ_CONFIG1 0x4B
+			USB3_DP_PCS_EQ_CONFIG5 0x10
+			USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8
+			USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07>;
 	};
 
 	usb_nop_phy: usb_nop_phy {
diff --git a/qcom/sm8150-usb.dtsi b/qcom/sm8150-usb.dtsi
index d1e371eb..65ec1043 100644
--- a/qcom/sm8150-usb.dtsi
+++ b/qcom/sm8150-usb.dtsi
@@ -190,106 +190,105 @@
 		qcom,vdd-max-load-uA = <47000>;
 		core-supply = <&L8C>;
 		qcom,qmp-phy-init-seq =
-			/* <reg_offset, value, delay> */
-			<USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x1a 0
-			USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0
-			USB3_UNI_QSERDES_COM_HSCLK_SEL 0x01 0
-			USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x82 0
-			USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0xab 0
-			USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0xea 0
-			USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0
-			USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xca 0
-			USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1e 0
-			USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x02 0
-			USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
-			USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0
-			USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0
-			USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0
-			USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0
-			USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x04 0
-			USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0a 0
-			USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0
-			USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0
-			USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0
-			USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x82 0
-			USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0xab 0
-			USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0xea 0
-			USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0
-			USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0
-			USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0
-			USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x06 0
-			USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0
-			USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0
-			USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xca 0
-			USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1e 0
-			USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01 0
-			USB3_UNI_QSERDES_COM_SSC_PER1 0x31 0
-			USB3_UNI_QSERDES_COM_SSC_PER2 0x01 0
-			USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xde 0
-			USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0
-			USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xde 0
-			USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0
-			USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02 0
-			USB3_UNI_QSERDES_COM_CMN_IPTRIM 0x20 0
-			USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xa4 0
-			USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0x7f 0
-			USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0x37 0
-			USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x2f 0
-			USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xaf 0
-			USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xb6 0
-			USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x0b 0
-			USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x5c 0
-			USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0xdc 0
-			USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0xdc 0
-			USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x99 0
-			USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x04 0
-			USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08 0
-			USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x05 0
-			USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x05 0
-			USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2f 0
-			USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xff 0
-			USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0f 0
-			USB3_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x7f 0
-			USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0a 0
-			USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 0
-			USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x00 0
-			USB3_UNI_QSERDES_RX_GM_CAL 0x1f 0
-			USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0f 0
-			USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4a 0
-			USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0a 0
-			USB3_UNI_QSERDES_RX_DFE_EN_TIMER 0x04 0
-			USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0
-			USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0
-			USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04 0
-			USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0e 0
-			USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x00 0
-			USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW 0xc0 0
-			USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x20 0
-			USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x06 0
-			USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x12 0
-			USB3_UNI_QSERDES_TX_LANE_MODE_1 0x95 0
-			USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x40 0
-			USB3_UNI_QSERDES_TX_RES_CODE_LANE_TX 0xe4 0
-			USB3_UNI_QSERDES_TX_RES_CODE_LANE_RX 0xd0 0
-			USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x10 0
-			USB3_UNI_QSERDES_RX_DCC_CTRL1 0x0c 0
-			USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xd0 0
-			USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07 0
-			USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20 0
-			USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13 0
-			USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7 0
-			USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0
-			USB3_UNI_PCS_RX_SIGDET_LVL 0xaa 0
-			USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0
-			USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xf8 0
-			USB3_UNI_PCS_CDR_RESET_TIME 0x0a 0
-			USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88 0
-			USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13 0
-			USB3_UNI_PCS_EQ_CONFIG1 0x4b 0
-			USB3_UNI_PCS_EQ_CONFIG5 0x10 0
-			USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21 0
-			USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0c 0
-			0xffffffff 0xffffffff 0x00>;
+			/* <reg_offset, valuey> */
+			<USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x1a
+			USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11
+			USB3_UNI_QSERDES_COM_HSCLK_SEL 0x01
+			USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x82
+			USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0xab
+			USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0xea
+			USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02
+			USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xca
+			USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1e
+			USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x02
+			USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x16
+			USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x36
+			USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x24
+			USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x34
+			USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x14
+			USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x04
+			USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0a
+			USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x02
+			USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x24
+			USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x08
+			USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x82
+			USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0xab
+			USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0xea
+			USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02
+			USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x82
+			USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x34
+			USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x06
+			USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x16
+			USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36
+			USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xca
+			USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1e
+			USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01
+			USB3_UNI_QSERDES_COM_SSC_PER1 0x31
+			USB3_UNI_QSERDES_COM_SSC_PER2 0x01
+			USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xde
+			USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07
+			USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xde
+			USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07
+			USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02
+			USB3_UNI_QSERDES_COM_CMN_IPTRIM 0x20
+			USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xa4
+			USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0x7f
+			USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0x37
+			USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x2f
+			USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xaf
+			USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xb6
+			USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x0b
+			USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x5c
+			USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0xdc
+			USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0xdc
+			USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x99
+			USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x04
+			USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08
+			USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x05
+			USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x05
+			USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2f
+			USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xff
+			USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0f
+			USB3_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x7f
+			USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0a
+			USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54
+			USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x00
+			USB3_UNI_QSERDES_RX_GM_CAL 0x1f
+			USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0f
+			USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4a
+			USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0a
+			USB3_UNI_QSERDES_RX_DFE_EN_TIMER 0x04
+			USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
+			USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x80
+			USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04
+			USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0e
+			USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x00
+			USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW 0xc0
+			USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x20
+			USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x06
+			USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x12
+			USB3_UNI_QSERDES_TX_LANE_MODE_1 0x95
+			USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x40
+			USB3_UNI_QSERDES_TX_RES_CODE_LANE_TX 0xe4
+			USB3_UNI_QSERDES_TX_RES_CODE_LANE_RX 0xd0
+			USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x10
+			USB3_UNI_QSERDES_RX_DCC_CTRL1 0x0c
+			USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xd0
+			USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07
+			USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20
+			USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13
+			USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7
+			USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03
+			USB3_UNI_PCS_RX_SIGDET_LVL 0xaa
+			USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07
+			USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xf8
+			USB3_UNI_PCS_CDR_RESET_TIME 0x0a
+			USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88
+			USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13
+			USB3_UNI_PCS_EQ_CONFIG1 0x4b
+			USB3_UNI_PCS_EQ_CONFIG5 0x10
+			USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21
+			USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0c>;
 
 		qcom,qmp-phy-reg-offset =
 				<USB3_UNI_PCS_PCS_STATUS1
diff --git a/qcom/waipio-usb.dtsi b/qcom/waipio-usb.dtsi
index e4e1b449..158092df 100644
--- a/qcom/waipio-usb.dtsi
+++ b/qcom/waipio-usb.dtsi
@@ -169,160 +169,159 @@
 			 USB3_DP_PCS_CLAMP_ENABLE>;
 
 		qcom,qmp-phy-init-seq =
-			/* <reg_offset, value, delay> */
-			<USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01 0
-			USB3_DP_QSERDES_COM_SSC_PER1 0x31 0
-			USB3_DP_QSERDES_COM_SSC_PER2 0x01 0
-			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE 0
-			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0
-			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE 0
-			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0
-			USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A 0
-			USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20 0
-			USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06 0
-			USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06 0
-			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
-			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0
-			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0
-			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0
-			USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A 0
-			USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x04 0
-			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0
-			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0
-			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0
-			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0
-			USB3_DP_QSERDES_COM_DEC_START_MODE0 0x82 0
-			USB3_DP_QSERDES_COM_DEC_START_MODE1 0x82 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0
-			USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02 0
-			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0
-			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0
-			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0
-			USB3_DP_QSERDES_COM_HSCLK_SEL 0x01 0
-			USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x00 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x00 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x16 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x0E 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_1 0x35 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_3 0x3F 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_4 0x7F 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_5 0x3F 0
-			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0
-			USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x21 0
-			USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x0A 0
-			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x03 0
-			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F 0
-			USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
-			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
-			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
-			USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x04 0
-			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54 0
-			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0F 0
-			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
-			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
-			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
-			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xC0 0
-			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00 0
-			USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0
-			USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04 0
-			USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xBB 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x7B 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xBB 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x3D 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0xDB 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x64 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x24 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0xD2 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x13 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xA9 0
-			USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04 0
-			USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38 0
-			USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0 0
-			USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C 0
-			USB3_DP_QSERDES_RXA_GM_CAL 0x00 0
-			USB3_DP_QSERDES_RXA_VTH_CODE 0x10 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x00 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x00 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x16 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x0E 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_1 0x35 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_3 0x3F 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_4 0x7F 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_5 0x3F 0
-			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0
-			USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x21 0
-			USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x0A 0
-			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x03 0
-			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F 0
-			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
-			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
-			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
-			USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x04 0
-			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54 0
-			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0F 0
-			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
-			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
-			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
-			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xC0 0
-			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00 0
-			USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0
-			USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04 0
-			USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0xBB 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0x7B 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xBB 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x3C 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xDB 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x64 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x24 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0xD2 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x13 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xA9 0
-			USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04 0
-			USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38 0
-			USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0 0
-			USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C 0
-			USB3_DP_QSERDES_RXB_GM_CAL 0x00 0
-			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40 0
-			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x00 0
-			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7 0
-			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0
-			USB3_DP_QSERDES_RXB_VTH_CODE 0x10 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xD0 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x07 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13 0
-			USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21 0
-			USB3_DP_PCS_RX_SIGDET_LVL 0xAA 0
-			USB3_DP_PCS_CDR_RESET_TIME 0x0A 0
-			USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88 0
-			USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13 0
-			USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C 0
-			USB3_DP_PCS_EQ_CONFIG1 0x4B 0
-			USB3_DP_PCS_EQ_CONFIG5 0x10 0
-			USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0
-			USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0
-			0xffffffff 0xffffffff 0x00>;
+			/* <reg_offset, value> */
+			<USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01
+			USB3_DP_QSERDES_COM_SSC_PER1 0x31
+			USB3_DP_QSERDES_COM_SSC_PER2 0x01
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07
+			USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A
+			USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20
+			USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06
+			USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06
+			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16
+			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16
+			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36
+			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36
+			USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A
+			USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x04
+			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x14
+			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x34
+			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x34
+			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x82
+			USB3_DP_QSERDES_COM_DEC_START_MODE0 0x82
+			USB3_DP_QSERDES_COM_DEC_START_MODE1 0x82
+			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB
+			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA
+			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02
+			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB
+			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA
+			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02
+			USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02
+			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x24
+			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x24
+			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02
+			USB3_DP_QSERDES_COM_HSCLK_SEL 0x01
+			USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x08
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x00
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x00
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x16
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x0E
+			USB3_DP_QSERDES_TXA_LANE_MODE_1 0x35
+			USB3_DP_QSERDES_TXA_LANE_MODE_3 0x3F
+			USB3_DP_QSERDES_TXA_LANE_MODE_4 0x7F
+			USB3_DP_QSERDES_TXA_LANE_MODE_5 0x3F
+			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12
+			USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x21
+			USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x0A
+			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x03
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F
+			USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F
+			USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99
+			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08
+			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08
+			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00
+			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x04
+			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54
+			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0F
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A
+			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xC0
+			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00
+			USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
+			USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04
+			USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E
+			USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xBB
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x7B
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xBB
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x3D
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0xDB
+			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x64
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x24
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0xD2
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x13
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xA9
+			USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04
+			USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38
+			USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0
+			USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C
+			USB3_DP_QSERDES_RXA_GM_CAL 0x00
+			USB3_DP_QSERDES_RXA_VTH_CODE 0x10
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x00
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x00
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x16
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x0E
+			USB3_DP_QSERDES_TXB_LANE_MODE_1 0x35
+			USB3_DP_QSERDES_TXB_LANE_MODE_3 0x3F
+			USB3_DP_QSERDES_TXB_LANE_MODE_4 0x7F
+			USB3_DP_QSERDES_TXB_LANE_MODE_5 0x3F
+			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12
+			USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x21
+			USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x0A
+			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x03
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F
+			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F
+			USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99
+			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08
+			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08
+			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00
+			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x04
+			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54
+			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0F
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A
+			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xC0
+			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00
+			USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
+			USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04
+			USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E
+			USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0xBB
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0x7B
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xBB
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x3C
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xDB
+			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x64
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x24
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0xD2
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x13
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xA9
+			USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04
+			USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38
+			USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0
+			USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C
+			USB3_DP_QSERDES_RXB_GM_CAL 0x00
+			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40
+			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x00
+			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7
+			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x03
+			USB3_DP_QSERDES_RXB_VTH_CODE 0x10
+			USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xD0
+			USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x07
+			USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20
+			USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13
+			USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21
+			USB3_DP_PCS_RX_SIGDET_LVL 0xAA
+			USB3_DP_PCS_CDR_RESET_TIME 0x0A
+			USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88
+			USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13
+			USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C
+			USB3_DP_PCS_EQ_CONFIG1 0x4B
+			USB3_DP_PCS_EQ_CONFIG5 0x10
+			USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8
+			USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07>;
 	};
 
 	usb_audio_qmi_dev {