From f79a0a8067ed5d6fc883b0f6c41773548e700884 Mon Sep 17 00:00:00 2001
From: Melody Olvera <molvera@quicinc.com>
Date: Thu, 20 Jan 2022 15:56:02 -0800
Subject: [PATCH] ARM: dts: msm: Change cpu enable method to psci

Change cpu enable method to psci to support full boot
on multicore.

Change-Id: Ia830e6f5ef76c8c99505fe92de121ff39da097a8
---
 qcom/cinder.dtsi | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/qcom/cinder.dtsi b/qcom/cinder.dtsi
index 4daf977e..fa5f1994 100644
--- a/qcom/cinder.dtsi
+++ b/qcom/cinder.dtsi
@@ -28,8 +28,7 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a55";
 			reg = <0x0 0x0>;
-			enable-method = "spin-table";
-			cpu-release-addr = <0x0 0x80C40000>;
+			enable-method = "psci";
 			next-level-cache = <&L2_0>;
 			L2_0: l2-cache {
 			      compatible = "arm,arch-cache";
@@ -47,8 +46,7 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a55";
 			reg = <0x0 0x100>;
-			enable-method = "spin-table";
-			cpu-release-addr = <0x0 0x80C40000>;
+			enable-method = "psci";
 			next-level-cache = <&L2_1>;
 			L2_1: l2-cache {
 			      compatible = "arm,arch-cache";
@@ -62,8 +60,7 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a55";
 			reg = <0x0 0x200>;
-			enable-method = "spin-table";
-			cpu-release-addr = <0x0 0x80C40000>;
+			enable-method = "psci";
 			next-level-cache = <&L2_2>;
 			L2_2: l2-cache {
 			      compatible = "arm,arch-cache";
@@ -76,8 +73,7 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a55";
 			reg = <0x0 0x300>;
-			enable-method = "spin-table";
-			cpu-release-addr = <0x0 0x80C40000>;
+			enable-method = "psci";
 			next-level-cache = <&L2_3>;
 			L2_3: l2-cache {
 			      compatible = "arm,arch-cache";
@@ -119,6 +115,11 @@
 	ranges = <0 0 0 0xffffffff>;
 	compatible = "simple-bus";
 
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
 	intc: interrupt-controller@17200000 {
 		compatible = "arm,gic-v3";
 		#interrupt-cells = <3>;