From b3a2cac038f29ee823cf93aec60df31ccce93263 Mon Sep 17 00:00:00 2001
From: Yatish Kumar Singh <yatishku@qti.qualcomm.com>
Date: Tue, 30 Nov 2021 17:30:51 +0530
Subject: [PATCH] ARM: dts: msm: Add QUPv3 UART console node for cinder

Enable console support on cinder

Change-Id: I5428597e0e8db87b4efa5bc9312e9b29de166dcf
---
 qcom/cinder-pinctrl.dtsi | 26 ++++++++++++++++++++++++++
 qcom/cinder-qupv3.dtsi   | 27 +++++++++++++++++++++++++++
 qcom/cinder-rumi.dtsi    |  4 ++++
 qcom/cinder.dtsi         |  8 +++++++-
 4 files changed, 64 insertions(+), 1 deletion(-)
 create mode 100644 qcom/cinder-qupv3.dtsi

diff --git a/qcom/cinder-pinctrl.dtsi b/qcom/cinder-pinctrl.dtsi
index 4d1f6044..1a970061 100644
--- a/qcom/cinder-pinctrl.dtsi
+++ b/qcom/cinder-pinctrl.dtsi
@@ -1,3 +1,29 @@
 &tlmm {
+	qupv3_se7_2uart_pins: qupv3_se7_2uart_pins {
+		qupv3_se7_2uart_active: qupv3_se7_2uart_active {
+			mux {
+				pins = "gpio134", "gpio135";
+				function = "qup07";
+			};
 
+			config {
+				pins = "gpio134", "gpio135";
+				drive-strength= <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se7_2uart_sleep: qupv3_se7_2uart_sleep {
+			mux {
+				pins = "gpio134", "gpio135";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio134", "gpio135";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+	};
 };
diff --git a/qcom/cinder-qupv3.dtsi b/qcom/cinder-qupv3.dtsi
new file mode 100644
index 00000000..c33ed734
--- /dev/null
+++ b/qcom/cinder-qupv3.dtsi
@@ -0,0 +1,27 @@
+&soc {
+	/* QUPv3_0 wrapper instance */
+	qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
+		compatible = "qcom,geni-se-qup";
+		reg = <0x9c0000 0x2000>;
+		clock-names = "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		status = "ok";
+
+		/*PORed Debug UART Instance */
+		qupv3_se7_2uart: qcom,qup_uart@99c000 {
+			compatible = "qcom,geni-debug-uart";
+			reg = <0x99c000 0x4000>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se7_2uart_active>;
+			pinctrl-1 = <&qupv3_se7_2uart_sleep>;
+		};
+	};
+};
diff --git a/qcom/cinder-rumi.dtsi b/qcom/cinder-rumi.dtsi
index 2865ab86..71e94a0a 100644
--- a/qcom/cinder-rumi.dtsi
+++ b/qcom/cinder-rumi.dtsi
@@ -13,3 +13,7 @@
 &soc {
 
 };
+
+&qupv3_se7_2uart {
+	qcom,rumi_platform;
+};
diff --git a/qcom/cinder.dtsi b/qcom/cinder.dtsi
index 27ac180e..a3182f1d 100644
--- a/qcom/cinder.dtsi
+++ b/qcom/cinder.dtsi
@@ -13,7 +13,9 @@
 
 	chosen: chosen { };
 
-	aliases { };
+	aliases {
+		serial0 = &qupv3_se7_2uart;
+	};
 
 	firmware: firmware { };
 
@@ -389,4 +391,8 @@
 };
 
 #include "cinder-pinctrl.dtsi"
+#include "cinder-qupv3.dtsi"
 
+&qupv3_se7_2uart {
+	status = "ok";
+};