From 5c8a2d04ac51c5f6ba445bb49af1356880e6a227 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Mon, 26 Sep 2022 14:22:47 +0530 Subject: [PATCH] ARM: dts: msm: Update GCC node for sdxpinn platform Add the support for emac clocks and update the GCC clock node for sdxpinn platform. Change-Id: I8d9f6504d92979516c416f0ae92d6acf8ec41f46 --- qcom/sdxpinn-rumi.dtsi | 7 ++-- qcom/sdxpinn.dtsi | 72 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+), 2 deletions(-) diff --git a/qcom/sdxpinn-rumi.dtsi b/qcom/sdxpinn-rumi.dtsi index 4d0e7198..17e29c75 100644 --- a/qcom/sdxpinn-rumi.dtsi +++ b/qcom/sdxpinn-rumi.dtsi @@ -221,8 +221,11 @@ }; &gcc { - clocks = <&bi_tcxo>, <&pcie20_phy_aux_clk>, <&pcie_1_pipe_clk>, <&pcie_2_pipe_clk>, - <&pcie_pipe_clk>, <&sleep_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + clocks = <&bi_tcxo>, <&emac0_sgmiiphy_mac_rclk>, <&emac0_sgmiiphy_mac_tclk>, + <&emac0_sgmiiphy_rclk>, <&emac0_sgmiiphy_tclk>, <&emac1_sgmiiphy_mac_rclk>, + <&emac1_sgmiiphy_mac_tclk>, <&emac1_sgmiiphy_rclk>, <&emac1_sgmiiphy_tclk>, + <&pcie20_phy_aux_clk>, <&pcie_1_pipe_clk>, <&pcie_2_pipe_clk>, <&pcie_pipe_clk>, + <&sleep_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; }; &gcc_emac0_gdsc { diff --git a/qcom/sdxpinn.dtsi b/qcom/sdxpinn.dtsi index 6cade107..e8709681 100644 --- a/qcom/sdxpinn.dtsi +++ b/qcom/sdxpinn.dtsi @@ -492,6 +492,62 @@ #clock-cells = <0>; }; + emac0_sgmiiphy_mac_rclk: emac0_sgmiiphy_mac_rclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac0_sgmiiphy_mac_rclk"; + #clock-cells = <0>; + }; + + emac0_sgmiiphy_mac_tclk: emac0_sgmiiphy_mac_tclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac0_sgmiiphy_mac_tclk"; + #clock-cells = <0>; + }; + + emac0_sgmiiphy_rclk: emac0_sgmiiphy_rclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac0_sgmiiphy_rclk"; + #clock-cells = <0>; + }; + + emac0_sgmiiphy_tclk: emac0_sgmiiphy_tclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac0_sgmiiphy_tclk"; + #clock-cells = <0>; + }; + + emac1_sgmiiphy_mac_rclk: emac1_sgmiiphy_mac_rclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac1_sgmiiphy_mac_rclk"; + #clock-cells = <0>; + }; + + emac1_sgmiiphy_mac_tclk: emac1_sgmiiphy_mac_tclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac1_sgmiiphy_mac_tclk"; + #clock-cells = <0>; + }; + + emac1_sgmiiphy_rclk: emac1_sgmiiphy_rclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac1_sgmiiphy_rclk"; + #clock-cells = <0>; + }; + + emac1_sgmiiphy_tclk: emac1_sgmiiphy_tclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac1_sgmiiphy_tclk"; + #clock-cells = <0>; + }; + pcie20_phy_aux_clk: pcie20_phy_aux_clk { compatible = "fixed-clock"; clock-frequency = <1000>; @@ -535,6 +591,14 @@ vdd_cx-supply = <&VDD_CX_LEVEL>; vdd_mx-supply = <&VDD_MXA_LEVEL>; clocks = <&rpmhcc RPMH_CXO_CLK>, + <&emac0_sgmiiphy_mac_rclk>, + <&emac0_sgmiiphy_mac_tclk>, + <&emac0_sgmiiphy_rclk>, + <&emac0_sgmiiphy_tclk>, + <&emac1_sgmiiphy_mac_rclk>, + <&emac1_sgmiiphy_mac_tclk>, + <&emac1_sgmiiphy_rclk>, + <&emac1_sgmiiphy_tclk>, <&pcie20_phy_aux_clk>, <&pcie_1_pipe_clk>, <&pcie_2_pipe_clk>, @@ -542,6 +606,14 @@ <&sleep_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; clock-names = "bi_tcxo", + "emac0_sgmiiphy_mac_rclk", + "emac0_sgmiiphy_mac_tclk", + "emac0_sgmiiphy_rclk", + "emac0_sgmiiphy_tclk", + "emac1_sgmiiphy_mac_rclk", + "emac1_sgmiiphy_mac_tclk", + "emac1_sgmiiphy_rclk", + "emac1_sgmiiphy_tclk", "pcie20_phy_aux_clk", "pcie_1_pipe_clk", "pcie_2_pipe_clk",