From f059f3d575016a9b8a3b68214b668238ba682208 Mon Sep 17 00:00:00 2001 From: Prerna Singh Date: Mon, 1 Aug 2022 15:58:28 +0530 Subject: [PATCH] ARM: dts: msm: Update freq-domain-cells property MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update freq-domain-cells property as per latest cpufreq driver for Monaco. Change-Id: Ie58536ab56410eed553058e59ba0c8cee1cdfd3b --- qcom/monaco.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index c329b643..eec4f9a8 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -41,7 +41,7 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_0>; - qcom,freq-domain = <&cpufreq_hw 0 4>; + qcom,freq-domain = <&cpufreq_hw 0>; qcom,lmh-dcvs = <&lmh_dcvs0>; #cooling-cells = <2>; L2_0: l2-cache { @@ -68,7 +68,7 @@ i-cache-size = <0x8000>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; - qcom,freq-domain = <&cpufreq_hw 0 4>; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_0>; qcom,lmh-dcvs = <&lmh_dcvs0>; @@ -90,7 +90,7 @@ i-cache-size = <0x8000>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; - qcom,freq-domain = <&cpufreq_hw 0 4>; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_0>; qcom,lmh-dcvs = <&lmh_dcvs0>; @@ -112,7 +112,7 @@ i-cache-size = <0x8000>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; - qcom,freq-domain = <&cpufreq_hw 0 4>; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_0>; qcom,lmh-dcvs = <&lmh_dcvs0>; @@ -898,7 +898,7 @@ clock-names = "xo", "alternate"; qcom,no-accumulative-counter; qcom,max-lut-entries = <12>; - #freq-domain-cells = <2>; + #freq-domain-cells = <1>; }; qcom,cpufreq-hw-debug@f521000 {