From 183d85dac68f8f59d1785863135e778c1eae1168 Mon Sep 17 00:00:00 2001
From: Anvisha <anvisriv@qti.qualcomm.com>
Date: Mon, 4 Jul 2022 12:32:41 +0530
Subject: [PATCH] ARM: dts: msm: Enable platform security drivers

This change adds dts entries for qrng(Random number generator),
QCEDEV(QTI Crypto Engine driver: module provided for accessing
CE(Crypto Engine) HW by user space apps) on cinder target.

Test: Nominal, Stress, Adversial and Repetitive Test passed.

Change-Id: Iabc6c9f905dc300137e62cdd4cd06505b57431ce
---
 qcom/cinder.dtsi | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/qcom/cinder.dtsi b/qcom/cinder.dtsi
index 18948f90..95b8ed96 100644
--- a/qcom/cinder.dtsi
+++ b/qcom/cinder.dtsi
@@ -475,6 +475,35 @@
 		compatible = "qcom,dload-mode";
 	};
 
+	qcom_cedev: qcedev@1de0000 {
+		compatible = "qcom,qcedev";
+		reg = <0x1de0000 0x20000>,
+			<0x1dc4000 0x28000>;
+		reg-names = "crypto-base","crypto-bam-base";
+		interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,bam-pipe-pair = <2>;
+		qcom,ce-hw-instance = <0>;
+		qcom,ce-device = <0>;
+		qcom,ce-hw-shared;
+		qcom,bam-ee = <0>;
+		qcom,smmu-s1-enable;
+		qcom,no-clock-support;
+		interconnect-names = "data_path";
+		interconnects = <&system_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
+		iommus = <&apps_smmu 0x0000 0x0>,
+			<&apps_smmu 0x0001 0x0>;
+		qcom,iommu-dma = "atomic";
+		dma-coherent;
+	};
+
+	qcom_rng: qrng@10c3000 {
+		compatible = "qcom,msm-rng";
+		reg = <0x10c3000 0x1000>;
+		qcom,no-qrng-config;
+		qcom,no-clock-support;
+	};
+
+
 	qcom_tzlog: tz-log@14680720 {
 		compatible = "qcom,tz-log";
 		reg = <0x14680720 0x3000>;