From 2c3282b26fe07b6b53bc34ed3b6e3398aa44dad8 Mon Sep 17 00:00:00 2001
From: Tushar Nimkar <tnimkar@qti.qualcomm.com>
Date: Mon, 16 May 2022 14:57:55 +0530
Subject: [PATCH 1/2] dt-bindings: Add pdc binding for sdxpinn

This change adds PDC binding support.

Change-Id: Icb40b4b972ce1c41000ad8286cc5073a9038da32
---
 bindings/interrupt-controller/qcom,pdc.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/bindings/interrupt-controller/qcom,pdc.txt b/bindings/interrupt-controller/qcom,pdc.txt
index bd353964..3b83aa7b 100644
--- a/bindings/interrupt-controller/qcom,pdc.txt
+++ b/bindings/interrupt-controller/qcom,pdc.txt
@@ -24,6 +24,7 @@ Properties:
 		    - "qcom,sdm8150-pdc": For SM8150
 		    - "qcom,sdm8250-pdc": For SM8250
 		    - "qcom,sdm8350-pdc": For SM8350
+		    - "qcom,sdxpinn-pdc": For SDXPINN
 
 - reg:
 	Usage: required

From b9f09c5ef2799c3197d46e2d8c6c8d2dac9f459e Mon Sep 17 00:00:00 2001
From: Tushar Nimkar <tnimkar@qti.qualcomm.com>
Date: Wed, 6 Jul 2022 13:01:37 +0530
Subject: [PATCH 2/2] ARM: dts: msm: Add bindings for RSC and PDC devices for
 sdxpinn

This change adds apps rsc and pdc devices. Along with this it adds
wakeup parent for TLMM.

Change-Id: Id4b28621bf0ddddab99ef045720b0ea013cef2d2
---
 qcom/sdxpinn.dtsi | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/qcom/sdxpinn.dtsi b/qcom/sdxpinn.dtsi
index 5aaa8d34..f537e55f 100644
--- a/qcom/sdxpinn.dtsi
+++ b/qcom/sdxpinn.dtsi
@@ -2,6 +2,7 @@
 #include <dt-bindings/clock/qcom,gcc-sdxpinn.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/soc/qcom,ipcc.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
 
 / {
 	model = "Qualcomm Technologies, Inc. SDXPINN";
@@ -145,6 +146,31 @@
 		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
+	apps_rsc: rsc@17a00000 {
+		label = "apps_rsc";
+		compatible = "qcom,rpmh-rsc";
+		reg = <0x17a00000 0x10000>,
+		      <0x17a10000 0x10000>,
+		      <0x17a20000 0x10000>;
+		reg-names = "drv-0", "drv-1", "drv-2";
+		qcom,drv-count = <3>;
+		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+
+		apps_rsc_drv2: drv@2 {
+			qcom,drv-id = <2>;
+			qcom,tcs-offset = <0xd00>;
+			channel@0 {
+				qcom,tcs-config = <ACTIVE_TCS    3>,
+						  <SLEEP_TCS     2>,
+						  <WAKE_TCS      2>,
+						  <CONTROL_TCS   0>,
+						  <FAST_PATH_TCS 1>;
+			};
+		};
+	};
+
 	arch_timer: timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
@@ -213,6 +239,15 @@
 		};
 	};
 
+	pdc: interrupt-controller@b220000 {
+		compatible = "qcom,sdxpinn-pdc", "qcom,pdc";
+		reg = <0xb220000 0x30000>, <0x174000f0 0x64>;
+		qcom,pdc-ranges = <0 147 52>, <52 558 91>;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&intc>;
+		interrupt-controller;
+	};
+
 	clocks {
 		xo_board: xo_board {
 			compatible = "fixed-clock";
@@ -363,6 +398,7 @@
 		#gpio-cells = <2>;
 		interrupt-controller;
 		#interrupt-cells = <2>;
+		wakeup-parent = <&pdc>;
 	};
 
 	ipcc_mproc: qcom,ipcc@408000 {