From e9c51fbcde25487d61bca24e750e9d6d20699f19 Mon Sep 17 00:00:00 2001
From: Yadu MG <ymg@qti.qualcomm.com>
Date: Wed, 9 Nov 2022 12:29:42 +0530
Subject: [PATCH] ARM: dts: msm: Add LLCC device nodes for Lemans

Add device nodes for Last level cache controller for
Lemans target.

Change-Id: I15641f24b18d1b85264a932955245fa1767b2549
---
 qcom/lemans.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/qcom/lemans.dtsi b/qcom/lemans.dtsi
index d69a1497..8b4206ec 100644
--- a/qcom/lemans.dtsi
+++ b/qcom/lemans.dtsi
@@ -4,6 +4,7 @@
 #include <dt-bindings/clock/qcom,gcc-lemans.h>
 #include <dt-bindings/clock/qcom,gpucc-lemans.h>
 #include <dt-bindings/clock/qcom,videocc-lemans.h>
+#include <dt-bindings/clock/qcom,aop-qmp.h>
 #include <dt-bindings/interconnect/qcom,lemans.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -668,6 +669,20 @@
 		#mbox-cells = <2>;
 	};
 
+	cache-controller@9200000 {
+		compatible = "qcom,lemans-llcc", "qcom,llcc-v31";
+		reg = <0x9200000 0x580000> , <0x9a00000 0x80000>;
+		reg-names = "llcc_base", "llcc_broadcast_base";
+		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
+		cap-based-alloc-and-pwr-collapse;
+
+		llcc-perfmon {
+			compatible = "qcom,llcc-perfmon";
+			clocks = <&aoss_qmp QDSS_CLK>;
+			clock-names = "qdss_clk";
+		};
+	};
+
 	clocks {
 		xo_board: xo_board {
 			compatible = "fixed-clock";