diff --git a/qcom/sa8195p-pcie.dtsi b/qcom/sa8195p-pcie.dtsi
new file mode 100644
index 00000000..43bbd716
--- /dev/null
+++ b/qcom/sa8195p-pcie.dtsi
@@ -0,0 +1,1347 @@
+#include <dt-bindings/clock/qcom,gcc-sc8180x.h>
+
+&soc {
+	pcie0: qcom,pcie@1c00000 {
+		compatible = "qcom,pci-msm";
+		cell-index = <0>;
+
+		reg = <0x1c00000 0x4000>,
+			<0x1c06000 0x1000>,
+			<0x60000000 0xf1d>,
+			<0x60000f20 0xa8>,
+			<0x60001000 0x1000>,
+			<0x60100000 0x100000>,
+			<0x60200000 0x100000>,
+			<0x60300000 0x3d00000>,
+			<0x01c03000 0x1000>;
+
+		reg-names = "parf", "phy", "dm_core", "elbi",
+				"iatu", "conf", "io", "bars",
+				"mhi";
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
+			<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;
+		interrupt-parent = <&pcie0>;
+		interrupts = <0 1 2 3 4>;
+		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
+				"int_d";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0xffffffff>;
+		interrupt-map = < 0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+
+		qcom,phy-sequence = <0x0840 0x03 0x0
+				0x0094 0x08 0x0
+				0x0154 0x34 0x0
+				0x016c 0x08 0x0
+				0x0058 0x0f 0x0
+				0x00a4 0x42 0x0
+				0x0110 0x24 0x0
+				0x011c 0x03 0x0
+				0x0118 0xb4 0x0
+				0x010c 0x02 0x0
+				0x01bc 0x11 0x0
+				0x00bc 0x82 0x0
+				0x00d4 0x03 0x0
+				0x00d0 0x55 0x0
+				0x00cc 0x55 0x0
+				0x00b0 0x1a 0x0
+				0x00ac 0x0a 0x0
+				0x00c4 0x68 0x0
+				0x00e0 0x02 0x0
+				0x00dc 0xaa 0x0
+				0x00d8 0xab 0x0
+				0x00b8 0x34 0x0
+				0x00b4 0x14 0x0
+				0x0158 0x01 0x0
+				0x0074 0x06 0x0
+				0x007c 0x16 0x0
+				0x0084 0x36 0x0
+				0x0078 0x06 0x0
+				0x0080 0x16 0x0
+				0x0088 0x36 0x0
+				0x01b0 0x1e 0x0
+				0x01ac 0xb9 0x0
+				0x01b8 0x18 0x0
+				0x01b4 0x94 0x0
+				0x0050 0x07 0x0
+				0x0010 0x00 0x0
+				0x001c 0x31 0x0
+				0x0020 0x01 0x0
+				0x0024 0xde 0x0
+				0x0028 0x07 0x0
+				0x0030 0x4c 0x0
+				0x0034 0x06 0x0
+				0x029c 0x12 0x0
+				0x0284 0x35 0x0
+				0x023c 0x11 0x0
+				0x051c 0x03 0x0
+				0x0518 0x1c 0x0
+				0x0524 0x1e 0x0
+				0x04e8 0x00 0x0
+				0x04ec 0x0e 0x0
+				0x04f0 0x4a 0x0
+				0x04f4 0x0f 0x0
+				0x05b4 0x04 0x0
+				0x0434 0x7f 0x0
+				0x0444 0x70 0x0
+				0x0510 0x17 0x0
+				0x04d4 0x54 0x0
+				0x04d8 0x07 0x0
+				0x0598 0xd4 0x0
+				0x059c 0x54 0x0
+				0x05a0 0xdb 0x0
+				0x05a4 0x3b 0x0
+				0x05a8 0x31 0x0
+				0x0584 0x24 0x0
+				0x0588 0xe4 0x0
+				0x058c 0xec 0x0
+				0x0590 0x3b 0x0
+				0x0594 0x36 0x0
+				0x0570 0xff 0x0
+				0x0574 0xff 0x0
+				0x0578 0xff 0x0
+				0x057c 0x7f 0x0
+				0x0580 0x66 0x0
+				0x04fc 0x00 0x0
+				0x04f8 0xc0 0x0
+				0x0460 0x30 0x0
+				0x0464 0xc0 0x0
+				0x05bc 0x0c 0x0
+				0x04dc 0x0d 0x0
+				0x0408 0x0c 0x0
+				0x0414 0x03 0x0
+				0x09a4 0x01 0x0
+				0x0c90 0x00 0x0
+				0x0c40 0x01 0x0
+				0x0c48 0x01 0x0
+				0x0c50 0x00 0x0
+				0x0cbc 0x00 0x0
+				0x0ce0 0x58 0x0
+				0x0048 0x90 0x0
+				0x0c1c 0xc1 0x0
+				0x0988 0x88 0x0
+				0x0998 0x0b 0x0
+				0x08dc 0x0d 0x0
+				0x09ec 0x01 0x0
+				0x0800 0x00 0x0
+				0x0844 0x03 0x0>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie0_clkreq_default
+			&pcie0_perst_default
+			&pcie0_wake_default>;
+
+		perst-gpio = <&tlmm 35 0>;
+		wake-gpio = <&tlmm 37 0>;
+
+		gdsc-core-vdd-supply = <&pcie_0_gdsc>;
+		vreg-1p2-supply = <&pm8195_1_l9>;
+		vreg-0p9-supply = <&pm8195_3_l5>;
+		vreg-cx-supply = <&VDD_CX_LEVEL>;
+
+		qcom,vreg-1p2-voltage-level = <1200000 1200000 24000>;
+		qcom,vreg-0p9-voltage-level = <880000 880000 24000>;
+		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_NOM 0>;
+
+		msi-parent = <&pcie0_msi>;
+
+		qcom,no-l0s-supported;
+		qcom,no-l1-supported;
+		qcom,no-l1ss-supported;
+		qcom,no-aux-clk-sync;
+
+		qcom,ep-latency = <10>;
+
+		qcom,slv-addr-space-size = <0x4000000>;
+
+		qcom,phy-status-offset = <0x814>;
+		qcom,phy-status-bit = <6>;
+		qcom,phy-power-down-offset = <0x840>;
+
+		qcom,boot-option = <0x1>;
+
+		linux,pci-domain = <0>;
+
+		qcom,pcie-phy-ver = <2110>;
+		qcom,aux-clk-freq = <20>; /* 19.2 MHz */
+
+		qcom,smmu-sid-base = <0x1d80>;
+
+		dma-coherent;
+		qcom,bw-scale = <RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen1 */
+				RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen2 */
+				RPMH_REGULATOR_LEVEL_NOM 100000000>; /* Gen3 */
+
+		iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
+			<0x100 &apps_smmu 0x1d81 0x1>,
+			<0x200 &apps_smmu 0x1d82 0x1>,
+			<0x300 &apps_smmu 0x1d83 0x1>,
+			<0x400 &apps_smmu 0x1d84 0x1>,
+			<0x500 &apps_smmu 0x1d85 0x1>,
+			<0x600 &apps_smmu 0x1d86 0x1>,
+			<0x700 &apps_smmu 0x1d87 0x1>,
+			<0x800 &apps_smmu 0x1d88 0x1>,
+			<0x900 &apps_smmu 0x1d89 0x1>,
+			<0xa00 &apps_smmu 0x1d8a 0x1>,
+			<0xb00 &apps_smmu 0x1d8b 0x1>,
+			<0xc00 &apps_smmu 0x1d8c 0x1>,
+			<0xd00 &apps_smmu 0x1d8d 0x1>,
+			<0xe00 &apps_smmu 0x1d8e 0x1>,
+			<0xf00 &apps_smmu 0x1d8f 0x1>;
+
+		interconnect-names = "icc_path";
+		interconnects = <&aggre1_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
+
+		clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+			<&rpmhcc RPMH_CXO_CLK>,
+			<&gcc GCC_PCIE_0_AUX_CLK>,
+			<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+			<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+			<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+			<&gcc GCC_PCIE_0_CLKREF_CLK>,
+			<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+			<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+			<&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
+			<&gcc GCC_PCIE_PHY_AUX_CLK>;
+
+		clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
+				"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
+				"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
+				"pcie_ldo", "pcie_0_slv_q2a_axi_clk",
+				"pcie_tbu_clk", "pcie_phy_refgen_clk",
+				"pcie_phy_aux_clk";
+
+		clock-frequency = <0>, <0>, <19200000>, <0>, <0>,
+					<0>, <0>, <0>, <0>, <100000000>, <0>;
+
+		clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>,
+						 <0>, <0>, <0>, <0>;
+
+		resets = <&gcc GCC_PCIE_0_BCR>,
+			<&gcc GCC_PCIE_0_PHY_BCR>;
+
+		reset-names = "pcie_0_core_reset",
+				"pcie_0_phy_reset";
+
+		pcie_rc0: pcie_rc0 {
+			reg = <0 0 0 0 0>;
+			pci-ids = "17cb:0109";
+		};
+	};
+
+	pcie0_msi: qcom,pcie0_msi@17a00040 {
+		compatible = "qcom,pci-msi";
+		msi-controller;
+		reg = <0x17a00040 0x0>;
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 864 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 865 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 866 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 867 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 868 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 869 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 870 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 871 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 872 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 873 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 874 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 875 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 876 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 877 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 878 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 879 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 880 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 881 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 882 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 883 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 884 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 885 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 886 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 887 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 888 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 889 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 890 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 891 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 892 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 893 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 894 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 895 IRQ_TYPE_EDGE_RISING>;
+	};
+
+	pcie1: qcom,pcie@1c10000 {
+		compatible = "qcom,pci-msm";
+		cell-index = <1>;
+
+		reg = <0x1c10000 0x3000>,
+			<0x01c16000 0x2000>,
+			<0x68000000 0xf1d>,
+			<0x68000f20 0xa8>,
+			<0x68001000 0x1000>,
+			<0x68100000 0x100000>,
+			<0x68200000 0x100000>,
+			<0x68300000 0x3d00000>,
+			<0x01fec004 0x4>,
+			<0x01c13000 0x1000>;
+
+		reg-names = "parf", "phy", "dm_core", "elbi",
+				"iatu", "conf", "io", "bars", "tcsr",
+				"mhi";
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges = <0x01000000 0x0 0x68200000 0x68200000 0x0 0x100000>,
+			<0x02000000 0x0 0x68300000 0x68300000 0x0 0x3d00000>;
+		interrupt-parent = <&pcie1>;
+		interrupts = <0 1 2 3 4>;
+		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
+				"int_d";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0xffffffff>;
+		interrupt-map = <0 0 0 0 &intc GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 1 &intc GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 2 &intc GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 3 &intc GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 4 &intc GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>;
+
+		qcom,tcsr = <0x0 0x0>;
+		qcom,phy-sequence = <0x0a40 0x03 0x0
+				0x0010 0x00 0x0
+				0x001c 0x31 0x0
+				0x0020 0x01 0x0
+				0x0024 0xde 0x0
+				0x0028 0x07 0x0
+				0x0030 0x4c 0x0
+				0x0034 0x06 0x0
+				0x0048 0x90 0x0
+				0x0058 0x0f 0x0
+				0x0074 0x06 0x0
+				0x0078 0x06 0x0
+				0x007c 0x16 0x0
+				0x0080 0x16 0x0
+				0x0084 0x36 0x0
+				0x0088 0x36 0x0
+				0x0094 0x08 0x0
+				0x00a4 0x42 0x0
+				0x00ac 0x0a 0x0
+				0x00b0 0x1a 0x0
+				0x00b4 0x14 0x0
+				0x00b8 0x34 0x0
+				0x00bc 0x82 0x0
+				0x00c4 0x68 0x0
+				0x00cc 0x55 0x0
+				0x00d0 0x55 0x0
+				0x00d4 0x03 0x0
+				0x00d8 0xab 0x0
+				0x00dc 0xaa 0x0
+				0x00e0 0x02 0x0
+				0x010c 0x02 0x0
+				0x0110 0x24 0x0
+				0x0118 0xb4 0x0
+				0x011c 0x03 0x0
+				0x0154 0x34 0x0
+				0x0158 0x01 0x0
+				0x016c 0x08 0x0
+				0x01ac 0xb9 0x0
+				0x01b0 0x1e 0x0
+				0x01b4 0x94 0x0
+				0x01b8 0x18 0x0
+				0x01bc 0x11 0x0
+				0x023c 0x11 0x0
+				0x0284 0x35 0x0
+				0x029c 0x12 0x0
+				0x0304 0x02 0x0
+				0x0408 0x0c 0x0
+				0x0414 0x03 0x0
+				0x0434 0x7f 0x0
+				0x0444 0x70 0x0
+				0x0460 0x30 0x0
+				0x0464 0x00 0x0
+				0x04d4 0x54 0x0
+				0x04d8 0x07 0x0
+				0x04dc 0x0d 0x0
+				0x04e8 0x00 0x0
+				0x04ec 0x0e 0x0
+				0x04f0 0x4a 0x0
+				0x04f4 0x0f 0x0
+				0x04f8 0xc0 0x0
+				0x04fc 0x00 0x0
+				0x0510 0x17 0x0
+				0x0518 0x1c 0x0
+				0x051c 0x03 0x0
+				0x0524 0x1e 0x0
+				0x0570 0xff 0x0
+				0x0574 0xff 0x0
+				0x0578 0xff 0x0
+				0x057c 0x7f 0x0
+				0x0580 0x66 0x0
+				0x0584 0x24 0x0
+				0x0588 0xe4 0x0
+				0x058c 0xec 0x0
+				0x0590 0x3b 0x0
+				0x0594 0x36 0x0
+				0x0598 0xd4 0x0
+				0x059c 0x54 0x0
+				0x05a0 0xdb 0x0
+				0x05a4 0x3b 0x0
+				0x05a8 0x31 0x0
+				0x05bc 0x0c 0x0
+				0x063c 0x11 0x0
+				0x0684 0x35 0x0
+				0x069c 0x12 0x0
+				0x0704 0x20 0x0
+				0x0808 0x0c 0x0
+				0x0814 0x03 0x0
+				0x0834 0x7f 0x0
+				0x0844 0x70 0x0
+				0x0860 0x30 0x0
+				0x0864 0x00 0x0
+				0x08d4 0x54 0x0
+				0x08d8 0x07 0x0
+				0x08dc 0x0d 0x0
+				0x08e8 0x00 0x0
+				0x08ec 0x0e 0x0
+				0x08f0 0x4a 0x0
+				0x08f4 0x0f 0x0
+				0x08f8 0xc0 0x0
+				0x08fc 0x00 0x0
+				0x0910 0x17 0x0
+				0x0918 0x1c 0x0
+				0x091c 0x03 0x0
+				0x0924 0x1e 0x0
+				0x0970 0xff 0x0
+				0x0974 0xff 0x0
+				0x0978 0xff 0x0
+				0x097c 0x7f 0x0
+				0x0980 0x66 0x0
+				0x0984 0x24 0x0
+				0x0988 0xe4 0x0
+				0x098c 0xec 0x0
+				0x0990 0x3b 0x0
+				0x0994 0x36 0x0
+				0x0998 0xd4 0x0
+				0x099c 0x54 0x0
+				0x09a0 0xdb 0x0
+				0x09a4 0x3b 0x0
+				0x09a8 0x31 0x0
+				0x09bc 0x0c 0x0
+				0x0adc 0x05 0x0
+				0x0b88 0x88 0x0
+				0x0b98 0x0b 0x0
+				0x0ba4 0x01 0x0
+				0x0bec 0x01 0x0
+				0x0e0c 0x0d 0x0
+				0x0e14 0x07 0x0
+				0x0e1c 0xc1 0x0
+				0x0e40 0x01 0x0
+				0x0e48 0x01 0x0
+				0x0e90 0x00 0x0
+				0x0ebc 0x00 0x0
+				0x0ee0 0x58 0x0
+				0x0eb4 0x33 0x0
+				0x0a00 0x00 0x0
+				0x0a44 0x03 0x0>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie1_clkreq_default
+			&pcie1_perst_default
+			&pcie1_wake_default>;
+
+		perst-gpio = <&tlmm 175 0>;
+		wake-gpio = <&tlmm 177 0>;
+
+		gdsc-core-vdd-supply = <&pcie_1_gdsc>;
+		vreg-1p2-supply = <&pm8195_1_l9>;
+		vreg-0p9-supply = <&pm8195_3_l5>;
+		vreg-cx-supply = <&VDD_CX_LEVEL>;
+
+		qcom,vreg-1p2-voltage-level = <1200000 1200000 24000>;
+		qcom,vreg-0p9-voltage-level = <880000 880000 24000>;
+		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_NOM 0>;
+
+		msi-parent = <&pcie1_msi>;
+
+		qcom,no-l0s-supported;
+
+		qcom,ep-latency = <10>;
+
+		qcom,slv-addr-space-size = <0x4000000>;
+
+		qcom,phy-status-offset = <0xa14>;
+		qcom,phy-status-bit = <6>;
+		qcom,phy-power-down-offset = <0xa40>;
+
+		qcom,boot-option = <0x1>;
+
+		linux,pci-domain = <1>;
+
+		qcom,pcie-phy-ver = <2113>;
+		qcom,aux-clk-freq = <20>; /* 19.2 MHz */
+
+		qcom,smmu-sid-base = <0x1c80>;
+
+		dma-coherent;
+		qcom,bw-scale = <RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen1 */
+				RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen2 */
+				RPMH_REGULATOR_LEVEL_NOM 100000000>; /* Gen3 */
+
+		iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
+			<0x100 &apps_smmu 0x1c81 0x1>,
+			<0x200 &apps_smmu 0x1c82 0x1>,
+			<0x300 &apps_smmu 0x1c83 0x1>,
+			<0x400 &apps_smmu 0x1c84 0x1>,
+			<0x500 &apps_smmu 0x1c85 0x1>,
+			<0x600 &apps_smmu 0x1c86 0x1>,
+			<0x700 &apps_smmu 0x1c87 0x1>,
+			<0x800 &apps_smmu 0x1c88 0x1>,
+			<0x900 &apps_smmu 0x1c89 0x1>,
+			<0xa00 &apps_smmu 0x1c8a 0x1>,
+			<0xb00 &apps_smmu 0x1c8b 0x1>,
+			<0xc00 &apps_smmu 0x1c8c 0x1>,
+			<0xd00 &apps_smmu 0x1c8d 0x1>,
+			<0xe00 &apps_smmu 0x1c8e 0x1>,
+			<0xf00 &apps_smmu 0x1c8f 0x1>;
+
+		interconnect-names = "icc_path";
+		interconnects = <&aggre1_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>;
+
+		clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
+			<&rpmhcc RPMH_CXO_CLK>,
+			<&gcc GCC_PCIE_1_AUX_CLK>,
+			<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+			<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+			<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
+			<&gcc GCC_PCIE_1_CLKREF_CLK>,
+			<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
+			<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+			<&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
+			<&gcc GCC_PCIE_PHY_AUX_CLK>;
+
+		clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
+				"pcie_1_aux_clk", "pcie_1_cfg_ahb_clk",
+				"pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk",
+				"pcie_ldo", "pcie_1_slv_q2a_axi_clk",
+				"pcie_tbu_clk", "pcie_phy_refgen_clk",
+				"pcie_phy_aux_clk";
+
+		clock-frequency = <0>, <0>, <19200000>, <0>, <0>,
+					<0>, <0>, <0>, <0>, <100000000>, <0>;
+
+		clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>,
+						 <0>, <0>, <0>, <0>;
+
+		resets = <&gcc GCC_PCIE_1_BCR>,
+			<&gcc GCC_PCIE_1_PHY_BCR>;
+
+		reset-names = "pcie_1_core_reset",
+				"pcie_1_phy_reset";
+
+		pcie_rc1: pcie_rc1 {
+			reg = <0 0 0 0 0>;
+			pci-ids = "17cb:0109";
+		};
+	};
+
+	pcie1_msi: qcom,pcie1_msi@17a00040 {
+		compatible = "qcom,pci-msi";
+		msi-controller;
+		reg = <0x17a00040 0x0>;
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 896 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 897 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 898 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 899 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 900 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 901 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 902 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 903 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 904 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 905 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 906 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 907 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 908 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 909 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 910 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 911 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 912 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 913 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 914 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 915 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 916 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 917 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 918 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 919 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 920 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 921 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 922 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 923 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 924 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 925 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 926 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 927 IRQ_TYPE_EDGE_RISING>;
+	};
+
+	pcie2: qcom,pcie@1c18000 {
+		compatible = "qcom,pci-msm";
+		cell-index = <2>;
+
+		reg = <0x1c18000 0x3000>,
+			<0x01c1c000 0x2000>,
+			<0x70000000 0xf1d>,
+			<0x70000f20 0xa8>,
+			<0x70001000 0x1000>,
+			<0x70100000 0x100000>,
+			<0x70200000 0x100000>,
+			<0x70300000 0x3d00000>,
+			<0x01fec004 0x4>,
+			<0x01c1b000 0x1000>;
+
+		reg-names = "parf", "phy", "dm_core", "elbi",
+				"iatu", "conf", "io", "bars", "tcsr",
+				"mhi";
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges = <0x01000000 0x0 0x70200000 0x70200000 0x0 0x100000>,
+			<0x02000000 0x0 0x70300000 0x70300000 0x0 0x3d00000>;
+		interrupt-parent = <&pcie2>;
+		interrupts = <0 1 2 3 4>;
+		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
+				"int_d";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0xffffffff>;
+		interrupt-map = <0 0 0 0 &intc GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 1 &intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 2 &intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 3 &intc GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 4 &intc GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>;
+
+		qcom,tcsr = <0x0 0x0>;
+		qcom,phy-sequence = <0x0a40 0x03 0x0
+				0x0010 0x00 0x0
+				0x001c 0x31 0x0
+				0x0020 0x01 0x0
+				0x0024 0xde 0x0
+				0x0028 0x07 0x0
+				0x0030 0x4c 0x0
+				0x0034 0x06 0x0
+				0x0048 0x90 0x0
+				0x0058 0x0f 0x0
+				0x0074 0x06 0x0
+				0x0078 0x06 0x0
+				0x007c 0x16 0x0
+				0x0080 0x16 0x0
+				0x0084 0x36 0x0
+				0x0088 0x36 0x0
+				0x0094 0x08 0x0
+				0x00a4 0x42 0x0
+				0x00ac 0x0a 0x0
+				0x00b0 0x1a 0x0
+				0x00b4 0x14 0x0
+				0x00b8 0x34 0x0
+				0x00bc 0x82 0x0
+				0x00c4 0x68 0x0
+				0x00cc 0x55 0x0
+				0x00d0 0x55 0x0
+				0x00d4 0x03 0x0
+				0x00d8 0xab 0x0
+				0x00dc 0xaa 0x0
+				0x00e0 0x02 0x0
+				0x010c 0x02 0x0
+				0x0110 0x24 0x0
+				0x0118 0xb4 0x0
+				0x011c 0x03 0x0
+				0x0154 0x34 0x0
+				0x0158 0x01 0x0
+				0x016c 0x08 0x0
+				0x01ac 0xb9 0x0
+				0x01b0 0x1e 0x0
+				0x01b4 0x94 0x0
+				0x01b8 0x18 0x0
+				0x01bc 0x11 0x0
+				0x023c 0x11 0x0
+				0x0284 0x35 0x0
+				0x029c 0x12 0x0
+				0x0304 0x02 0x0
+				0x0408 0x0c 0x0
+				0x0414 0x03 0x0
+				0x0434 0x7f 0x0
+				0x0444 0x70 0x0
+				0x0460 0x30 0x0
+				0x0464 0x00 0x0
+				0x04d4 0x54 0x0
+				0x04d8 0x07 0x0
+				0x04dc 0x0d 0x0
+				0x04e8 0x00 0x0
+				0x04ec 0x0e 0x0
+				0x04f0 0x4a 0x0
+				0x04f4 0x0f 0x0
+				0x04f8 0xc0 0x0
+				0x04fc 0x00 0x0
+				0x0510 0x17 0x0
+				0x0518 0x1c 0x0
+				0x051c 0x03 0x0
+				0x0524 0x1e 0x0
+				0x0570 0xff 0x0
+				0x0574 0xff 0x0
+				0x0578 0xff 0x0
+				0x057c 0x7f 0x0
+				0x0580 0x66 0x0
+				0x0584 0x24 0x0
+				0x0588 0xe4 0x0
+				0x058c 0xec 0x0
+				0x0590 0x3b 0x0
+				0x0594 0x36 0x0
+				0x0598 0xd4 0x0
+				0x059c 0x54 0x0
+				0x05a0 0xdb 0x0
+				0x05a4 0x3b 0x0
+				0x05a8 0x31 0x0
+				0x05bc 0x0c 0x0
+				0x063c 0x11 0x0
+				0x0684 0x35 0x0
+				0x069c 0x12 0x0
+				0x0704 0x20 0x0
+				0x0808 0x0c 0x0
+				0x0814 0x03 0x0
+				0x0834 0x7f 0x0
+				0x0844 0x70 0x0
+				0x0860 0x30 0x0
+				0x0864 0x00 0x0
+				0x08d4 0x54 0x0
+				0x08d8 0x07 0x0
+				0x08dc 0x0d 0x0
+				0x08e8 0x00 0x0
+				0x08ec 0x0e 0x0
+				0x08f0 0x4a 0x0
+				0x08f4 0x0f 0x0
+				0x08f8 0xc0 0x0
+				0x08fc 0x00 0x0
+				0x0910 0x17 0x0
+				0x0918 0x1c 0x0
+				0x091c 0x03 0x0
+				0x0924 0x1e 0x0
+				0x0970 0xff 0x0
+				0x0974 0xff 0x0
+				0x0978 0xff 0x0
+				0x097c 0x7f 0x0
+				0x0980 0x66 0x0
+				0x0984 0x24 0x0
+				0x0988 0xe4 0x0
+				0x098c 0xec 0x0
+				0x0990 0x3b 0x0
+				0x0994 0x36 0x0
+				0x0998 0xd4 0x0
+				0x099c 0x54 0x0
+				0x09a0 0xdb 0x0
+				0x09a4 0x3b 0x0
+				0x09a8 0x31 0x0
+				0x09bc 0x0c 0x0
+				0x0adc 0x05 0x0
+				0x0b88 0x88 0x0
+				0x0b98 0x0b 0x0
+				0x0ba4 0x01 0x0
+				0x0bec 0x01 0x0
+				0x0e0c 0x0d 0x0
+				0x0e14 0x07 0x0
+				0x0e1c 0xc1 0x0
+				0x0e40 0x01 0x0
+				0x0e48 0x01 0x0
+				0x0e90 0x00 0x0
+				0x0ebc 0x00 0x0
+				0x0ee0 0x58 0x0
+				0x0eb4 0x33 0x0
+				0x0a00 0x00 0x0
+				0x0a44 0x03 0x0>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie2_clkreq_default
+			&pcie2_perst_default
+			&pcie2_wake_default>;
+
+		perst-gpio = <&tlmm 102 0>;
+		wake-gpio = <&tlmm 104 0>;
+
+		gdsc-core-vdd-supply = <&pcie_2_gdsc>;
+		vreg-1p2-supply = <&pm8195_1_l9>;
+		vreg-0p9-supply = <&pm8195_3_l5>;
+		vreg-cx-supply = <&VDD_CX_LEVEL>;
+
+		qcom,vreg-1p2-voltage-level = <1200000 1200000 24000>;
+		qcom,vreg-0p9-voltage-level = <880000 880000 24000>;
+		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_NOM 0>;
+
+		msi-parent = <&pcie2_msi>;
+
+		qcom,no-l0s-supported;
+
+		qcom,ep-latency = <10>;
+
+		qcom,slv-addr-space-size = <0x4000000>;
+
+		qcom,phy-status-offset = <0xa14>;
+		qcom,phy-status-bit = <6>;
+		qcom,phy-power-down-offset = <0xa40>;
+
+		qcom,boot-option = <0x1>;
+
+		linux,pci-domain = <2>;
+
+		qcom,pcie-phy-ver = <2105>;
+		qcom,aux-clk-freq = <20>; /* 19.2 MHz */
+
+		qcom,smmu-sid-base = <0x1d00>;
+
+		dma-coherent;
+		qcom,bw-scale = <RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen1 */
+				RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen2 */
+				RPMH_REGULATOR_LEVEL_NOM 100000000>; /* Gen3 */
+
+		iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
+			<0x100 &apps_smmu 0x1d01 0x1>,
+			<0x200 &apps_smmu 0x1d02 0x1>,
+			<0x300 &apps_smmu 0x1d03 0x1>,
+			<0x400 &apps_smmu 0x1d04 0x1>,
+			<0x500 &apps_smmu 0x1d05 0x1>,
+			<0x600 &apps_smmu 0x1d06 0x1>,
+			<0x700 &apps_smmu 0x1d07 0x1>,
+			<0x800 &apps_smmu 0x1d08 0x1>,
+			<0x900 &apps_smmu 0x1d09 0x1>,
+			<0xa00 &apps_smmu 0x1d0a 0x1>,
+			<0xb00 &apps_smmu 0x1d0b 0x1>,
+			<0xc00 &apps_smmu 0x1d0c 0x1>,
+			<0xd00 &apps_smmu 0x1d0d 0x1>,
+			<0xe00 &apps_smmu 0x1d0e 0x1>,
+			<0xf00 &apps_smmu 0x1d0f 0x1>;
+
+		interconnect-names = "icc_path";
+		interconnects = <&aggre1_noc MASTER_PCIE_2 &mc_virt SLAVE_EBI1>;
+
+		clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
+			<&rpmhcc RPMH_CXO_CLK>,
+			<&gcc GCC_PCIE_2_AUX_CLK>,
+			<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
+			<&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
+			<&gcc GCC_PCIE_2_SLV_AXI_CLK>,
+			<&gcc GCC_PCIE_2_CLKREF_CLK>,
+			<&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
+			<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+			<&gcc GCC_PCIE2_PHY_REFGEN_CLK>,
+			<&gcc GCC_PCIE_PHY_AUX_CLK>;
+
+		clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
+				"pcie_2_aux_clk", "pcie_2_cfg_ahb_clk",
+				"pcie_2_mstr_axi_clk", "pcie_2_slv_axi_clk",
+				"pcie_ldo", "pcie_2_slv_q2a_axi_clk",
+				"pcie_tbu_clk", "pcie_phy_refgen_clk",
+				"pcie_phy_aux_clk";
+
+		clock-frequency = <0>, <0>, <19200000>, <0>, <0>,
+					<0>, <0>, <0>, <0>, <100000000>, <0>;
+
+		clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>,
+						 <0>, <0>, <0>, <0>;
+
+		resets = <&gcc GCC_PCIE_2_BCR>,
+			<&gcc GCC_PCIE_2_PHY_BCR>;
+
+		reset-names = "pcie_2_core_reset",
+				"pcie_2_phy_reset";
+
+		pcie_rc2: pcie_rc2 {
+			reg = <0 0 0 0 0>;
+			pci-ids = "17cb:0109";
+		};
+	};
+
+	pcie2_msi: qcom,pcie2_msi@17a00040 {
+		compatible = "qcom,pci-msi";
+		msi-controller;
+		reg = <0x17a00040 0x0>;
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 832 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 833 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 834 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 835 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 836 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 837 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 838 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 839 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 840 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 841 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 842 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 843 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 844 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 845 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 846 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 847 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 848 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 849 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 850 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 851 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 852 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 853 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 854 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 855 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 856 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 857 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 858 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 859 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 860 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 861 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 862 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 863 IRQ_TYPE_EDGE_RISING>;
+	};
+
+	pcie3: qcom,pcie@1c08000 {
+		compatible = "qcom,pci-msm";
+		cell-index = <3>;
+
+		reg = <0x1c08000 0x3000>,
+			<0x1c0c000 0x4000>,
+			<0x40000000 0xf1d>,
+			<0x40000f20 0xa8>,
+			<0x40001000 0x1000>,
+			<0x40100000 0x100000>,
+			<0x40200000 0x100000>,
+			<0x40300000 0x1fd00000>,
+			<0x01c0b000 0x1000>;
+
+		reg-names = "parf", "phy", "dm_core", "elbi",
+				"iatu", "conf", "io", "bars",
+				"mhi";
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
+			<0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>;
+		interrupt-parent = <&pcie3>;
+		interrupts = <0 1 2 3 4>;
+		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
+				"int_d";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0xffffffff>;
+		interrupt-map = <0 0 0 0 &intc GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
+
+		qcom,phy-sequence = <0x0a40 0x03 0x0
+				0x0010 0x00 0x0
+				0x001c 0x31 0x0
+				0x0020 0x01 0x0
+				0x0024 0xde 0x0
+				0x0028 0x07 0x0
+				0x0030 0x4c 0x0
+				0x0034 0x06 0x0
+				0x0048 0x90 0x0
+				0x0044 0x1c 0x0
+				0x0058 0x0f 0x0
+				0x0074 0x06 0x0
+				0x0078 0x06 0x0
+				0x007c 0x16 0x0
+				0x0080 0x16 0x0
+				0x0084 0x36 0x0
+				0x0088 0x36 0x0
+				0x0094 0x08 0x0
+				0x00a4 0x42 0x0
+				0x00ac 0x0a 0x0
+				0x00b0 0x1a 0x0
+				0x00b4 0x14 0x0
+				0x00b8 0x34 0x0
+				0x00bc 0x82 0x0
+				0x00c4 0x68 0x0
+				0x00cc 0x55 0x0
+				0x00d0 0x55 0x0
+				0x00d4 0x03 0x0
+				0x00d8 0xab 0x0
+				0x00dc 0xaa 0x0
+				0x00e0 0x02 0x0
+				0x010c 0x02 0x0
+				0x0110 0x24 0x0
+				0x0118 0xb4 0x0
+				0x011c 0x03 0x0
+				0x0154 0x34 0x0
+				0x0158 0x01 0x0
+				0x016c 0x08 0x0
+				0x01ac 0xb9 0x0
+				0x01b0 0x1e 0x0
+				0x01b4 0x94 0x0
+				0x01b8 0x18 0x0
+				0x01bc 0x11 0x0
+				0x0284 0x35 0x0
+				0x023c 0x11 0x0
+				0x029c 0x12 0x0
+				0x0408 0x0c 0x0
+				0x0414 0x03 0x0
+				0x0434 0x7f 0x0
+				0x0444 0x70 0x0
+				0x0460 0x30 0x0
+				0x0464 0x00 0x0
+				0x04d4 0x54 0x0
+				0x04d8 0x07 0x0
+				0x04dc 0x0d 0x0
+				0x04e8 0x00 0x0
+				0x04ec 0x0e 0x0
+				0x04f0 0x4a 0x0
+				0x04f4 0x0f 0x0
+				0x04f8 0xc0 0x0
+				0x04fc 0x00 0x0
+				0x0510 0x17 0x0
+				0x0518 0x1c 0x0
+				0x051c 0x03 0x0
+				0x0524 0x1e 0x0
+				0x0570 0xff 0x0
+				0x0574 0xff 0x0
+				0x0578 0xff 0x0
+				0x057c 0x7f 0x0
+				0x0580 0x66 0x0
+				0x0584 0x24 0x0
+				0x0588 0xe4 0x0
+				0x058c 0xec 0x0
+				0x0590 0x3b 0x0
+				0x0594 0x36 0x0
+				0x0598 0xd4 0x0
+				0x059c 0x54 0x0
+				0x05a0 0xdb 0x0
+				0x05a4 0x3b 0x0
+				0x05a8 0x31 0x0
+				0x05bc 0x0c 0x0
+				0x0684 0x35 0x0
+				0x063c 0x11 0x0
+				0x069c 0x12 0x0
+				0x0808 0x0c 0x0
+				0x0814 0x03 0x0
+				0x0834 0x7f 0x0
+				0x0844 0x70 0x0
+				0x0860 0x30 0x0
+				0x0864 0x00 0x0
+				0x08d4 0x54 0x0
+				0x08d8 0x07 0x0
+				0x08dc 0x0d 0x0
+				0x08e8 0x00 0x0
+				0x08ec 0x0e 0x0
+				0x08f0 0x4a 0x0
+				0x08f4 0x0f 0x0
+				0x08f8 0xc0 0x0
+				0x08fc 0x00 0x0
+				0x0910 0x17 0x0
+				0x0918 0x1c 0x0
+				0x091c 0x03 0x0
+				0x0924 0x1e 0x0
+				0x0970 0xff 0x0
+				0x0974 0xff 0x0
+				0x0978 0xff 0x0
+				0x097c 0x7f 0x0
+				0x0980 0x66 0x0
+				0x0984 0x24 0x0
+				0x0988 0xe4 0x0
+				0x098c 0xec 0x0
+				0x0990 0x3b 0x0
+				0x0994 0x36 0x0
+				0x0998 0xd4 0x0
+				0x099c 0x54 0x0
+				0x09a0 0xdb 0x0
+				0x09a4 0x3b 0x0
+				0x09a8 0x31 0x0
+				0x09bc 0x0c 0x0
+				0x0adc 0x05 0x0
+				0x0b88 0x88 0x0
+				0x0b98 0x0b 0x0
+				0x0ba4 0x01 0x0
+				0x0bec 0x01 0x0
+				0x0e0c 0x0d 0x0
+				0x0e14 0x07 0x0
+				0x0e1c 0xc1 0x0
+				0x0e40 0x01 0x0
+				0x0e48 0x01 0x0
+				0x0e90 0x00 0x0
+				0x0ebc 0x00 0x0
+				0x0ee0 0x58 0x0
+				0x0eb4 0x33 0x0
+				0x2a40 0x03 0x0
+				0x2010 0x00 0x0
+				0x201c 0x31 0x0
+				0x2020 0x01 0x0
+				0x2024 0xde 0x0
+				0x2028 0x07 0x0
+				0x2030 0x4c 0x0
+				0x2034 0x06 0x0
+				0x2048 0x90 0x0
+				0x2044 0x1c 0x0
+				0x2058 0x0f 0x0
+				0x2074 0x06 0x0
+				0x2078 0x06 0x0
+				0x207c 0x16 0x0
+				0x2080 0x16 0x0
+				0x2084 0x36 0x0
+				0x2088 0x36 0x0
+				0x2094 0x08 0x0
+				0x20a4 0x42 0x0
+				0x20ac 0x0a 0x0
+				0x20b0 0x1a 0x0
+				0x20b4 0x14 0x0
+				0x20b8 0x34 0x0
+				0x20bc 0x82 0x0
+				0x20c4 0x68 0x0
+				0x20cc 0x55 0x0
+				0x20d0 0x55 0x0
+				0x20d4 0x03 0x0
+				0x20d8 0xab 0x0
+				0x20dc 0xaa 0x0
+				0x20e0 0x02 0x0
+				0x210c 0x02 0x0
+				0x2110 0x24 0x0
+				0x2118 0xb4 0x0
+				0x211c 0x03 0x0
+				0x2154 0x34 0x0
+				0x2158 0x01 0x0
+				0x216c 0x08 0x0
+				0x21ac 0xb9 0x0
+				0x21b0 0x1e 0x0
+				0x21b4 0x94 0x0
+				0x21b8 0x18 0x0
+				0x21bc 0x11 0x0
+				0x2284 0x35 0x0
+				0x223c 0x11 0x0
+				0x229c 0x12 0x0
+				0x2408 0x0c 0x0
+				0x2414 0x03 0x0
+				0x2434 0x7f 0x0
+				0x2444 0x70 0x0
+				0x2460 0x30 0x0
+				0x2464 0x00 0x0
+				0x24d4 0x54 0x0
+				0x24d8 0x07 0x0
+				0x24dc 0x0d 0x0
+				0x24e8 0x00 0x0
+				0x24ec 0x0e 0x0
+				0x24f0 0x4a 0x0
+				0x24f4 0x0f 0x0
+				0x24f8 0xc0 0x0
+				0x24fc 0x00 0x0
+				0x2510 0x17 0x0
+				0x2518 0x1c 0x0
+				0x251c 0x03 0x0
+				0x2524 0x1e 0x0
+				0x2570 0xff 0x0
+				0x2574 0xff 0x0
+				0x2578 0xff 0x0
+				0x257c 0x7f 0x0
+				0x2580 0x66 0x0
+				0x2584 0x24 0x0
+				0x2588 0xe4 0x0
+				0x258c 0xec 0x0
+				0x2590 0x3b 0x0
+				0x2594 0x36 0x0
+				0x2598 0xd4 0x0
+				0x259c 0x54 0x0
+				0x25a0 0xdb 0x0
+				0x25a4 0x3b 0x0
+				0x25a8 0x31 0x0
+				0x25bc 0x0c 0x0
+				0x2684 0x35 0x0
+				0x263c 0x11 0x0
+				0x269c 0x12 0x0
+				0x2808 0x0c 0x0
+				0x2814 0x03 0x0
+				0x2834 0x7f 0x0
+				0x2844 0x70 0x0
+				0x2860 0x30 0x0
+				0x2864 0x00 0x0
+				0x28d4 0x54 0x0
+				0x28d8 0x07 0x0
+				0x28dc 0x0d 0x0
+				0x28e8 0x00 0x0
+				0x28ec 0x0e 0x0
+				0x28f0 0x4a 0x0
+				0x28f4 0x0f 0x0
+				0x28f8 0xc0 0x0
+				0x28fc 0x00 0x0
+				0x2910 0x17 0x0
+				0x2918 0x1c 0x0
+				0x291c 0x03 0x0
+				0x2924 0x1e 0x0
+				0x2970 0xff 0x0
+				0x2974 0xff 0x0
+				0x2978 0xff 0x0
+				0x297c 0x7f 0x0
+				0x2980 0x66 0x0
+				0x2984 0x24 0x0
+				0x2988 0xe4 0x0
+				0x298c 0xec 0x0
+				0x2990 0x3b 0x0
+				0x2994 0x36 0x0
+				0x2998 0xd4 0x0
+				0x299c 0x54 0x0
+				0x29a0 0xdb 0x0
+				0x29a4 0x3b 0x0
+				0x29a8 0x31 0x0
+				0x29bc 0x0c 0x0
+				0x2adc 0x05 0x0
+				0x2b88 0x88 0x0
+				0x2b98 0x0b 0x0
+				0x2ba4 0x01 0x0
+				0x2bec 0x01 0x0
+				0x2e0c 0x0d 0x0
+				0x2e14 0x07 0x0
+				0x2e1c 0xc1 0x0
+				0x2e40 0x01 0x0
+				0x2e48 0x01 0x0
+				0x2e90 0x00 0x0
+				0x2ebc 0x00 0x0
+				0x2ee0 0x58 0x0
+				0x2eb4 0x33 0x0
+				0x0a00 0x00 0x0
+				0x0a44 0x03 0x0>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie3_clkreq_default
+			&pcie3_perst_default
+			&pcie3_wake_default>;
+
+		perst-gpio = <&tlmm 178 0>;
+		wake-gpio = <&tlmm 56 0>;
+
+		gdsc-core-vdd-supply = <&pcie_3_gdsc>;
+		vreg-1p2-supply = <&pm8195_1_l9>;
+		vreg-0p9-supply = <&pm8195_3_l5>;
+		vreg-cx-supply = <&VDD_CX_LEVEL>;
+
+		qcom,vreg-1p2-voltage-level = <1200000 1200000 24000>;
+		qcom,vreg-0p9-voltage-level = <880000 880000 24000>;
+		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_NOM 0>;
+
+		msi-parent = <&pcie3_msi>;
+
+		qcom,no-l0s-supported;
+
+		qcom,ep-latency = <10>;
+
+		qcom,slv-addr-space-size = <0x20000000>;
+
+		qcom,phy-status-offset = <0xa14>;
+		qcom,phy-status-bit = <6>;
+		qcom,phy-power-down-offset = <0xa40>;
+
+		qcom,boot-option = <0x1>;
+
+		linux,pci-domain = <3>;
+
+		qcom,pcie-phy-ver = <2105>;
+		qcom,aux-clk-freq = <20>; /* 19.2 MHz */
+
+		qcom,smmu-sid-base = <0x1e00>;
+
+		dma-coherent;
+		qcom,bw-scale = <RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen1 */
+				RPMH_REGULATOR_LEVEL_LOW_SVS 19200000 /* Gen2 */
+				RPMH_REGULATOR_LEVEL_NOM 100000000>; /* Gen3 */
+
+		iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
+			<0x100 &apps_smmu 0x1e01 0x1>,
+			<0x200 &apps_smmu 0x1e02 0x1>,
+			<0x300 &apps_smmu 0x1e03 0x1>,
+			<0x400 &apps_smmu 0x1e04 0x1>,
+			<0x500 &apps_smmu 0x1e05 0x1>,
+			<0x600 &apps_smmu 0x1e06 0x1>,
+			<0x700 &apps_smmu 0x1e07 0x1>,
+			<0x800 &apps_smmu 0x1e08 0x1>,
+			<0x900 &apps_smmu 0x1e09 0x1>,
+			<0xa00 &apps_smmu 0x1e0a 0x1>,
+			<0xb00 &apps_smmu 0x1e0b 0x1>,
+			<0xc00 &apps_smmu 0x1e0c 0x1>,
+			<0xd00 &apps_smmu 0x1e0d 0x1>,
+			<0xe00 &apps_smmu 0x1e0e 0x1>,
+			<0xf00 &apps_smmu 0x1e0f 0x1>;
+
+		interconnect-names = "icc_path";
+		interconnects = <&aggre1_noc MASTER_PCIE_3 &mc_virt SLAVE_EBI1>;
+
+		clocks = <&gcc GCC_PCIE_3_PIPE_CLK>,
+			<&rpmhcc RPMH_CXO_CLK>,
+			<&gcc GCC_PCIE_3_AUX_CLK>,
+			<&gcc GCC_PCIE_3_CFG_AHB_CLK>,
+			<&gcc GCC_PCIE_3_MSTR_AXI_CLK>,
+			<&gcc GCC_PCIE_3_SLV_AXI_CLK>,
+			<&gcc GCC_PCIE_3_CLKREF_CLK>,
+			<&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>,
+			<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+			<&gcc GCC_PCIE3_PHY_REFGEN_CLK>,
+			<&gcc GCC_PCIE_PHY_AUX_CLK>;
+
+		clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
+				"pcie_3_aux_clk", "pcie_3_cfg_ahb_clk",
+				"pcie_3_mstr_axi_clk", "pcie_3_slv_axi_clk",
+				"pcie_ldo", "pcie_3_slv_q2a_axi_clk",
+				"pcie_tbu_clk", "pcie_phy_refgen_clk",
+				"pcie_phy_aux_clk";
+
+		clock-frequency = <0>, <0>, <19200000>, <0>, <0>,
+					<0>, <0>, <0>, <0>, <100000000>, <0>;
+
+		clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>,
+						 <0>, <0>, <0>, <0>;
+
+		resets = <&gcc GCC_PCIE_3_BCR>,
+			<&gcc GCC_PCIE_3_PHY_BCR>;
+
+		reset-names = "pcie_3_core_reset",
+				"pcie_3_phy_reset";
+
+		pcie_rc3: pcie_rc3 {
+			reg = <0 0 0 0 0>;
+			pci-ids = "17cb:0109";
+		};
+	};
+
+	pcie3_msi: qcom,pcie3_msi@17a00040 {
+		compatible = "qcom,pci-msi";
+		msi-controller;
+		reg = <0x17a00040 0x0>;
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 800 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 801 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 802 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 803 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 804 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 805 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 806 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 807 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 808 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 809 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 810 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 811 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 812 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 813 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 814 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 815 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 816 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 817 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 818 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 819 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 820 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 821 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 822 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 823 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 824 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 825 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 826 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 827 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 828 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 829 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 830 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 831 IRQ_TYPE_EDGE_RISING>;
+	};
+};
+
diff --git a/qcom/sa8195p.dtsi b/qcom/sa8195p.dtsi
index 77cdf96d..1370f512 100644
--- a/qcom/sa8195p.dtsi
+++ b/qcom/sa8195p.dtsi
@@ -1,5 +1,6 @@
 #include "sdmshrike-v2.dtsi"
 #include "sa8195-pmic.dtsi"
+#include "sa8195p-pcie.dtsi"
 
 / {
 	model = "Qualcomm Technologies, Inc. SA8195P";