From c3e1184a5ff924c4d386f4eec494140bf8af2d9f Mon Sep 17 00:00:00 2001 From: Po-Jung Lai Date: Mon, 4 Oct 2021 17:10:26 -0700 Subject: [PATCH] ARM: dts: msm: gunyah: Add qtmr binding Add qtmr binding description and requirments which include compatible, reg, interrupts and interrupts name. Change-Id: I6bc11b30cb05876475bd43148b072e93dfaf5006 --- bindings/soc/qcom/qcom,gh-qtmr.txt | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 bindings/soc/qcom/qcom,gh-qtmr.txt diff --git a/bindings/soc/qcom/qcom,gh-qtmr.txt b/bindings/soc/qcom/qcom,gh-qtmr.txt new file mode 100644 index 00000000..5304b1cb --- /dev/null +++ b/bindings/soc/qcom/qcom,gh-qtmr.txt @@ -0,0 +1,27 @@ +QCT Gunyah Hypervisor irq Lending Test Driver + +The Gunyah Hypervisor Test Driver is used to validate gunyah hypervisor +functionality. It includes test node for gunyah irq lending between vms. +Qtime timer and irq will be lended between vms. + +Required properties: +- compatible: "qcom,gh-qtmr" +- reg: Pairs of physical base addresses and region sizes of + memory mapped registers. +- reg-names: Names of the bases for the above registers. Expected + bases are: "qtmr-base" +- interrupts: Lists the threshold IRQ. +- interrupt-names: Names of the interrupts. +- qcom,primary or qcom,secondary: primary is for PVM / secondary is for SVM + +Example: + + qcom,gh-qtimer@17425000{ + compatible = "qcom,gh-qtmr"; + reg = <0x17425000 0x1000>; + reg-names = "qtmr-base"; + interrupts = ; + interrupt-names = "qcom,qtmr-intr"; + qcom,primary; + }; +