From decaa3b21370c82b6c9f8f74283c8fde8252939d Mon Sep 17 00:00:00 2001
From: Archana Sriram <c_apsrir@qti.qualcomm.com>
Date: Wed, 20 Jul 2022 20:59:17 +0530
Subject: [PATCH] ARM: dts: msm: Add support for GPU SMMU context for Bengal

Add support for GPU SMMU context for Bengal.

Change-Id: I40c31ed4d6b0f6471843044e9a8405ff778437f6
---
 qcom/khaje.dtsi               |  2 ++
 qcom/msm-arm-smmu-bengal.dtsi | 50 +++++++++++++++++++++++++++++++++++
 2 files changed, 52 insertions(+)

diff --git a/qcom/khaje.dtsi b/qcom/khaje.dtsi
index 521a813f..82fb32f5 100644
--- a/qcom/khaje.dtsi
+++ b/qcom/khaje.dtsi
@@ -3609,6 +3609,8 @@ tpdm_turing_llm: tpdm@8861000 {
 		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
 		clock-names = "apb_pclk";
 	};
+
+	msm_gpu: qcom,kgsl-3d0@5900000 { };
 };
 
 #include "bengal-gdsc.dtsi"
diff --git a/qcom/msm-arm-smmu-bengal.dtsi b/qcom/msm-arm-smmu-bengal.dtsi
index a9c32eb5..8d8b5b5b 100644
--- a/qcom/msm-arm-smmu-bengal.dtsi
+++ b/qcom/msm-arm-smmu-bengal.dtsi
@@ -1,6 +1,56 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 &soc {
+	kgsl_smmu: kgsl-smmu@0x59a0000 {
+		status = "okay";
+		compatible = "qcom,qsmmu-v500";
+		reg = <0x59a0000 0x10000>,
+			<0x59c2000 0x20>;
+		reg-names = "base", "tcu-base";
+		#iommu-cells = <2>;
+		qcom,dynamic;
+		qcom,skip-init;
+		qcom,testbus-version = <1>;
+		qcom,no-dynamic-asid;
+		qcom,use-3-lvl-tables;
+		#global-interrupts = <1>;
+		qcom,regulator-names = "vdd";
+		vdd-supply = <&gpu_cx_gdsc>;
+
+		clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+			 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+			 <&gpucc GPU_CC_AHB_CLK>,
+			 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
+		clock-names = "gcc_gpu_memnoc_gfx",
+			      "gcc_gpu_snoc_dvm_gfx",
+			      "gpu_cc_ahb",
+			      "gpu_cc_hlos1_vote_gpu_smmu_clk";
+		#size-cells = <1>;
+		#address-cells = <1>;
+		ranges;
+		interrupts =	<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,actlr =
+			/* All CBs of GFX: +15 deep PF */
+			<0x0 0x3ff 0x30B>;
+
+		gfx_0_tbu: gfx_0_tbu@0x59c5000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x59c5000 0x1000>,
+				<0x59c2200 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x0 0x400>;
+			qcom,iova-width = <36>;
+		};
+	};
+
 	apps_smmu: apps-smmu@0xc600000 {
 		status = "okay";
 		compatible = "qcom,qsmmu-v500";