From 0cd29767d6c0030dc74d01feae45d5c33d7a3092 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Mon, 20 Jun 2022 16:51:38 +0530 Subject: [PATCH 1/2] ARM: dts: msm: Update GCC, GDSC and RPMHCC nodes for SDXPINN Update the GCC, GDSC and RPMHCC nodes for SDXPINN platform. While at it, configure RPMHCC and few GDSC nodes as dummy on RUMI platform. Change-Id: I1b4105e0806a8ab243e5550baba843b2e035c026 --- qcom/sdxpinn-rumi.dtsi | 52 +++++++++++++++++++++ qcom/sdxpinn.dtsi | 103 ++++++++++++++++++++++++++--------------- 2 files changed, 117 insertions(+), 38 deletions(-) diff --git a/qcom/sdxpinn-rumi.dtsi b/qcom/sdxpinn-rumi.dtsi index a2be1602..1daa913c 100644 --- a/qcom/sdxpinn-rumi.dtsi +++ b/qcom/sdxpinn-rumi.dtsi @@ -64,6 +64,24 @@ qcom,no-l1ss-supported; qcom,no-aux-clk-sync; }; + + bi_tcxo: bi_tcxo { + compatible = "fixed-factor-clock"; + clocks = <&xo_board>; + clock-mult = <1>; + clock-div = <4>; + #clock-cells = <0>; + clock-output-names = "bi_tcxo"; + }; + + bi_tcxo_ao: bi_tcxo_ao { + compatible = "fixed-factor-clock"; + clocks = <&xo_board>; + clock-mult = <1>; + clock-div = <4>; + #clock-cells = <0>; + clock-output-names = "bi_tcxo_ao"; + }; }; &qupv3_se1_2uart { @@ -147,3 +165,37 @@ &mhi_device { status = "ok"; }; + +&rpmhcc { + compatible = "fixed-clock"; + clock-output-names = "rpmh_clocks"; +}; + +&gcc { + clocks = <&bi_tcxo>, <&pcie20_phy_aux_clk>, <&pcie_1_pipe_clk>, <&pcie_2_pipe_clk>, + <&pcie_pipe_clk>, <&sleep_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; +}; + +&gcc_emac0_gdsc { + compatible = "regulator-fixed"; +}; + +&gcc_emac1_gdsc { + compatible = "regulator-fixed"; +}; + +&gcc_pcie_1_phy_gdsc { + compatible = "regulator-fixed"; +}; + +&gcc_pcie_2_gdsc { + compatible = "regulator-fixed"; +}; + +&gcc_pcie_phy_gdsc { + compatible = "regulator-fixed"; +}; + +&gcc_usb3_phy_gdsc { + compatible = "regulator-fixed"; +}; diff --git a/qcom/sdxpinn.dtsi b/qcom/sdxpinn.dtsi index aacf2c66..a7da0ea2 100644 --- a/qcom/sdxpinn.dtsi +++ b/qcom/sdxpinn.dtsi @@ -265,6 +265,11 @@ , ; }; + + rpmhcc: clock-controller { + compatible = "qcom,sdxpinn-rpmh-clk"; + #clock-cells = <1>; + }; }; }; @@ -452,7 +457,7 @@ clocks { xo_board: xo_board { compatible = "fixed-clock"; - clock-frequency = <19200000>; + clock-frequency = <76800000>; clock-output-names = "xo_board"; #clock-cells = <0>; }; @@ -500,95 +505,117 @@ }; }; - bi_tcxo: bi_tcxo { - compatible = "fixed-factor-clock"; - clocks = <&xo_board>; - clock-mult = <1>; - clock-div = <1>; - #clock-cells = <0>; - clock-output-names = "bi_tcxo"; - }; - - bi_tcxo_ao: bi_tcxo_ao { - compatible = "fixed-factor-clock"; - clocks = <&xo_board>; - clock-mult = <1>; - clock-div = <1>; - #clock-cells = <0>; - clock-output-names = "bi_tcxo_ao"; - }; - - rpmhcc: clock-controller { - compatible = "fixed-clock"; - clock-output-names = "rpmh_clocks"; - clock-frequency = <19200000>; - #clock-cells = <1>; - }; - gcc: clock-controller@80000 { - compatible = "qcom,dummycc"; - clock-output-names = "gcc_clocks"; + compatible = "qcom,sdxpinn-gcc", "syscon"; + reg = <0x80000 0x1f4200>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MXA_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&pcie20_phy_aux_clk>, + <&pcie_1_pipe_clk>, + <&pcie_2_pipe_clk>, + <&pcie_pipe_clk>, + <&sleep_clk>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + clock-names = "bi_tcxo", + "pcie20_phy_aux_clk", + "pcie_1_pipe_clk", + "pcie_2_pipe_clk", + "pcie_pipe_clk", + "sleep_clk", + "usb3_phy_wrapper_gcc_usb30_pipe_clk"; #clock-cells = <1>; #reset-cells = <1>; }; /* GCC GDSCs */ gcc_emac0_gdsc: qcom,gdsc@f1004 { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; + reg = <0xf1004 0x4>; regulator-name = "gcc_emac0_gdsc"; + parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; qcom,support-hw-trigger; }; gcc_emac1_gdsc: qcom,gdsc@f2004 { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; + reg = <0xf2004 0x4>; regulator-name = "gcc_emac1_gdsc"; + parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; qcom,support-hw-trigger; }; gcc_pcie_1_gdsc: qcom,gdsc@e7004 { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; + reg = <0xe7004 0x4>; regulator-name = "gcc_pcie_1_gdsc"; + parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; qcom,support-hw-trigger; }; gcc_pcie_1_phy_gdsc: qcom,gdsc@d6004 { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; + reg = <0xd6004 0x4>; regulator-name = "gcc_pcie_1_phy_gdsc"; + parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; qcom,support-hw-trigger; }; gcc_pcie_2_gdsc: qcom,gdsc@e8004 { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; + reg = <0xe8004 0x4>; regulator-name = "gcc_pcie_2_gdsc"; + parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; qcom,support-hw-trigger; }; gcc_pcie_2_phy_gdsc: qcom,gdsc@ee004 { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; + reg = <0xee004 0x4>; regulator-name = "gcc_pcie_2_phy_gdsc"; + parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; qcom,support-hw-trigger; }; gcc_pcie_gdsc: qcom,gdsc@d3004 { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; + reg = <0xd3004 0x4>; regulator-name = "gcc_pcie_gdsc"; + parent-supply = <&VDD_MXA_LEVEL>; + qcom,retain-regs; qcom,support-hw-trigger; }; gcc_pcie_phy_gdsc: qcom,gdsc@d4004 { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; + reg = <0xd4004 0x4>; regulator-name = "gcc_pcie_phy_gdsc"; + parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; qcom,support-hw-trigger; }; gcc_usb30_gdsc: qcom,gdsc@a7004 { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; + reg = <0xa7004 0x4>; regulator-name = "gcc_usb30_gdsc"; + parent-supply = <&VDD_MXA_LEVEL>; + qcom,retain-regs; }; gcc_usb3_phy_gdsc: qcom,gdsc@a8008 { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; + reg = <0xa8008 0x4>; regulator-name = "gcc_usb3_phy_gdsc"; + parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; }; qnand_1: nand@1c98000 { From f63ea151cfa621c1ec28d68b712e5faf8ff2c052 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Wed, 27 Jul 2022 17:58:44 +0530 Subject: [PATCH 2/2] ARM: dts: msm: Add support for DEBUGCC node for SDXPINN Add the support for debug clock controller node for SDXPINN platform. Change-Id: I17edde591410b356bba0736721924f534d6d1112 --- qcom/sdxpinn-rumi.dtsi | 5 +++++ qcom/sdxpinn.dtsi | 22 ++++++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/qcom/sdxpinn-rumi.dtsi b/qcom/sdxpinn-rumi.dtsi index 1daa913c..28a223da 100644 --- a/qcom/sdxpinn-rumi.dtsi +++ b/qcom/sdxpinn-rumi.dtsi @@ -171,6 +171,11 @@ clock-output-names = "rpmh_clocks"; }; +&debugcc { + clocks = <&bi_tcxo>, <&gcc 0>; + clock-names = "xo_clk_src", "gcc"; +}; + &gcc { clocks = <&bi_tcxo>, <&pcie20_phy_aux_clk>, <&pcie_1_pipe_clk>, <&pcie_2_pipe_clk>, <&pcie_pipe_clk>, <&sleep_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; diff --git a/qcom/sdxpinn.dtsi b/qcom/sdxpinn.dtsi index a7da0ea2..450006e6 100644 --- a/qcom/sdxpinn.dtsi +++ b/qcom/sdxpinn.dtsi @@ -529,6 +529,28 @@ #reset-cells = <1>; }; + apsscc: syscon@17aa0000 { + compatible = "syscon"; + reg = <0x17aa0000 0x1c>; + }; + + mccc: syscon@190ba000 { + compatible = "syscon"; + reg = <0x190ba000 0x54>; + }; + + debugcc: clock-controller@0 { + compatible = "qcom,sdxpinn-debugcc"; + qcom,apsscc = <&apsscc>; + qcom,gcc = <&gcc>; + qcom,mccc = <&mccc>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc 0>; + clock-names = "xo_clk_src", + "gcc"; + #clock-cells = <1>; + }; + /* GCC GDSCs */ gcc_emac0_gdsc: qcom,gdsc@f1004 { compatible = "qcom,gdsc";