diff --git a/Kbuild b/Kbuild
index a42d25dd..7852f7d4 100644
--- a/Kbuild
+++ b/Kbuild
@@ -8,6 +8,10 @@ dtbo-y += kalama-vidc.dtbo
 dtbo-y += kalama-vidc-v2.dtbo
 endif
 
+ifeq ($(CONFIG_ARCH_ANORAK), y)
+dtbo-y += anorak-vidc.dtbo
+endif
+
 always-y    := $(dtb-y) $(dtbo-y)
 subdir-y    := $(dts-dirs)
-clean-files    := *.dtb *.dtbo
\ No newline at end of file
+clean-files    := *.dtb *.dtbo
diff --git a/anorak-vidc.dts b/anorak-vidc.dts
new file mode 100644
index 00000000..42421168
--- /dev/null
+++ b/anorak-vidc.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-anorak.h>
+#include <dt-bindings/interconnect/qcom,anorak.h>
+#include <dt-bindings/clock/qcom,videocc-anorak.h>
+#include "anorak-vidc.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Anorak";
+	compatible = "qcom,anorak";
+	qcom,msm-id = <549 0x10000>;
+	qcom,board-id = <0 0>;
+};
diff --git a/anorak-vidc.dtsi b/anorak-vidc.dtsi
new file mode 100644
index 00000000..a6de55fb
--- /dev/null
+++ b/anorak-vidc.dtsi
@@ -0,0 +1,110 @@
+&soc {
+	msm_vidc: qcom,vidc@aa00000 {
+		compatible = "qcom,msm-vidc", "qcom,msm-vidc-anorak", "qcom,msm-vidc-iris3";
+		status = "okay";
+		reg = <0x0aa00000 0xF0000>;
+		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+		memory-region = <&video_mem>;
+		pas-id = <9>;
+
+		/* IOMMU Config */
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* LLCC Cache */
+		cache-slice-names = "vidsc0";
+
+		/* Supply */
+		iris-ctl-supply = <&video_cc_mvs0c_gdsc>;
+		vcodec-supply = <&video_cc_mvs0_gdsc>;
+
+		/* Clocks */
+		clock-names = "gcc_video_axi0",
+			"core_clk", "vcodec_clk", "video_cc_mvs0_clk_src";
+		clock-ids = <GCC_VIDEO_AXI0_CLK VIDEO_CC_MVS0C_CLK
+			VIDEO_CC_MVS0_CLK VIDEO_CC_MVS0_CLK_SRC>;
+		clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+			<&videocc VIDEO_CC_MVS0C_CLK>,
+			<&videocc VIDEO_CC_MVS0_CLK>,
+			<&videocc VIDEO_CC_MVS0_CLK_SRC>;
+		qcom,proxy-clock-names = "gcc_video_axi0",
+			"core_clk", "vcodec_clk", "video_cc_mvs0_clk_src";
+		/* Mask: Bit0: Clock Scaling, Bit1: Mem Retention*/
+		qcom,clock-configs = <0x0 0x0 0x0 0x1>;
+		qcom,allowed-clock-rates = <240000000 338000000
+			366000000 444000000 533000000>;
+
+		qcom,reg-presets = <0xB0088 0x0 0x11>;
+
+		/* Video Firmware ELF image name */
+		vidc,firmware-name = "vpu33_4v";
+
+		/* Bus Interconnects */
+		interconnect-names = "venus-cnoc", "venus-ddr", "venus-llcc";
+		interconnects = <&gem_noc MASTER_APPSS_PROC
+					&config_noc SLAVE_VENUS_CFG>,
+				<&mc_virt MASTER_LLCC
+					&mc_virt SLAVE_EBI1>,
+				<&mmss_noc MASTER_VIDEO
+					&gem_noc SLAVE_LLCC>;
+		/* Bus BW range (low, high) for each bus */
+		qcom,bus-range-kbps = <1000 1000
+					1000 15000000
+					1000 15000000>;
+
+		/* MMUs */
+		non_secure_pixel_cb {
+			compatible = "qcom,msm-vidc,context-bank";
+			label = "venus_ns_pixel";
+			iommus = <&apps_smmu 0x0987 0x0400>;
+			qcom,iommu-dma-addr-pool = <0x00100000 0xdff00000>;
+			qcom,iommu-faults = "non-fatal";
+			virtual-addr-pool = <0x00100000 0xdff00000>;
+			dma-coherent;
+		};
+
+		non_secure_cb {
+			compatible = "qcom,msm-vidc,context-bank";
+			label = "venus_ns";
+			iommus = <&apps_smmu 0x0980 0x0400>;
+			qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>;
+			qcom,iommu-faults = "non-fatal";
+			virtual-addr-pool = <0x25800000 0xba800000>;
+			dma-coherent;
+		};
+
+		secure_non_pixel_cb {
+			compatible = "qcom,msm-vidc,context-bank";
+			label = "venus_sec_non_pixel";
+			iommus = <&apps_smmu 0x0984 0x0400>;
+			qcom,iommu-dma-addr-pool = <0x01000000 0x24800000>;
+			qcom,iommu-faults = "non-fatal";
+			qcom,iommu-vmid = <0xB>; /* VMID_CP_NON_PIXEL */
+			virtual-addr-pool = <0x01000000 0x24800000>;
+			qcom,secure-context-bank;
+		};
+
+		secure_bitstream_cb {
+			compatible = "qcom,msm-vidc,context-bank";
+			label = "venus_sec_bitstream";
+			iommus = <&apps_smmu 0x0981 0x0404>;
+			qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
+			qcom,iommu-faults = "non-fatal";
+			qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */
+			virtual-addr-pool = <0x00500000 0xdfb00000>;
+			qcom,secure-context-bank;
+		};
+
+		secure_pixel_cb {
+			compatible = "qcom,msm-vidc,context-bank";
+			label = "venus_sec_pixel";
+			iommus = <&apps_smmu 0x0983 0x0400>;
+			qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
+			qcom,iommu-faults = "non-fatal";
+			qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */
+			virtual-addr-pool = <0x00500000 0xdfb00000>;
+			qcom,secure-context-bank;
+		};
+	};
+};