diff --git a/qcom/kalama-pinn.dtsi b/qcom/kalama-pinn.dtsi
index 04c9ddf3..7473d300 100644
--- a/qcom/kalama-pinn.dtsi
+++ b/qcom/kalama-pinn.dtsi
@@ -1,3 +1,6 @@
+#include <dt-bindings/interconnect/qcom,kalama.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+
 &mdm0 {
 	compatible = "qcom,ext-pinn";
 	qcom,mdm-link-info = "0309_01.01.00";
@@ -6,3 +9,228 @@
 &modem_pas {
 	status = "disabled";
 };
+
+&pcie1 {
+	qcom,target-link-width = <1>; /* force X1 lane width */
+	qcom,panic-genspeed-mismatch;
+	qcom,no-l0s-supported;
+	qcom,target-link-speed = <4>; /* Set max link speed to Gen4 */
+	qcom,vreg-0p9-voltage-level = <912000 880000 193000>;
+	qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+					RPMH_REGULATOR_LEVEL_NOM 0>;
+	qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+					RPMH_REGULATOR_LEVEL_NOM 0>;
+	qcom,bw-scale = /* Gen1 */
+			<RPMH_REGULATOR_LEVEL_LOW_SVS
+			RPMH_REGULATOR_LEVEL_LOW_SVS
+			19200000
+			/* Gen2 */
+			RPMH_REGULATOR_LEVEL_LOW_SVS
+			RPMH_REGULATOR_LEVEL_LOW_SVS
+			19200000
+			/* Gen3 */
+			RPMH_REGULATOR_LEVEL_LOW_SVS
+			RPMH_REGULATOR_LEVEL_LOW_SVS
+			100000000
+			/* Gen4 */
+			RPMH_REGULATOR_LEVEL_NOM
+			RPMH_REGULATOR_LEVEL_NOM
+			100000000>;
+
+	qcom,pcie-phy-ver = <100>;
+	qcom,phy-sequence = <0x1240 0x03 0x0
+			0x0030 0x1d 0x0
+			0x0034 0x03 0x0
+			0x0078 0x01 0x0
+			0x007c 0x00 0x0
+			0x0080 0x51 0x0
+			0x00ac 0x34 0x0
+			0x0208 0x0c 0x0
+			0x020c 0x0a 0x0
+			0x0218 0x04 0x0
+			0x0220 0x16 0x0
+			0x0234 0x00 0x0
+			0x029c 0x80 0x0
+			0x02a0 0x7c 0x0
+			0x02b4 0x05 0x0
+			0x02e8 0x0a 0x0
+			0x030c 0x0d 0x0
+			0x0320 0x0b 0x0
+			0x0348 0x1c 0x0
+			0x0388 0x20 0x0
+			0x0394 0x30 0x0
+			0x03dc 0x09 0x0
+			0x03f4 0x14 0x0
+			0x03f8 0xb3 0x0
+			0x03fc 0x58 0x0
+			0x0400 0x9a 0x0
+			0x0404 0x26 0x0
+			0x0408 0xb6 0x0
+			0x040c 0xee 0x0
+			0x0410 0xdb 0x0
+			0x0414 0xdb 0x0
+			0x0418 0xa0 0x0
+			0x041c 0xdf 0x0
+			0x0420 0x78 0x0
+			0x0424 0x76 0x0
+			0x0428 0xff 0x0
+			0x0830 0x1d 0x0
+			0x0834 0x03 0x0
+			0x0878 0x01 0x0
+			0x087c 0x00 0x0
+			0x0880 0x51 0x0
+			0x08ac 0x34 0x0
+			0x0a08 0x0c 0x0
+			0x0a0c 0x0a 0x0
+			0x0a18 0x04 0x0
+			0x0a20 0x16 0x0
+			0x0a34 0x00 0x0
+			0x0a9c 0x80 0x0
+			0x0aa0 0x7c 0x0
+			0x0ab4 0x05 0x0
+			0x0ae8 0x0a 0x0
+			0x0b0c 0x0d 0x0
+			0x0b20 0x0b 0x0
+			0x0b48 0x1c 0x0
+			0x0b88 0x20 0x0
+			0x0b94 0x30 0x0
+			0x0bdc 0x09 0x0
+			0x0bf4 0x14 0x0
+			0x0bf8 0xb3 0x0
+			0x0bfc 0x58 0x0
+			0x0c00 0x9a 0x0
+			0x0c04 0x26 0x0
+			0x0c08 0xb6 0x0
+			0x0c0c 0xee 0x0
+			0x0c10 0xdb 0x0
+			0x0c14 0xdb 0x0
+			0x0c18 0xa0 0x0
+			0x0c1c 0xdf 0x0
+			0x0c20 0x78 0x0
+			0x0c24 0x76 0x0
+			0x0c28 0xff 0x0
+			0x0ea0 0x01 0x0
+			0x0eb4 0x00 0x0
+			0x0ec4 0x00 0x0
+			0x0ec8 0x1f 0x0
+			0x0ed4 0x12 0x0
+			0x0ed8 0x12 0x0
+			0x0edc 0xdb 0x0
+			0x0ee0 0x9a 0x0
+			0x0ee4 0x38 0x0
+			0x0ee8 0xb6 0x0
+			0x0eec 0x64 0x0
+			0x0ef0 0x1f 0x0
+			0x0ef4 0x1f 0x0
+			0x0ef8 0x1f 0x0
+			0x0efc 0x1f 0x0
+			0x0f00 0x1f 0x0
+			0x0f04 0x1f 0x0
+			0x0f0c 0x1f 0x0
+			0x0f14 0x1f 0x0
+			0x0f1c 0x1f 0x0
+			0x0f28 0x5b 0x0
+			0x1000 0x26 0x0
+			0x1004 0x03 0x0
+			0x1010 0x06 0x0
+			0x1014 0x16 0x0
+			0x1018 0x36 0x0
+			0x101c 0x04 0x0
+			0x1020 0x0a 0x0
+			0x1024 0x1a 0x0
+			0x1028 0x68 0x0
+			0x1030 0xab 0x0
+			0x1034 0xaa 0x0
+			0x1038 0x02 0x0
+			0x103c 0x12 0x0
+			0x1060 0xf8 0x0
+			0x1064 0x01 0x0
+			0x1070 0x06 0x0
+			0x1074 0x16 0x0
+			0x1078 0x36 0x0
+			0x107c 0x0a 0x0
+			0x1080 0x04 0x0
+			0x1084 0x0d 0x0
+			0x1088 0x41 0x0
+			0x1090 0xab 0x0
+			0x1094 0xaa 0x0
+			0x1098 0x01 0x0
+			0x109c 0x00 0x0
+			0x10bc 0x0a 0x0
+			0x10c0 0x01 0x0
+			0x10cc 0x62 0x0
+			0x10d0 0x02 0x0
+			0x10d8 0x40 0x0
+			0x10dc 0x14 0x0
+			0x10e0 0x90 0x0
+			0x10e4 0x82 0x0
+			0x10f4 0x0f 0x0
+			0x1110 0x08 0x0
+			0x1120 0x46 0x0
+			0x1124 0x04 0x0
+			0x1140 0x14 0x0
+			0x1164 0x34 0x0
+			0x1170 0xa0 0x0
+			0x1174 0x06 0x0
+			0x1184 0x88 0x0
+			0x1188 0x14 0x0
+			0x1198 0x0f 0x0
+			0x1378 0x2e 0x0
+			0x1390 0xcc 0x0
+			0x13f8 0x00 0x0
+			0x13fc 0x22 0x0
+			0x141c 0xc1 0x0
+			0x1490 0x00 0x0
+			0x14a0 0x16 0x0
+			0x1508 0x02 0x0
+			0x155c 0x2e 0x0
+			0x157c 0x03 0x0
+			0x1584 0x28 0x0
+			0x13dc 0x04 0x0
+			0x13e0 0x02 0x0
+			0x1418 0xc0 0x0
+			0x140c 0x1d 0x0
+			0x158c 0x0f 0x0
+			0x15ac 0xf2 0x0
+			0x15c0 0xf2 0x0
+			0x1828 0x50 0x0
+			0x1e24 0x01 0x0
+			0x1e28 0x01 0x0
+			0x1200 0x00 0x0
+			0x1244 0x03 0x0>;
+};
+
+
+&pcie1_rp {
+	#address-cells = <5>;
+	#size-cells = <0>;
+
+	mhi0: qcom,mhi@0 {
+		reg = <0 0 0 0 0 >;
+
+		esoc-names = "mdm";
+		esoc-0 = <&mdm0>;
+
+		interconnects = <&pcie_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>;
+		interconnect-names = "pcie_to_ddr";
+
+		qcom,mhi-bus-bw-cfg =
+		<0 0>, /* no vote */
+		<250000 0>, /* avg bw / AB: 2 GBps, peak bw / IB: no vote */
+		<500000 0>, /* avg bw / AB: 4 GBps, peak bw / IB: no vote */
+		<1000000 0>, /* avg bw / AB: 8 GBps, peak bw / IB: no vote */
+		<2000000 0>; /* avg bw / AB: 16 GBps, peak bw / IB: no vote */
+
+		qcom,iommu-group = <&mhi0_iommu_group>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		mhi0_iommu_group: mhi0_iommu_group {
+			qcom,iommu-msi-size = <0x1000>;
+			qcom,iommu-dma-addr-pool = <0x20000000 0x0fffffff>;
+			qcom,iommu-dma = "fastmap";
+			qcom,iommu-pagetable = "coherent";
+		};
+	};
+};