From 3eadd6fc409b0ce82ad04348fe622a734326f5b5 Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Mon, 25 Apr 2022 18:11:53 -0700 Subject: [PATCH 1/2] ARM: dts: msm: Enable DRV support on RC1 Enables DRV support for wifi attach. Change-Id: I28d2f9f03f984582ff58bd5c2872cb82f726f6fd --- qcom/kalama-pcie.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/kalama-pcie.dtsi b/qcom/kalama-pcie.dtsi index 9ccdd6d8..55c948e5 100644 --- a/qcom/kalama-pcie.dtsi +++ b/qcom/kalama-pcie.dtsi @@ -397,6 +397,7 @@ qcom,boot-option = <0x1>; qcom,no-l0s-supported; qcom,aux-clk-freq = <17>; /* 16.6 MHz */ + qcom,drv-name = "lpass"; qcom,eq-fmdc-t-min-phase23 = <1>; qcom,slv-addr-space-size = <0x20000000>; qcom,ep-latency = <10>; From 54a342bbc5e5b2b1d7dd381bbad7f0646b754d6f Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Fri, 29 Apr 2022 10:37:39 -0700 Subject: [PATCH 2/2] ARM: dts: msm: Use XO clk source for aux clk Phy HSR setting is turning phy FLL on to source aux clk. Turn off FLL and use XO clk source to generate aux clk. Also, set the L1SS inactivity timeout to 5ms. Change-Id: Ifc51a2ac0f3b6141ca55cacb91372c0a3c996c88 --- qcom/kalama-pcie.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/kalama-pcie.dtsi b/qcom/kalama-pcie.dtsi index 55c948e5..62fe93e1 100644 --- a/qcom/kalama-pcie.dtsi +++ b/qcom/kalama-pcie.dtsi @@ -398,6 +398,7 @@ qcom,no-l0s-supported; qcom,aux-clk-freq = <17>; /* 16.6 MHz */ qcom,drv-name = "lpass"; + qcom,drv-l1ss-timeout-us = <5000>; qcom,eq-fmdc-t-min-phase23 = <1>; qcom,slv-addr-space-size = <0x20000000>; qcom,ep-latency = <10>; @@ -546,7 +547,6 @@ 0x13f8 0x00 0x0 0x13fc 0x22 0x0 0x141c 0xc1 0x0 - 0x1450 0x03 0x0 0x1490 0x00 0x0 0x14a0 0x16 0x0 0x1508 0x02 0x0