diff --git a/qcom/lemans-rumi.dtsi b/qcom/lemans-rumi.dtsi index ed634a58..6d2a9510 100644 --- a/qcom/lemans-rumi.dtsi +++ b/qcom/lemans-rumi.dtsi @@ -9,3 +9,31 @@ &soc { }; + +&soc { + usb_emu_phy_0: usb_emu_phy@a784000 { + compatible = "qcom,usb-emu-phy"; + reg = <0x0a784000 0x9500>; + + qcom,emu-init-seq = <0xfffff 0x4 + 0x2110010 0x34 + 0x0110010 0x34 + 0xffff3 0x4 + 0xffff0 0x4 + 0x100000 0x20 + 0x0 0x20 + 0x1A0 0x20 + 0x100000 0x3c + 0x0 0x3c + 0x10060 0x3c + 0x0 0x4 + 0x9 0x14>; + }; +}; + +&usb0 { + dwc3@a600000 { + usb-phy = <&usb_emu_phy_0>, <&usb_nop_phy>; + maximum-speed = "high-speed"; + }; +}; diff --git a/qcom/lemans-usb.dtsi b/qcom/lemans-usb.dtsi new file mode 100644 index 00000000..311837de --- /dev/null +++ b/qcom/lemans-usb.dtsi @@ -0,0 +1,502 @@ +#include +#include + +&soc { + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa600000 0x100000>; + reg-names = "core_base"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = ; + interrupt-names = "pwr_event_irq"; + + USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,core-clk-rate-disconnected = <133333333>; + qcom,pm-qos-latency = <2>; + + qcom,host-poweroff-in-pm-suspend; + + interconnect-names = "usb-ddr", "ddr-usb"; + interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>; + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0xa600000 0xd93c>; + iommus = <&apps_smmu 0x080 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + interrupts = ; + usb-phy = <&usb2_phy0>, <&usb_qmp_phy0>; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + snps,usb2-gadget-lpm-disable; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,ssp-u3-u0-quirk; + tx-fifo-resize; + maximum-speed = "super-speed-plus"; + dr_mode = "otg"; + }; + }; + + /* Primary USB port related High Speed PHY */ + usb2_phy0: hsphy@88e4000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e4000 0x120>, + <0x088e3000 0x4>; + reg-names = "hsusb_phy_base", + "eud_enable_reg"; + + vdd-supply = <&L7A>; + vdda18-supply = <&L6C>; + vdda33-supply = <&L9A>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; + reset-names = "phy_reset"; + }; + + /* Primary USB port related QMP PHY */ + usb_qmp_phy0: ssphy@88e8000 { + compatible = "qcom,usb-ssphy-qmp-v2"; + reg = <0x88e8000 0x2000>, + <0x088e828c 0x4>; + reg-names = "qmp_phy_base", + "pcs_clamp_enable_reg"; + + vdd-supply = <&L7A>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&L1C>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, + <&usb3_phy_wrapper_gcc_usb30_prim_pipe_clk>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + + qcom,qmp-phy-reg-offset = + ; + + qcom,qmp-phy-init-seq = + /* */ + ; + }; + + usb1: ssusb@a800000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa800000 0x100000>; + reg-names = "core_base"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = ; + interrupt-names = "pwr_event_irq"; + + USB3_GDSC-supply = <&gcc_usb30_sec_gdsc>; + clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk"; + + resets = <&gcc GCC_USB30_SEC_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,core-clk-rate-disconnected = <133333333>; + qcom,pm-qos-latency = <2>; + + qcom,host-poweroff-in-pm-suspend; + + interconnect-names = "usb-ddr", "ddr-usb"; + interconnects = <&aggre1_noc MASTER_USB3_1 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_1>; + + dwc3@a800000 { + compatible = "snps,dwc3"; + reg = <0xa800000 0xd93c>; + interrupts = ; + iommus = <&apps_smmu 0x0A0 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + usb-phy = <&usb2_phy1>, <&usb_qmp_phy1>; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,ssp-u3-u0-quirk; + snps,is-utmi-l1-suspend; + snps,usb2-gadget-lpm-disable; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + tx-fifo-resize; + maximum-speed = "super-speed-plus"; + dr_mode = "otg"; + }; + }; + + /* Secondary USB port related High Speed PHY */ + usb2_phy1: hsphy@88e6000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e6000 0x120>; + reg-names = "hsusb_phy_base"; + + vdd-supply = <&L7A>; + vdda18-supply = <&L6C>; + vdda33-supply = <&L9A>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB_CLKREF_EN>; + clock-names = "ref_clk_src", "ref_clk"; + + resets = <&gcc GCC_USB2_PHY_SEC_BCR>; + reset-names = "phy_reset"; + }; + + /* Secondary USB port related QMP PHY */ + usb_qmp_phy1: ssphy@88ea000 { + compatible = "qcom,usb-ssphy-qmp-v2"; + reg = <0x88ea000 0x2000>, + <0x088ea28c 0x4>; + reg-names = "qmp_phy_base", + "pcs_clamp_enable_reg"; + + vdd-supply = <&L7A>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&L1C>; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK_SRC>, + <&usb3_phy_wrapper_gcc_usb30_sec_pipe_clk>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB_CLKREF_EN>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB3_PHY_SEC_BCR>, + <&gcc GCC_USB3PHY_PHY_SEC_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + + qcom,qmp-phy-reg-offset = + ; + + qcom,qmp-phy-init-seq = + /* */ + ; + }; + + /* Tertiary USB port related controller */ + usb2: hsusb@a400000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa400000 0x100000>; + reg-names = "core_base"; + + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = ; + interrupt-names = "pwr_event_irq"; + + USB3_GDSC-supply = <&gcc_usb20_prim_gdsc>; + clocks = <&gcc GCC_USB20_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_SLEEP_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk"; + + resets = <&gcc GCC_USB20_PRIM_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <120000000>; + + qcom,host-poweroff-in-pm-suspend; + qcom,default-mode-host; + + interconnect-names = "usb-ddr", "ddr-usb"; + interconnects = <&aggre1_noc MASTER_USB2 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB2>; + + dwc3@a400000 { + compatible = "snps,dwc3"; + reg = <0xa400000 0xd800>; + iommus = <&apps_smmu 0x020 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + interrupts = ; + usb-phy = <&usb2_phy2>, <&usb_nop_phy>; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + snps,usb2-gadget-lpm-disable; + tx-fifo-resize; + maximum-speed = "high-speed"; + dr_mode = "host"; + }; + }; + + /* Tertiary USB port related High Speed PHY */ + usb2_phy2: hsphy@88e7000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e7000 0x120>; + reg-names = "hsusb_phy_base"; + + vdd-supply = <&L7A>; + vdda18-supply = <&L6C>; + vdda33-supply = <&L9A>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB_CLKREF_EN>; + clock-names = "ref_clk_src", "ref_clk"; + + resets = <&gcc GCC_USB3_PHY_TERT_BCR>; + reset-names = "phy_reset"; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; +}; diff --git a/qcom/lemans.dtsi b/qcom/lemans.dtsi index 5f94561a..8953fc9c 100644 --- a/qcom/lemans.dtsi +++ b/qcom/lemans.dtsi @@ -1200,6 +1200,7 @@ #include "lemans-debug.dtsi" #include "lemans-qupv3.dtsi" #include "lemans-pcie.dtsi" +#include "lemans-usb.dtsi" &cam_cc_titan_top_gdsc { clocks = <&gcc GCC_CAMERA_AHB_CLK>;