From dabc6d838c06be6b69ce8cec334663fd20dea527 Mon Sep 17 00:00:00 2001 From: Khushal Bawankar Date: Thu, 23 Jun 2022 14:34:11 +0530 Subject: [PATCH] ARM: dts: msm: Update protected-clocks and compatible string for SC8180X Add protected-clocks for GCC, change compatible string for SCC and modify clock names for better readability. Change-Id: I1d3c03ff192775932c5cba848260193bc0a73e47 --- qcom/sa8195p-regulator.dtsi | 2 +- qcom/sdmshrike.dtsi | 57 +++++++++++-------------------------- 2 files changed, 17 insertions(+), 42 deletions(-) diff --git a/qcom/sa8195p-regulator.dtsi b/qcom/sa8195p-regulator.dtsi index 44dfbb50..05abc06b 100644 --- a/qcom/sa8195p-regulator.dtsi +++ b/qcom/sa8195p-regulator.dtsi @@ -425,7 +425,7 @@ rpmh-regulator-gfxlvl { compatible = "qcom,rpmh-arc-regulator"; qcom,resource-name = "gfx.lvl"; - VDD_GFX: + VDD_GFX_LEVEL: S10C_LEVEL: pm8195_2_s10_level: regulator-pm8195-2-s10-level { regulator-name = "pm8195_2_s10_level"; qcom,set = ; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 0e64125e..2bb13d80 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -706,19 +706,15 @@ vdd_cx-supply = <&VDD_CX_LEVEL>; vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; vdd_mm-supply = <&VDD_MMCX_LEVEL>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&rpmhcc RPMH_CXO_CLK_A>, - <&sleep_clk>; - clock-names = - "bi_tcxo", - "bi_tcxo_ao", - "sleep_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + protected-clocks = ; #clock-cells = <1>; #reset-cells = <1>; }; scc: clock-controller@2b10000 { - compatible = "qcom,sa8195-scc"; + compatible = "qcom,sc8180x-scc"; reg = <0x2b10000 0x30000>; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "bi_tcxo"; @@ -732,12 +728,9 @@ reg-names = "cc_base"; vdd_cx-supply = <&VDD_CX_LEVEL>; vdd_mx-supply = <&VDD_MX_LEVEL>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_GPU_GPLL0_CLK_SRC>, + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPU_GPLL0_CLK_SRC>, <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; - clock-names = "bi_tcxo", - "gcc_gpu_gpll0_clk_src", - "gcc_gpu_gpll0_div_clk_src"; + clock-names = "bi_tcxo", "gcc_gpu_gpll0_clk_src", "gcc_gpu_gpll0_div_clk_src"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -748,15 +741,10 @@ reg-names = "cc_base"; vdd_cx-supply = <&VDD_CX_LEVEL>; vdd_gdsc-supply = <&npu_core_gdsc>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_NPU_GPLL0_DIV_CLK_SRC>, - <&gcc GCC_NPU_GPLL0_CLK_SRC>, - <&gcc GCC_NPU_AXI_CLK>; - clock-names = - "bi_tcxo", - "gcc_npu_gpll0_div_clk_src", - "gcc_npu_gpll0_clk_src", - "gcc_npu_axi_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_NPU_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_NPU_GPLL0_CLK_SRC>, <&gcc GCC_NPU_AXI_CLK>; + clock-names = "bi_tcxo", "gcc_npu_gpll0_div_clk_src", + "gcc_npu_gpll0_clk_src", "gcc_npu_axi_clk"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -766,11 +754,8 @@ reg = <0xab00000 0x10000>; reg-names = "cc_base"; vdd_mm-supply = <&VDD_MMCX_LEVEL>; - clocks = <&gcc GCC_VIDEO_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = - "cfg_ahb_clk", - "bi_tcxo"; + clocks = <&gcc GCC_VIDEO_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>; + clock-names = "cfg_ahb_clk", "bi_tcxo"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -781,13 +766,8 @@ reg-name = "cc_base"; vdd_mm-supply = <&VDD_MMCX_LEVEL>; vdd_mx-supply = <&VDD_MX_LEVEL>; - clocks = <&gcc GCC_CAMERA_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&sleep_clk>; - clock-names = - "cfg_ahb_clk", - "bi_tcxo", - "sleep_clk"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + clock-names = "cfg_ahb_clk", "bi_tcxo", "sleep_clk"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -797,13 +777,8 @@ reg = <0xaf00000 0x20000>; reg-names = "cc_base"; vdd_mm-supply = <&VDD_MMCX_LEVEL>; - clocks = <&gcc GCC_DISP_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&sleep_clk>; - clock-names = - "cfg_ahb_clk", - "bi_tcxo", - "sleep_clk"; + clocks = <&gcc GCC_DISP_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + clock-names = "cfg_ahb_clk", "bi_tcxo", "sleep_clk"; #clock-cells = <1>; #reset-cells = <1>; };