From c8000cbaf81555d0fbc0be8935f73315dcc2ae94 Mon Sep 17 00:00:00 2001
From: Maulik Shah <mkshah@qti.qualcomm.com>
Date: Thu, 3 Mar 2022 15:15:56 +0530
Subject: [PATCH] ARM: dts: msm: Update RSC and PDC device nodes for sdmshrike

Update device node as per latest bindings. While at this also
add disp_rsc device.

Change-Id: Ic27268a2f264ac5cba3ed3277e3f4467f578d723
---
 qcom/sdmshrike.dtsi | 52 ++++++++++++++++++++++++++++++++++++++-------
 1 file changed, 44 insertions(+), 8 deletions(-)

diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi
index 0a83c587..5f4c55f2 100644
--- a/qcom/sdmshrike.dtsi
+++ b/qcom/sdmshrike.dtsi
@@ -492,19 +492,55 @@
 		label = "apps_rsc";
 		compatible = "qcom,rpmh-rsc";
 		reg = <0x18200000 0x10000>,
-			<0x18210000 0x10000>,
-			<0x18220000 0x10000>;
+		      <0x18210000 0x10000>,
+		      <0x18220000 0x10000>;
 		reg-names = "drv-0", "drv-1", "drv-2";
+		qcom,drv-count = <3>;
 		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
-		qcom,tcs-offset = <0xd00>;
-		qcom,drv-id = <2>;
-		qcom,tcs-config = <ACTIVE_TCS  2>,
-				<SLEEP_TCS   3>,
-				<WAKE_TCS    3>,
-				<CONTROL_TCS 1>;
 
+		apps_rsc_drv2: drv@2 {
+			qcom,drv-id = <2>;
+			qcom,tcs-offset = <0xd00>;
+			channel@0 {
+				qcom,tcs-config = <ACTIVE_TCS    2>,
+						  <SLEEP_TCS     3>,
+						  <WAKE_TCS      3>,
+						  <CONTROL_TCS   1>,
+						  <FAST_PATH_TCS 0>;
+			};
+		};
+	};
+
+	disp_rsc: rsc@af20000 {
+		label = "disp_rsc";
+		compatible = "qcom,rpmh-rsc";
+		reg = <0xaf20000 0x10000>;
+		reg-names = "drv-0";
+		qcom,drv-count = <1>;
+		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+
+		disp_rsc_drv0: drv@0 {
+			qcom,drv-id = <0>;
+			qcom,tcs-offset = <0x1c00>;
+			channel@0 {
+				qcom,tcs-config = <SLEEP_TCS     1>,
+						  <WAKE_TCS      1>,
+						  <ACTIVE_TCS    2>,
+						  <CONTROL_TCS   0>,
+						  <FAST_PATH_TCS 0>;
+			};
+		};
+	};
+
+	pdc: interrupt-controller@b220000 {
+		compatible = "qcom,pdc";
+		reg = <0xb220000 0x30000>, <0x17c000f0 0x64>;
+		qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&intc>;
+		interrupt-controller;
 	};
 
 	qupv3_id_1: geniqup@ac0000 {