From e0cd2447b11a5ebb22d8128302a242cb36cee599 Mon Sep 17 00:00:00 2001 From: Trishansh Bhardwaj Date: Wed, 22 Apr 2020 20:14:12 +0530 Subject: [PATCH] ARM: dts: msm: camera: Merge kmd 3.1 changes in kmd 4.0 ARM: dts: msm: Fix custom gpio tables for bengal ARM: dts: msm: Fix svs clock level for bengal ARM: dts: msm: camera: Add required clocks to tpg and cpas node ARM: dts: msm: camera: cpas: Add constituent paths for OPE ARM: dts: msm: Fix the reset gpio for rear aux camera ARM: dts: msm: Fix orientation of camera sensors ARM: dts: msm: camera: cci: Add cci version ARM: dts: msm: camera: cpas: Add camera fuse support ARM: dts: msm: camera: smmu: Fix camera SID issue ARM: dts: msm: camera: Add support to Cx Ipeak ARM: dts: msm: Fix orientation of front camera ARM: dts: msm: Add support to discard a region in dma space ARM: dts: msm: camera: Correct the clock rates for all modules ARM: dts: msm: Fix inverted image on front camera ARM: dts: msm: Add CAMNOC nodes in lagoon camera dtsi ARM: dts: msm: camera: Update fifo depth for OPE CDM ARM: dts: msm: Change the vdig voltage of bengal front camera ARM: dts: msm: Change the vdig voltage of bengal front camera ARM: dts: msm: camera: ope: Change BL fifo depth ARM: dts: msm: Add camera sensor nodes in MTP/CDP for lagoon ARM: dts: msm: Update clock header for lagoon ARM: dts: msm: Add csiphy and cci nodes in lagoon camera DT ARM: dts: msm: Change IPE Write port, IPE clock source for lagoon camera ARM: dts: msm: Change CSID and VFE interrupt name for lagoon camera ARM: dts: msm: Add csiphy3 and cci1 clients to cpas ARM: dts: msm: Add support for Scuba camera ARM: dts: msm: Fix Bus and TFE nodes in Scuba camera ARM: dts: msm: Add cci and csiphy support for Scuba camera ARM: dts: msm: Fix the phy regulator voltage ARM: dts: msm: Add Camera Sensor nodes for IDP/IDPS for scuba ARM: dts: msm: Update GPU Mitigation ARM: dts: msm: Fix compilation issue for scuba-camera-sensor-idp ARM: dts: msm: camera: cpas: Disable secure feature mask ARM: dts: msm: Update PHY version for bengal target ARM: dts: msm: Remove fuse setting for secure camera. CRs-Fixed: 2668666 Change-Id: I052654c8cc05043a63355ccd13582a87e993e42a --- bengal-camera-sensor-idp.dtsi | 38 +- bengal-camera-sensor-qrd.dtsi | 10 +- bengal-camera.dtsi | 180 ++++---- bindings/msm-cam-cci.txt | 2 + bindings/msm-cam-cpas.txt | 6 + bindings/msm-cam-csiphy.txt | 4 +- bindings/msm-cam-tpg.txt | 4 +- lagoon-camera-sensor-cdp.dtsi | 421 +++++++++++++++++ lagoon-camera-sensor-mtp.dtsi | 421 +++++++++++++++++ lagoon-camera.dtsi | 828 +++++++++++++++++++++++++++++++++- scuba-camera-sensor-idp.dtsi | 313 +++++++++++++ scuba-camera.dtsi | 766 +++++++++++++++++++++++++++++++ 12 files changed, 2874 insertions(+), 119 deletions(-) create mode 100644 lagoon-camera-sensor-cdp.dtsi create mode 100644 lagoon-camera-sensor-mtp.dtsi create mode 100644 scuba-camera-sensor-idp.dtsi create mode 100644 scuba-camera.dtsi diff --git a/bengal-camera-sensor-idp.dtsi b/bengal-camera-sensor-idp.dtsi index 65ac1994..48f40a98 100644 --- a/bengal-camera-sensor-idp.dtsi +++ b/bengal-camera-sensor-idp.dtsi @@ -118,8 +118,8 @@ &cam_sensor_rear1_reset_active>; pinctrl-1 = <&cam_sensor_mclk1_suspend &cam_sensor_rear1_reset_suspend>; - gpios = <&tlmm 19 0>, - <&tlmm 21 0>; + gpios = <&tlmm 21 0>, + <&tlmm 19 0>; gpio-reset = <1>; gpio-req-tbl-num = <0 1>; gpio-req-tbl-flags = <1 0>; @@ -145,8 +145,8 @@ "cam_clk"; rgltr-cntrl-support; pwm-switch; - rgltr-min-voltage = <1800000 2800000 1056000 0>; - rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-min-voltage = <1800000 2800000 1050000 0>; + rgltr-max-voltage = <1800000 2800000 1050000 0>; rgltr-load-current = <0 80000 105000 0>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; @@ -211,7 +211,7 @@ cell-index = <0>; compatible = "qcom,cam-sensor"; csiphy-sd-index = <0>; - sensor-position-roll = <90>; + sensor-position-roll = <270>; sensor-position-pitch = <0>; sensor-position-yaw = <180>; actuator-src = <&actuator_rear>; @@ -255,7 +255,7 @@ cell-index = <1>; compatible = "qcom,cam-sensor"; csiphy-sd-index = <1>; - sensor-position-roll = <90>; + sensor-position-roll = <270>; sensor-position-pitch = <0>; sensor-position-yaw = <180>; actuator-src = <&actuator_rear_aux>; @@ -278,8 +278,8 @@ &cam_sensor_rear1_reset_active>; pinctrl-1 = <&cam_sensor_mclk1_suspend &cam_sensor_rear1_reset_suspend>; - gpios = <&tlmm 19 0>, - <&tlmm 21 0>; + gpios = <&tlmm 21 0>, + <&tlmm 19 0>; gpio-reset = <1>; gpio-req-tbl-num = <0 1>; gpio-req-tbl-flags = <1 0>; @@ -299,9 +299,9 @@ cell-index = <2>; compatible = "qcom,cam-sensor"; csiphy-sd-index = <2>; - sensor-position-roll = <90>; + sensor-position-roll = <270>; sensor-position-pitch = <0>; - sensor-position-yaw = <180>; + sensor-position-yaw = <0>; eeprom-src = <&eeprom_front>; cam_vio-supply = <&L7P>; cam_vana-supply = <&L6P>; @@ -311,8 +311,8 @@ "cam_clk"; rgltr-cntrl-support; pwm-switch; - rgltr-min-voltage = <1800000 2800000 1056000 0>; - rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-min-voltage = <1800000 2800000 1050000 0>; + rgltr-max-voltage = <1800000 2800000 1050000 0>; rgltr-load-current = <0 80000 105000 0>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; @@ -329,10 +329,14 @@ <&tlmm 66 0>, <&tlmm 67 0>; gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-custom2 = <3>; gpio-req-tbl-num = <0 1>; gpio-req-tbl-flags = <1 0>; gpio-req-tbl-label = "CAMIF_MCLK2", - "CAM_RESET2"; + "CAM_RESET2", + "CAM_CSIMUX_OE0", + "CAM_CSIMUX_SEL0"; sensor-mode = <0>; cci-master = <1>; status = "ok"; @@ -347,7 +351,7 @@ cell-index = <3>; compatible = "qcom,cam-sensor"; csiphy-sd-index = <2>; - sensor-position-roll = <90>; + sensor-position-roll = <270>; sensor-position-pitch = <0>; sensor-position-yaw = <180>; led-flash-src = <&led_flash_rear_aux2>; @@ -378,10 +382,14 @@ <&tlmm 66 0>, <&tlmm 67 0>; gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-custom2 = <3>; gpio-req-tbl-num = <0 1>; gpio-req-tbl-flags = <1 0>; gpio-req-tbl-label = "CAMIF_MCLK3", - "CAM_RESET3"; + "CAM_RESET3", + "CAM_CSIMUX_OE1", + "CAM_CSIMUX_SEL1"; sensor-mode = <0>; cci-master = <0>; status = "ok"; diff --git a/bengal-camera-sensor-qrd.dtsi b/bengal-camera-sensor-qrd.dtsi index a4c93476..c6aa60f3 100644 --- a/bengal-camera-sensor-qrd.dtsi +++ b/bengal-camera-sensor-qrd.dtsi @@ -145,8 +145,8 @@ "cam_clk"; rgltr-cntrl-support; pwm-switch; - rgltr-min-voltage = <1800000 2800000 1056000 0>; - rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-min-voltage = <1800000 2800000 1050000 0>; + rgltr-max-voltage = <1800000 2800000 1050000 0>; rgltr-load-current = <0 80000 105000 0>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; @@ -301,7 +301,7 @@ cell-index = <2>; compatible = "qcom,cam-sensor"; csiphy-sd-index = <2>; - sensor-position-roll = <90>; + sensor-position-roll = <270>; sensor-position-pitch = <0>; sensor-position-yaw = <0>; eeprom-src = <&eeprom_front>; @@ -313,8 +313,8 @@ "cam_clk"; rgltr-cntrl-support; pwm-switch; - rgltr-min-voltage = <1800000 2800000 1056000 0>; - rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-min-voltage = <1800000 2800000 1050000 0>; + rgltr-max-voltage = <1800000 2800000 1050000 0>; rgltr-load-current = <0 80000 105000 0>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; diff --git a/bengal-camera.dtsi b/bengal-camera.dtsi index f771d374..a84ebde3 100644 --- a/bengal-camera.dtsi +++ b/bengal-camera.dtsi @@ -8,7 +8,7 @@ cam_csiphy0: qcom,csiphy0 { cell-index = <0>; - compatible = "qcom,csiphy-v2.0", "qcom,csiphy"; + compatible = "qcom,csiphy-v2.0.1", "qcom,csiphy"; reg = <0x05C52000 0x1000>; reg-names = "csiphy"; reg-cam-base = <0x52000>; @@ -30,15 +30,16 @@ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; clock-rates = <19200000 0 19200000 0>, - <341330000 0 200000000 0>, + <240000000 0 200000000 0>, <341330000 0 200000000 0>, <384000000 0 268800000 0>; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; cam_csiphy1: qcom,csiphy1 { cell-index = <1>; - compatible = "qcom,csiphy-v2.0", "qcom,csiphy"; + compatible = "qcom,csiphy-v2.0.1", "qcom,csiphy"; reg = <0x05C53000 0x1000>; reg-names = "csiphy"; reg-cam-base = <0x53000>; @@ -60,15 +61,16 @@ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; clock-rates = <19200000 0 19200000 0>, - <341330000 0 200000000 0>, + <240000000 0 200000000 0>, <341330000 0 200000000 0>, <384000000 0 268800000 0>; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; cam_csiphy2: qcom,csiphy2 { cell-index = <2>; - compatible = "qcom,csiphy-v2.0", "qcom,csiphy"; + compatible = "qcom,csiphy-v2.0.1", "qcom,csiphy"; reg = <0x05C54000 0x1000>; reg-names = "csiphy"; reg-cam-base = <0x54000>; @@ -90,15 +92,16 @@ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; clock-rates = <19200000 0 19200000 0>, - <341330000 0 200000000 0>, + <240000000 0 200000000 0>, <341330000 0 200000000 0>, <384000000 0 268800000 0>; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; cam_cci0: qcom,cci0 { cell-index = <0>; - compatible = "qcom,cci", "simple-bus"; + compatible = "qcom,cci-v1.2", "qcom,cci", "simple-bus"; #address-cells = <1>; #size-cells = <0>; reg = <0x05C1B000 0x1000>; @@ -197,8 +200,7 @@ msm_cam_smmu_tfe { compatible = "qcom,msm-cam-smmu-cb"; - iommus = <&apps_smmu 0x400 0x000>, - <&apps_smmu 0x401 0x000>; + iommus = <&apps_smmu 0x400 0x000>; qcom,iommu-faults = "non-fatal"; qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; label = "tfe"; @@ -217,9 +219,7 @@ msm_cam_smmu_ope { compatible = "qcom,msm-cam-smmu-cb"; iommus = <&apps_smmu 0x820 0x000>, - <&apps_smmu 0x821 0x020>, - <&apps_smmu 0x840 0x000>, - <&apps_smmu 0x841 0x000>; + <&apps_smmu 0x840 0x000>; qcom,iommu-faults = "non-fatal"; multiple-client-devices; qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; @@ -238,8 +238,7 @@ msm_cam_smmu_cpas_cdm { compatible = "qcom,msm-cam-smmu-cb"; - iommus = <&apps_smmu 0x800 0x000>, - <&apps_smmu 0x801 0x020>; + iommus = <&apps_smmu 0x800 0x000>; label = "cpas-cdm0"; qcom,iommu-faults = "non-fatal"; qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; @@ -283,37 +282,42 @@ "gcc_camss_top_ahb_clk", "gcc_camss_top_ahb_clk_src", "gcc_camss_axi_clk", - "gcc_camss_axi_clk_src"; + "gcc_camss_axi_clk_src", + "gcc_camss_nrt_axi_clk", + "gcc_camss_rt_axi_clk"; clocks = <&gcc GCC_CAMERA_AHB_CLK>, <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_TOP_AHB_CLK_SRC>, <&gcc GCC_CAMSS_AXI_CLK>, - <&gcc GCC_CAMSS_AXI_CLK_SRC>; + <&gcc GCC_CAMSS_AXI_CLK_SRC>, + <&gcc GCC_CAMSS_NRT_AXI_CLK>, + <&gcc GCC_CAMSS_RT_AXI_CLK>; src-clock-name = "gcc_camss_axi_clk_src"; clock-rates = - <0 0 0 0 0>, - <0 80000000 80000000 19200000 19200000>, - <0 80000000 80000000 150000000 150000000>, - <0 80000000 80000000 200000000 200000000>, - <0 80000000 80000000 300000000 300000000>, - <0 80000000 80000000 300000000 300000000>, - <0 80000000 80000000 300000000 300000000>; + <0 0 0 0 0 0 0>, + <0 0 80000000 0 19200000 0 0>, + <0 0 80000000 0 150000000 0 0>, + <0 0 80000000 0 200000000 0 0>, + <0 0 80000000 0 300000000 0 0>, + <0 0 80000000 0 300000000 0 0>, + <0 0 80000000 0 300000000 0 0>; clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; control-camnoc-axi-clk; camnoc-bus-width = <32>; camnoc-axi-clk-bw-margin-perc = <20>; - qcom,msm-bus,name = "cam_ahb"; /*Need to verify*/ - qcom,msm-bus,num-cases = <7>; /*Need to verify*/ - qcom,msm-bus,num-paths = <1>; /*Need to verify*/ - qcom,msm-bus,vectors-KBps = /*Need to verify*/ + qcom,msm-bus,name = "cam_ahb"; + qcom,msm-bus,num-cases = <7>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = , , + MSM_BUS_SLAVE_CAMERA_CFG 0 133333>, , + MSM_BUS_SLAVE_CAMERA_CFG 0 133333>, , ; traffic-transaction-type = ; + constituent-paths = + ; parent-node = <&level1_nrt0_rd_wr>; }; @@ -427,6 +435,9 @@ traffic-data = ; traffic-transaction-type = ; + constituent-paths = + ; parent-node = <&level1_nrt0_rd_wr>; }; @@ -591,23 +602,22 @@ "cphy_rx_clk_src", "tfe_cphy_rx_clk", "tfe_clk_src", - "tfe_clk", - "tfe_axi_clk"; + "tfe_clk"; clocks = <&gcc GCC_CAMSS_TFE_0_CSID_CLK_SRC>, <&gcc GCC_CAMSS_TFE_0_CSID_CLK>, <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, - <&gcc GCC_CAMSS_TFE_0_CLK>, - <&gcc GCC_CAMSS_AXI_CLK>; + <&gcc GCC_CAMSS_TFE_0_CLK>; clock-rates = - <240000000 240000000 0 240000000 256000000 256000000 150000000>, - <384000000 384000000 0 341333333 460800000 460800000 200000000>, - <426400000 426400000 0 384000000 576000000 576000000 300000000>; + <240000000 0 240000000 0 256000000 0>, + <384000000 0 341333333 0 460800000 0>, + <426400000 0 384000000 0 576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; @@ -623,19 +633,18 @@ camss-supply = <&gcc_camss_top_gdsc>; clock-names = "tfe_clk_src", - "tfe_clk", - "tfe_axi_clk"; + "tfe_clk"; clocks = <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, - <&gcc GCC_CAMSS_TFE_0_CLK>, - <&gcc GCC_CAMSS_AXI_CLK>; + <&gcc GCC_CAMSS_TFE_0_CLK>; clock-rates = - <256000000 256000000 150000000>, - <460800000 460800000 200000000>, - <576000000 576000000 300000000>; + <256000000 0>, + <460800000 0>, + <576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_clk_src"; clock-control-debugfs = "true"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; @@ -657,23 +666,22 @@ "cphy_rx_clk_src", "tfe_cphy_rx_clk", "tfe_clk_src", - "tfe_clk", - "tfe_axi_clk"; + "tfe_clk"; clocks = <&gcc GCC_CAMSS_TFE_1_CSID_CLK_SRC>, <&gcc GCC_CAMSS_TFE_1_CSID_CLK>, <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>, <&gcc GCC_CAMSS_TFE_1_CLK_SRC>, - <&gcc GCC_CAMSS_TFE_1_CLK>, - <&gcc GCC_CAMSS_AXI_CLK>; + <&gcc GCC_CAMSS_TFE_1_CLK>; clock-rates = - <240000000 240000000 0 240000000 256000000 256000000 150000000>, - <384000000 384000000 0 341333333 460800000 460800000 200000000>, - <426400000 426400000 0 384000000 576000000 576000000 300000000>; + <240000000 0 240000000 0 256000000 0>, + <384000000 0 341333333 0 460800000 0>, + <426400000 0 384000000 0 576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; @@ -689,19 +697,18 @@ camss-supply = <&gcc_camss_top_gdsc>; clock-names = "tfe_clk_src", - "tfe_clk", - "tfe_axi_clk"; + "tfe_clk"; clocks = <&gcc GCC_CAMSS_TFE_1_CLK_SRC>, - <&gcc GCC_CAMSS_TFE_1_CLK>, - <&gcc GCC_CAMSS_AXI_CLK>; + <&gcc GCC_CAMSS_TFE_1_CLK>; clock-rates = - <256000000 256000000 150000000>, - <460800000 460800000 200000000>, - <576000000 576000000 300000000>; + <256000000 0>, + <460800000 0>, + <576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_clk_src"; clock-control-debugfs = "true"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; @@ -723,23 +730,22 @@ "cphy_rx_clk_src", "tfe_cphy_rx_clk", "tfe_clk_src", - "tfe_clk", - "tfe_axi_clk"; + "tfe_clk"; clocks = <&gcc GCC_CAMSS_TFE_2_CSID_CLK_SRC>, <&gcc GCC_CAMSS_TFE_2_CSID_CLK>, <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, <&gcc GCC_CAMSS_TFE_2_CPHY_RX_CLK>, <&gcc GCC_CAMSS_TFE_2_CLK_SRC>, - <&gcc GCC_CAMSS_TFE_2_CLK>, - <&gcc GCC_CAMSS_AXI_CLK>; + <&gcc GCC_CAMSS_TFE_2_CLK>; clock-rates = - <240000000 240000000 0 240000000 256000000 256000000 150000000>, - <384000000 384000000 0 341333333 460800000 460800000 200000000>, - <426400000 426400000 0 384000000 576000000 576000000 300000000>; + <240000000 0 240000000 0 256000000 0>, + <384000000 0 341333333 0 460800000 0>, + <426400000 0 384000000 0 576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; @@ -755,19 +761,18 @@ camss-supply = <&gcc_camss_top_gdsc>; clock-names = "tfe_clk_src", - "tfe_clk", - "tfe_axi_clk"; + "tfe_clk"; clocks = <&gcc GCC_CAMSS_TFE_2_CLK_SRC>, - <&gcc GCC_CAMSS_TFE_2_CLK>, - <&gcc GCC_CAMSS_AXI_CLK>; + <&gcc GCC_CAMSS_TFE_2_CLK>; clock-rates = - <256000000 256000000 150000000>, - <460800000 460800000 200000000>, - <576000000 576000000 300000000>; + <256000000 0>, + <460800000 0>, + <576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_clk_src"; clock-control-debugfs = "true"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; @@ -782,14 +787,16 @@ camss-supply = <&gcc_camss_top_gdsc>; clock-names = "cphy_rx_clk_src", - "tfe_0_cphy_rx_clk"; + "tfe_0_cphy_rx_clk", + "gcc_camss_cphy_0_clk"; clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, - <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>; + <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_CPHY_0_CLK>; clock-rates = - <240000000 240000000>, - <341333333 341333333>, - <384000000 384000000>; + <240000000 0 0>, + <341333333 0 0>, + <384000000 0 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "cphy_rx_clk_src"; clock-control-debugfs = "false"; @@ -807,14 +814,16 @@ camss-supply = <&gcc_camss_top_gdsc>; clock-names = "cphy_rx_clk_src", - "tfe_1_cphy_rx_clk"; + "tfe_1_cphy_rx_clk", + "gcc_camss_cphy_1_clk"; clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, - <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>; + <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_CPHY_1_CLK>; clock-rates = - <240000000 240000000>, - <341333333 341333333>, - <384000000 384000000>; + <240000000 0 0>, + <341333333 0 0>, + <384000000 0 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "cphy_rx_clk_src"; clock-control-debugfs = "false"; @@ -859,12 +868,13 @@ <&gcc GCC_CAMSS_OPE_CLK_SRC>, <&gcc GCC_CAMSS_OPE_CLK>; clock-rates = - <171428571 200000000 200000000>, - <171428571 266600000 266600000>, - <240000000 465000000 465000000>, - <240000000 580000000 580000000>; + <171428571 200000000 0>, + <171428571 266600000 0>, + <240000000 465000000 0>, + <240000000 580000000 0>; clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ope_clk_src"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; }; diff --git a/bindings/msm-cam-cci.txt b/bindings/msm-cam-cci.txt index be7cc712..d353e8b0 100644 --- a/bindings/msm-cam-cci.txt +++ b/bindings/msm-cam-cci.txt @@ -19,6 +19,8 @@ First Level Node - CCI device Usage: required Value type: Definition: Should be "qcom,cci". + In case of cci version 1.2, + use "qcom,cci-v1.2". - cell-index: cci hardware core index Usage: required diff --git a/bindings/msm-cam-cpas.txt b/bindings/msm-cam-cpas.txt index c18b7439..068edb5e 100644 --- a/bindings/msm-cam-cpas.txt +++ b/bindings/msm-cam-cpas.txt @@ -128,6 +128,11 @@ First Level Node - CAM CPAS device Definition: List of strings corresponds clock-rates levels. Supported strings: minsvs, lowsvs, svs, svs_l1, nominal, turbo. +- qcom,cam-cx-ipeak + Usage: required + Value type: + Definition: Camera Cx Ipeak ID. + - control-camnoc-axi-clk Usage: optional Value type: @@ -311,6 +316,7 @@ Example: src-clock-name = "slow_ahb_clk_src"; clock-rates = <0 0 0 0 80000000 0>; clock-cntl-level = "turbo"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; control-camnoc-axi-clk; camnoc-bus-width = <32>; camnoc-axi-clk-bw-margin-perc = <10>; diff --git a/bindings/msm-cam-csiphy.txt b/bindings/msm-cam-csiphy.txt index fba46eed..cb5680aa 100644 --- a/bindings/msm-cam-csiphy.txt +++ b/bindings/msm-cam-csiphy.txt @@ -15,8 +15,8 @@ First Level Node - CSIPHY device Value type: Definition: Should be "qcom,csiphy-v1.0", "qcom,csiphy-v1.1", "qcom,csiphy-v1.2", "qcom,csiphy-v1.2.1", - "qcom,csiphy-v1.2.2", "qcom,csiphy-v1.2.3", - "qcom,csiphy-v2.0", "qcom,csiphy-v1.2.2.2", "qcom,csiphy". + "qcom,csiphy-v1.2.2", "qcom,csiphy-v2.0", "qcom,csiphy-v1.2.2.2", + "qcom,csiphy-v1.2.3", "qcom,csiphy-v2.0.1", "qcom,csiphy". - cell-index: csiphy hardware core index Usage: required diff --git a/bindings/msm-cam-tpg.txt b/bindings/msm-cam-tpg.txt index 86935237..12672cb0 100644 --- a/bindings/msm-cam-tpg.txt +++ b/bindings/msm-cam-tpg.txt @@ -17,7 +17,7 @@ Required properties: Usage: required Value type: Definition: Should specify the compatibility string for matching the - driver. e.g. "qcom,tpg101", "qcom,tpg102" + driver. e.g. "qcom,tpg101", "qcom,tpg102", "qcom,tpgv1" - cell-index Usage: required @@ -110,4 +110,4 @@ Example: src-clock-name = "cphy_rx_clk_src"; clock-control-debugfs = "false"; status = "ok"; - }; \ No newline at end of file + }; diff --git a/lagoon-camera-sensor-cdp.dtsi b/lagoon-camera-sensor-cdp.dtsi new file mode 100644 index 00000000..1bb08daa --- /dev/null +++ b/lagoon-camera-sensor-cdp.dtsi @@ -0,0 +1,421 @@ +#include + +&soc { + led_flash_triple_rear: qcom,camera-flash@4 { + cell-index = <4>; + reg = <0x04 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2>; + }; + + led_flash_triple_rear_aux: qcom,camera-flash@5 { + cell-index = <5>; + reg = <0x05 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2>; + }; + + led_flash_triple_rear_aux2: qcom,camera-flash@6 { + cell-index = <6>; + reg = <0x06 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2>; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_triple_rear: qcom,actuator@4 { + cell-index = <4>; + reg = <0x4>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + actuator_triple_rear_aux: qcom,actuator@5 { + cell-index = <5>; + reg = <0x5>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_triple_rear: qcom,eeprom@4 { + cell-index = <4>; + reg = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2904000 1104000 0 2800000>; + rgltr-max-voltage = <1800000 2904000 1104000 0 2800000>; + rgltr-load-current = <0 80000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 29 0>, + <&tlmm 34 0>, + <&tlmm 50 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4", + "CAM_VANA4"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_rear_aux: qcom,eeprom@5 { + cell-index = <5>; + reg = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-load-current = <0 2000000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 30 0>, + <&tlmm 35 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@4 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + reg = <0x4>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_triple_rear>; + actuator-src = <&actuator_triple_rear>; + eeprom-src = <&eeprom_triple_rear>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_v_custom1-supply = <&S2A>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_v_custom1"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2904000 1104000 0 2096000>; + rgltr-max-voltage = <1800000 2904000 1104000 0 2096000>; + rgltr-load-current = <0 80000 105000 0 80000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 29 0>, + <&tlmm 34 0>, + <&tlmm 50 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4", + "CAM_VANA4"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + reg = <0x5>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_triple_rear_aux>; + actuator-src = <&actuator_triple_rear_aux>; + eeprom-src = <&eeprom_triple_rear_aux>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 2000000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 30 0>, + <&tlmm 35 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; + +&cam_cci1 { + actuator_triple_rear_aux2: qcom,actuator@6 { + cell-index = <6>; + reg = <0x6>; + compatible = "qcom,actuator"; + cci-device = <1>; + cci-master = <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_front: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 32 0>, + <&tlmm 37 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-position = <1>; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_rear_aux2: qcom,eeprom@6 { + cell-index = <6>; + reg = <6>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L7P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-load-current = <0 80000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rear_aux2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rear_aux2>; + gpios = <&tlmm 31 0>, + <&tlmm 36 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 32 0>, + <&tlmm 37 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@6 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + reg = <0x06>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_triple_rear_aux2>; + actuator-src = <&actuator_triple_rear_aux2>; + eeprom-src = <&eeprom_triple_rear_aux2>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L7P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rear_aux2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rear_aux2>; + gpios = <&tlmm 31 0>, + <&tlmm 36 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK6", + "CAM_RESET6"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; diff --git a/lagoon-camera-sensor-mtp.dtsi b/lagoon-camera-sensor-mtp.dtsi new file mode 100644 index 00000000..1bb08daa --- /dev/null +++ b/lagoon-camera-sensor-mtp.dtsi @@ -0,0 +1,421 @@ +#include + +&soc { + led_flash_triple_rear: qcom,camera-flash@4 { + cell-index = <4>; + reg = <0x04 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2>; + }; + + led_flash_triple_rear_aux: qcom,camera-flash@5 { + cell-index = <5>; + reg = <0x05 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2>; + }; + + led_flash_triple_rear_aux2: qcom,camera-flash@6 { + cell-index = <6>; + reg = <0x06 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2>; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_triple_rear: qcom,actuator@4 { + cell-index = <4>; + reg = <0x4>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + actuator_triple_rear_aux: qcom,actuator@5 { + cell-index = <5>; + reg = <0x5>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_triple_rear: qcom,eeprom@4 { + cell-index = <4>; + reg = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2904000 1104000 0 2800000>; + rgltr-max-voltage = <1800000 2904000 1104000 0 2800000>; + rgltr-load-current = <0 80000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 29 0>, + <&tlmm 34 0>, + <&tlmm 50 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4", + "CAM_VANA4"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_rear_aux: qcom,eeprom@5 { + cell-index = <5>; + reg = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-load-current = <0 2000000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 30 0>, + <&tlmm 35 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@4 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + reg = <0x4>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_triple_rear>; + actuator-src = <&actuator_triple_rear>; + eeprom-src = <&eeprom_triple_rear>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_v_custom1-supply = <&S2A>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_v_custom1"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2904000 1104000 0 2096000>; + rgltr-max-voltage = <1800000 2904000 1104000 0 2096000>; + rgltr-load-current = <0 80000 105000 0 80000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 29 0>, + <&tlmm 34 0>, + <&tlmm 50 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4", + "CAM_VANA4"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + reg = <0x5>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_triple_rear_aux>; + actuator-src = <&actuator_triple_rear_aux>; + eeprom-src = <&eeprom_triple_rear_aux>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 2000000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 30 0>, + <&tlmm 35 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; + +&cam_cci1 { + actuator_triple_rear_aux2: qcom,actuator@6 { + cell-index = <6>; + reg = <0x6>; + compatible = "qcom,actuator"; + cci-device = <1>; + cci-master = <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_front: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 32 0>, + <&tlmm 37 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-position = <1>; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_rear_aux2: qcom,eeprom@6 { + cell-index = <6>; + reg = <6>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L7P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-load-current = <0 80000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rear_aux2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rear_aux2>; + gpios = <&tlmm 31 0>, + <&tlmm 36 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 32 0>, + <&tlmm 37 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@6 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + reg = <0x06>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_triple_rear_aux2>; + actuator-src = <&actuator_triple_rear_aux2>; + eeprom-src = <&eeprom_triple_rear_aux2>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L7P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rear_aux2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rear_aux2>; + gpios = <&tlmm 31 0>, + <&tlmm 36 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK6", + "CAM_RESET6"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; diff --git a/lagoon-camera.dtsi b/lagoon-camera.dtsi index 9c2a5e88..e59eb916 100644 --- a/lagoon-camera.dtsi +++ b/lagoon-camera.dtsi @@ -6,6 +6,332 @@ status = "ok"; }; + cam_csiphy0: qcom,csiphy0 { + cell-index = <0>; + compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy"; + reg = <0x0ac65000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x65000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "refgen", "mipi-csi-vdd1", + "mipi-csi-vdd2"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + refgen-supply = <&refgen>; + mipi-csi-vdd1-supply = <&L18A>; + mipi-csi-vdd2-supply = <&L22A>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0 880000 1200000>; + rgltr-max-voltage = <0 0 880000 1200000>; + rgltr-load-current = <0 0 80000 80000>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + src-clock-name = "csi0phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1"; + clock-rates = + <300000000 0 300000000 0>, + <384000000 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy1 { + cell-index = <1>; + compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy"; + reg = <0xac66000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x66000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "refgen", "mipi-csi-vdd1", + "mipi-csi-vdd2"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + refgen-supply = <&refgen>; + mipi-csi-vdd1-supply = <&L18A>; + mipi-csi-vdd2-supply = <&L22A>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0 880000 1200000>; + rgltr-max-voltage = <0 0 880000 1200000>; + rgltr-load-current = <0 0 80000 80000>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + src-clock-name = "csi1phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1"; + clock-rates = + <300000000 0 300000000 0>, + <384000000 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy2: qcom,csiphy2 { + cell-index = <2>; + compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy"; + reg = <0xac67000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x67000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "refgen", "mipi-csi-vdd1", + "mipi-csi-vdd2"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + refgen-supply = <&refgen>; + mipi-csi-vdd1-supply = <&L18A>; + mipi-csi-vdd2-supply = <&L22A>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0 880000 1200000>; + rgltr-max-voltage = <0 0 880000 1200000>; + rgltr-load-current = <0 0 80000 80000>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + src-clock-name = "csi2phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1"; + clock-rates = + <300000000 0 300000000 0>, + <384000000 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy3: qcom,csiphy3 { + cell-index = <3>; + compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy"; + reg = <0xac68000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x68000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "refgen", "mipi-csi-vdd1", + "mipi-csi-vdd2"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + refgen-supply = <&refgen>; + mipi-csi-vdd1-supply = <&L18A>; + mipi-csi-vdd2-supply = <&L22A>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0 880000 1200000>; + rgltr-max-voltage = <0 0 880000 1200000>; + rgltr-load-current = <0 0 80000 80000>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy3_clk", + "csi3phytimer_clk_src", + "csi3phytimer_clk"; + src-clock-name = "csi3phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1"; + clock-rates = + <300000000 0 300000000 0>, + <384000000 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_cci0: qcom,cci0 { + cell-index = <0>; + compatible = "qcom,cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xac4a000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x4a000>; + interrupt-names = "cci"; + interrupts = ; + status = "ok"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&camcc CAM_CC_CCI_0_CLK>, + <&camcc CAM_CC_CCI_0_CLK_SRC>; + clock-names = "cci_0_clk", + "cci_0_clk_src"; + src-clock-name = "cci_0_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <0 37500000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci0_active &cci1_active>; + pinctrl-1 = <&cci0_suspend &cci1_suspend>; + gpios = <&tlmm 39 0>, + <&tlmm 40 0>, + <&tlmm 41 0>, + <&tlmm 42 0>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 1 1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + + i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci0: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci1: qcom,cci1 { + cell-index = <1>; + compatible = "qcom,cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xac4b000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x4b000>; + interrupt-names = "cci"; + interrupts = ; + status = "ok"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&camcc CAM_CC_CCI_1_CLK>, + <&camcc CAM_CC_CCI_1_CLK_SRC>; + clock-names = "cci_clk", + "cci_1_clk_src"; + src-clock-name = "cci_1_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <0 37500000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci2_active>; + pinctrl-1 = <&cci2_suspend>; + gpios = <&tlmm 43 0>, + <&tlmm 44 0>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA2", + "CCI_I2C_CLK2"; + + i2c_freq_100Khz_cci1: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci1: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci1: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + qcom,cam_smmu { compatible = "qcom,msm-cam-smmu"; status = "ok"; @@ -207,7 +533,7 @@ reg-names = "csid"; reg = <0xacb3000 0x1000>; reg-cam-base = <0xb3000>; - interrupt-names = "csid"; + interrupt-names = "csid0"; interrupts = ; regulator-names = "camss", "ife0"; camss-supply = <&cam_cc_titan_top_gdsc>; @@ -244,7 +570,7 @@ reg-names = "ife"; reg = <0xacaf000 0x4000>; reg-cam-base = <0xaf000>; - interrupt-names = "ife"; + interrupt-names = "ife0"; interrupts = ; regulator-names = "camss", "ife0"; camss-supply = <&cam_cc_titan_top_gdsc>; @@ -276,7 +602,7 @@ reg-names = "csid"; reg = <0xacba000 0x1000>; reg-cam-base = <0xba000>; - interrupt-names = "csid"; + interrupt-names = "csid1"; interrupts = ; regulator-names = "camss", "ife1"; camss-supply = <&cam_cc_titan_top_gdsc>; @@ -313,7 +639,7 @@ reg-names = "ife"; reg = <0xacb6000 0x4000>; reg-cam-base = <0xb6000>; - interrupt-names = "ife"; + interrupt-names = "ife1"; interrupts = ; regulator-names = "camss", "ife1"; camss-supply = <&cam_cc_titan_top_gdsc>; @@ -342,11 +668,11 @@ cam_csid2: qcom,csid2@acc1000 { cell-index = <2>; compatible = "qcom,csid170_200"; - reg-names = "csid"; + reg-names = "csid2"; reg = <0xacc1000 0x1000>; reg-cam-base = <0xc1000>; interrupt-names = "csid"; - interrupts = ; + interrupts = ; regulator-names = "camss", "ife2"; camss-supply = <&cam_cc_titan_top_gdsc>; ife2-supply = <&cam_cc_ife_2_gdsc>; @@ -379,11 +705,11 @@ cam_vfe2: qcom,vfe2@acbd000 { cell-index = <2>; compatible = "qcom,vfe170_150"; - reg-names = "ife"; + reg-names = "ife2"; reg = <0xacbd000 0x4000>; reg-cam-base = <0xbd000>; interrupt-names = "ife"; - interrupts = ; + interrupts = ; regulator-names = "camss", "ife2"; camss-supply = <&cam_cc_titan_top_gdsc>; ife2-supply = <&cam_cc_ife_2_gdsc>; @@ -496,6 +822,7 @@ "soc_ahb_clk", "icp_clk", "icp_clk_src"; + src-clock-name = "icp_clk_src"; clocks = <&camcc CAM_CC_FAST_AHB_CLK_SRC>, <&camcc CAM_CC_SOC_AHB_CLK>, @@ -506,8 +833,10 @@ <100000000 0 0 384000000>, <200000000 0 0 404000000>, <300000000 0 0 600000000>, + <404000000 0 0 600000000>, <404000000 0 0 600000000>; - clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + clock-cntl-level = "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; fw_name = "CAMERA_ICP.elf"; ubwc-cfg = <0x73 0x1CF>; status = "ok"; @@ -538,7 +867,7 @@ <0 0 0 0 240000000>, <0 0 0 0 320000000>, <0 0 0 0 404000000>, - <0 0 0 0 538000000>, + <0 0 0 0 538666666>, <0 0 0 0 600000000>; clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; @@ -667,4 +996,483 @@ src-clock-name = "lrme_clk_src"; status = "ok"; }; + + qcom,cam-cpas@ac40000 { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + status = "ok"; + reg-names = "cam_cpas_top", "cam_camnoc", "core_top_csr_tcsr"; + reg = <0xac40000 0x1000>, + <0xac42000 0x4600>, + <0x01fc0000 0x40000>; + reg-cam-base = <0x40000 0x42000 0x0>; + interrupt-names = "cpas_camnoc"; + interrupts = ; + qcom,cpas-hw-ver = <0x170200>; /* Titan v170 v2.0.0 */ + camnoc-axi-min-ib-bw = <3000000000>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "gcc_ahb_clk", + "gcc_axi_clk", + "soc_ahb_clk", + "slow_ahb_clk_src", + "cpas_ahb_clk", + "camnoc_axi_clk"; + clocks = + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>; + src-clock-name = "slow_ahb_clk_src"; + clock-rates = + <0 0 0 0 0 0>, + <0 0 0 80000000 0 0>, + <0 0 0 80000000 0 0>, + <0 0 0 80000000 0 0>, + <0 0 0 80000000 0 0>, + <0 0 0 80000000 0 0>; + clock-cntl-level = "suspend", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + qcom,msm-bus,name = "cam_ahb"; + qcom,msm-bus,num-cases = <7>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + , + , + , + , + ; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", + "minsvs", "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "csiphy2", "csiphy3", "cci0", + "cci1", "csid0", "csid1", "csid2", "csid3", + "ife0", "ife1", "ife2", "ife3", "ipe0", + "cam-cdm-intf0", "cpas-cdm0", "bps0", + "icp0", "jpeg-dma0", "jpeg-enc0", "lrmecpas0"; + + camera-bus-nodes { + level3-nodes { + level-index = <3>; + level3_rt0_wr_sum: level3-rt0-wr-sum { + cell-index = <0>; + node-name = "level3-rt0-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_hf_0"; + ib-bw-voting-needed; + qcom,axi-port-mnoc { + qcom,msm-bus,name = + "cam_hf_0_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + + qcom,axi-port-camnoc { + qcom,msm-bus,name = + "cam_hf_0_camnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + + level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum { + cell-index = <1>; + node-name = "level3-nrt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_sf_0"; + qcom,axi-port-mnoc { + qcom,msm-bus,name = + "cam_sf_0_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + + qcom,axi-port-camnoc { + qcom,msm-bus,name = + "cam_sf_0_camnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + + level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum { + cell-index = <2>; + node-name = "level3-nrt1-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_sf_icp"; + qcom,axi-port-mnoc { + qcom,msm-bus,name = + "cam_sf_icp_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + + qcom,axi-port-camnoc { + qcom,msm-bus,name = + "cam_sf_icp_camnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + }; + + level2-nodes { + level-index = <2>; + level2_rt0_wr: level2-rt0-wr { + cell-index = <3>; + node-name = "level2-rt0-wr"; + parent-node = <&level3_rt0_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt0_rd_wr: level2-nrt0-rd-wr { + cell-index = <4>; + node-name = "level2-nrt0-rd-wr"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt1_rd: level2-nrt1-rd { + cell-index = <5>; + node-name = "level2-nrt1-rd"; + parent-node = <&level3_nrt1_rd_wr_sum>; + traffic-merge-type = + ; + bus-width-factor = <4>; + }; + }; + + level1-nodes { + level-index = <1>; + level1_rt0_wr: level1-rt0-wr { + cell-index = <6>; + node-name = "level1-rt0-wr"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt1_wr: level1-rt1-wr { + cell-index = <7>; + node-name = "level1-rt1-wr"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_nrt0_wr: level1-nrt0-wr { + cell-index = <8>; + node-name = "level1-nrt0-wr"; + parent-node = <&level2_nrt0_rd_wr>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd: level1-nrt0-rd { + cell-index = <9>; + node-name = "level1-nrt0-rd"; + parent-node = <&level2_nrt0_rd_wr>; + traffic-merge-type = + ; + }; + }; + + level0-nodes { + level-index = <0>; + + ife0_rdi_all_wr: ife0-rdi-all-wr { + cell-index = <10>; + node-name = "ife0-rdi-all-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr>; + }; + + ife1_rdi_all_wr: ife1-rdi-all-wr { + cell-index = <11>; + node-name = "ife1-rdi-all-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr>; + }; + + ife2_rdi_all_wr: ife2-rdi-all-wr { + cell-index = <12>; + node-name = "ife2-rdi-all-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt1_wr>; + }; + + ife3_rdi_all_wr: ife3-rdi-all-wr { + cell-index = <13>; + node-name = "ife3-rdi-all-wr"; + client-name = "ife3"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt1_wr>; + }; + + ife0_pixelall_wr: ife0-pixelall-wr { + cell-index = <14>; + node-name = "ife0-pixelall-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr>; + }; + + ife1_pixelall_wr: ife1-pixelall-wr { + cell-index = <15>; + node-name = "ife1-pixelall-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr>; + }; + + ife2_pixelall_wr: ife2-pixelall-wr { + cell-index = <16>; + node-name = "ife2-pixelall-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt1_wr>; + }; + + bps0_all_wr: bps0-all-wr { + cell-index = <17>; + node-name = "bps0-all-wr"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_wr>; + }; + + bps0_all_rd: bps0-all-rd { + cell-index = <18>; + node-name = "bps0-all-rd"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd>; + }; + + ipe0_all_rd: ipe0-all-rd { + cell-index = <19>; + node-name = "ipe0-all-rd"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt0_rd>; + }; + + ipe0_all_wr: ipe0-all-wr { + cell-index = <20>; + node-name = "ipe0-all-wr"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt0_wr>; + }; + + lrme0_all_rd: lrme0-all-rd { + cell-index = <21>; + node-name = "lrme0-all-rd"; + client-name = "lrmecpas0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd>; + }; + + lrme0_all_wr: lrme0-all-wr { + cell-index = <22>; + node-name = "lrme0-all-wr"; + client-name = "lrmecpas0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_wr>; + }; + + cpas_cdm0_all_rd: cpas-cdm0-all-rd { + cell-index = <23>; + node-name = "cpas-cdm0-all-rd"; + client-name = "cpas-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd_wr>; + }; + + jpeg0_all_wr: jpeg0-all-wr { + cell-index = <24>; + node-name = "jpeg0-all-wr"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd_wr>; + }; + + jpeg0_all_rd: jpeg0-all-rd { + cell-index = <25>; + node-name = "jpeg0-all-rd"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd_wr>; + }; + + icp0_all_rd: icp0-all-rd { + cell-index = <26>; + node-name = "icp0-all-rd"; + client-name = "icp0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt1_rd>; + }; + }; + }; + }; }; diff --git a/scuba-camera-sensor-idp.dtsi b/scuba-camera-sensor-idp.dtsi new file mode 100644 index 00000000..6c7655b2 --- /dev/null +++ b/scuba-camera-sensor-idp.dtsi @@ -0,0 +1,313 @@ +#include +&soc { + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + compatible = "qcom,camera-flash"; + flash-source = <&pm2250_flash0>; + torch-source = <&pm2250_torch0>; + switch-source = <&pm2250_switch0>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash@1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm2250_flash0>; + torch-source = <&pm2250_torch0>; + switch-source = <&pm2250_switch0>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_rear: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + actuator_rear_aux: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_rear: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_vaf-supply = <&L5P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1050000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1050000 0 2800000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear0_reset_suspend>; + gpios = <&tlmm 20 0>, + <&tlmm 18 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_aux: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_vaf-supply = <&L5P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1200000 0 2800000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear1_reset_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear1_reset_suspend>; + gpios = <&tlmm 21 0>, + <&tlmm 19 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_front: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L6P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front0_reset_suspend>; + gpios = <&tlmm 27 0>, + <&tlmm 24 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + /* Rear*/ + qcom,cam-sensor0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear>; + led-flash-src = <&led_flash_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1050000 0>; + rgltr-max-voltage = <1800000 2800000 1050000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear0_reset_suspend>; + gpios = <&tlmm 20 0>, + <&tlmm 18 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /*Rear Aux*/ + qcom,cam-sensor1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear_aux>; + led-flash-src = <&led_flash_rear_aux>; + eeprom-src = <&eeprom_rear_aux>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear1_reset_active + &cam_sensor_csi_mux_oe_active + &cam_sensor_csi_mux_sel_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear1_reset_suspend + &cam_sensor_csi_mux_oe_suspend + &cam_sensor_csi_mux_sel_suspend>; + gpios = <&tlmm 21 0>, + <&tlmm 19 0>, + <&tlmm 113 0>, + <&tlmm 114 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-custom2 = <3>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1", + "CAM_CSIMUX_OE0", + "CAM_CSIMUX_SEL0"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /*Front*/ + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L6P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front0_reset_active + &cam_sensor_csi_mux_oe_active + &cam_sensor_csi_mux_sel_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front0_reset_suspend + &cam_sensor_csi_mux_oe_suspend + &cam_sensor_csi_mux_sel_suspend>; + gpios = <&tlmm 27 0>, + <&tlmm 24 0>, + <&tlmm 113 0>, + <&tlmm 114 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-custom2 = <3>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_CSIMUX_OE0", + "CAM_CSIMUX_SEL0"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; diff --git a/scuba-camera.dtsi b/scuba-camera.dtsi new file mode 100644 index 00000000..68a4f911 --- /dev/null +++ b/scuba-camera.dtsi @@ -0,0 +1,766 @@ +#include + +&soc { + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + cam_csiphy0: qcom,csiphy0 { + cell-index = <0>; + compatible = "qcom,csiphy-v2.0", "qcom,csiphy"; + reg = <0x05C52000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x52000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr"; + gdscr-supply = <&gcc_camss_top_gdsc>; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&L5A>; + clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_CPHY_0_CLK>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK_SRC>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + src-clock-name = "csi0phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + clock-rates = + <19200000 0 19200000 0>, + <341330000 0 200000000 0>, + <341330000 0 200000000 0>, + <384000000 0 268800000 0>; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy1 { + cell-index = <1>; + compatible = "qcom,csiphy-v2.0", "qcom,csiphy"; + reg = <0x05C53000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x53000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr"; + gdscr-supply = <&gcc_camss_top_gdsc>; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&L5A>; + clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_CPHY_1_CLK>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK_SRC>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + src-clock-name = "csi1phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + clock-rates = + <19200000 0 19200000 0>, + <341330000 0 200000000 0>, + <341330000 0 200000000 0>, + <384000000 0 268800000 0>; + status = "ok"; + }; + + cam_cci0: qcom,cci0 { + cell-index = <0>; + compatible = "qcom,cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x05C1B000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x1B000>; + interrupt-names = "cci"; + interrupts = ; + status = "ok"; + gdscr-supply = <&gcc_camss_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&gcc GCC_CAMSS_CCI_0_CLK>, + <&gcc GCC_CAMSS_CCI_CLK_SRC>; + clock-names = "cci_0_clk", + "cci_0_clk_src"; + src-clock-name = "cci_0_clk_src"; + clock-cntl-level = "svs"; + clock-rates = <0 37500000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci0_active &cci1_active>; + pinctrl-1 = <&cci0_suspend &cci1_suspend>; + gpios = <&tlmm 22 0>, + <&tlmm 23 0>, + <&tlmm 29 0>, + <&tlmm 30 0>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 1 1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + + i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci0: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu"; + status = "ok"; + + msm_cam_smmu_tfe { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x400 0x000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + label = "tfe"; + tfe_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_ope { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x820 0x000>, + <&apps_smmu 0x840 0x000>; + qcom,iommu-faults = "non-fatal"; + multiple-client-devices; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + label = "ope", "ope-cdm0"; + ope_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cpas_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x800 0x000>; + label = "cpas-cdm0"; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + cpas_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 3.4 GB */ + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + label = "cam-secure"; + qcom,secure-cb; + }; + + }; + + qcom,cam-cpas@5c11000 { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + status = "ok"; + reg-names = "cam_cpas_top", "cam_camnoc"; + reg = <0x5c11000 0x1000>, + <0x5c13000 0x4000>; + reg-cam-base = <0x11000 0x13000>; + interrupt-names = "cpas_camnoc"; + interrupts = ; + camnoc-axi-min-ib-bw = <3000000000>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&gcc_camss_top_gdsc>; + clock-names = + "gcc_camss_ahb_clk", + "gcc_camss_top_ahb_clk", + "gcc_camss_top_ahb_clk_src", + "gcc_camss_axi_clk", + "gcc_camss_axi_clk_src", + "gcc_camss_nrt_axi_clk", + "gcc_camss_rt_axi_clk"; + clocks = + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK_SRC>, + <&gcc GCC_CAMSS_AXI_CLK>, + <&gcc GCC_CAMSS_AXI_CLK_SRC>, + <&gcc GCC_CAMSS_NRT_AXI_CLK>, + <&gcc GCC_CAMSS_RT_AXI_CLK>; + src-clock-name = "gcc_camss_axi_clk_src"; + clock-rates = + <0 0 0 0 0 0 0>, + <0 0 80000000 0 19200000 0 0>, + <0 0 80000000 0 150000000 0 0>, + <0 0 80000000 0 200000000 0 0>, + <0 0 80000000 0 300000000 0 0>, + <0 0 80000000 0 300000000 0 0>, + <0 0 80000000 0 300000000 0 0>; + clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + qcom,cx-ipeak-gpu-limit = <921600000>; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + qcom,msm-bus,name = "cam_ahb"; + qcom,msm-bus,num-cases = <7>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + , + , + , + , + ; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "lowsvs", "lowsvs", + "lowsvs", "lowsvs", "svs", "svs_l1", "svs_l1", + "svs_l1", "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "cci0", + "csid0", "csid1", "tfe0", + "tfe1", "ope0", "cam-cdm-intf0", + "cpas-cdm0", "ope-cdm0", "tpg0", "tpg1"; + + camera-bus-nodes { + level2-nodes { + level-index = <2>; + level2_rt0_rd_wr_sum: level2-rt0-rd-wr-sum { + cell-index = <0>; + node-name = "level2-rt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_hf_0"; + ib-bw-voting-needed; + qcom,axi-port-mnoc { + qcom,msm-bus,name = + "cam_hf_0_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + + level2_nrt0_rd_wr_sum: level2-nrt0-rd-wr-sum { + cell-index = <1>; + node-name = "level2-nrt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_sf_0"; + qcom,axi-port-mnoc { + qcom,msm-bus,name = + "cam_sf_0_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + level1_rt0_wr: level1-rt0-wr { + cell-index = <2>; + node-name = "level1-rt0-wr"; + parent-node = <&level2_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd_wr: level1-nrt0-rd-wr { + cell-index = <3>; + node-name = "level1-nrt0-rd-wr"; + parent-node = <&level2_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + }; + + level0-nodes { + level-index = <0>; + ope0_all_wr: ope0-all-wr { + cell-index = <4>; + node-name = "ope0-all-wr"; + client-name = "ope0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt0_rd_wr>; + }; + + ope0_all_rd: ope0-all-rd { + cell-index = <5>; + node-name = "ope0-all-rd"; + client-name = "ope0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt0_rd_wr>; + }; + + tfe0_all_wr: tfe0-all-wr { + cell-index = <6>; + node-name = "tfe0-all-wr"; + client-name = "tfe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr>; + }; + + tfe1_all_wr: tfe1-all-wr { + cell-index = <7>; + node-name = "tfe1-all-wr"; + client-name = "tfe1"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr>; + }; + + cpas_cdm0_all_rd: cpas-cdm0-all-rd { + cell-index = <9>; + node-name = "cpas-cdm0-all-rd"; + client-name = "cpas-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd_wr>; + }; + + ope_cdm0_all_rd: ope-cdm0-all-rd { + cell-index = <10>; + node-name = "ope-cdm0-all-rd"; + client-name = "ope-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd_wr>; + }; + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <2>; + cdm-client-names = "vfe"; + status = "ok"; + }; + + cam_cpas_cdm: qcom,cpas-cdm0@5c23000 { + cell-index = <0>; + compatible = "qcom,cam-cpas-cdm2_0"; + label = "cpas-cdm"; + reg = <0x5c23000 0x400>; + reg-names = "cpas-cdm0"; + reg-cam-base = <0x23000>; + interrupts = ; + interrupt-names = "cpas-cdm0"; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = "cam_cc_cpas_top_ahb_clk"; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "svs"; + cdm-client-names = "tfe0", "tfe1"; + config-fifo; + fifo-depths = <64 64 64 64>; + status = "ok"; + }; + + cam_ope_cdm: qcom,ope-cdm0@5c42000 { + cell-index = <0>; + compatible = "qcom,cam-ope-cdm2_0"; + label = "ope-cdm"; + reg = <0x5c42000 0x400>; + reg-names = "ope-cdm0"; + reg-cam-base = <0x42000>; + interrupts = ; + interrupt-names = "ope-cdm0"; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "ope_ahb_clk", + "ope_clk_src", + "ope_clk"; + clocks = + <&gcc GCC_CAMSS_OPE_AHB_CLK>, + <&gcc GCC_CAMSS_OPE_CLK_SRC>, + <&gcc GCC_CAMSS_OPE_CLK>; + clock-rates = <0 0 0>, + <0 0 0>, + <0 0 0>, + <0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + cdm-client-names = "ope"; + config-fifo; + fifo-depths = <64 64 64 64>; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "tfe"; + status = "ok"; + }; + + cam_tfe_csid0: qcom,tfe_csid0@5c6e000 { + cell-index = <0>; + compatible = "qcom,csid530"; + reg-names = "csid", "top", "camnoc"; + reg = <0x5c6e000 0x1000>, + <0x5c11000 0x1000>, + <0x5c13000 0x4000>; + reg-cam-base = <0x6e000 0x11000 0x13000>; + interrupt-names = "csid0"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_csid_clk_src", + "tfe_csid_clk", + "cphy_rx_clk_src", + "tfe_cphy_rx_clk", + "tfe_clk_src", + "tfe_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_0_CSID_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CSID_CLK>, + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CLK>; + clock-rates = + <240000000 0 240000000 0 256000000 0>, + <384000000 0 341333333 0 460800000 0>, + <426400000 0 384000000 0 576000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_tfe0: qcom,tfe0@5c6e000 { + cell-index = <0>; + compatible = "qcom,tfe530"; + reg-names = "tfe0"; + reg = <0x5c6e000 0x5000>; + reg-cam-base = <0x6e000>; + interrupt-names = "tfe0"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_clk_src", + "tfe_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CLK>; + clock-rates = + <256000000 0>, + <460800000 0>, + <576000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_tfe_csid1: qcom,tfe_csid1@5c75000 { + cell-index = <1>; + compatible = "qcom,csid530"; + reg-names = "csid", "top", "camnoc"; + reg = <0x5c75000 0x1000>, + <0x5c11000 0x1000>, + <0x5c13000 0x4000>; + reg-cam-base = <0x75000 0x11000 0x13000>; + interrupt-names = "csid1"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_csid_clk_src", + "tfe_csid_clk", + "cphy_rx_clk_src", + "tfe_cphy_rx_clk", + "tfe_clk_src", + "tfe_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_1_CSID_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CSID_CLK>, + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_TFE_1_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CLK>; + clock-rates = + <240000000 0 240000000 0 256000000 0>, + <384000000 0 341333333 0 460800000 0>, + <426400000 0 384000000 0 576000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_tfe1: qcom,tfe1@5c75000 { + cell-index = <1>; + compatible = "qcom,tfe530"; + reg-names = "tfe1"; + reg = <0x5c75000 0x5000>; + reg-cam-base = <0x75000>; + interrupt-names = "tfe1"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_clk_src", + "tfe_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_1_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CLK>; + clock-rates = + <256000000 0>, + <460800000 0>, + <576000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_tfe_tpg0: qcom,tpg0@5c66000 { + cell-index = <0>; + compatible = "qcom,tpgv1"; + reg-names = "tpg0", "top"; + reg = <0x5c66000 0x400>, + <0x5c11000 0x1000>; + reg-cam-base = <0x66000 0x11000>; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "cphy_rx_clk_src", + "tfe_0_cphy_rx_clk", + "gcc_camss_cphy_0_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_CPHY_0_CLK>; + clock-rates = + <240000000 0 0>, + <341333333 0 0>, + <384000000 0 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "cphy_rx_clk_src"; + clock-control-debugfs = "false"; + status = "ok"; + }; + + cam_tfe_tpg1: qcom,tpg0@5c68000 { + cell-index = <1>; + compatible = "qcom,tpgv1"; + reg-names = "tpg0", "top"; + reg = <0x5c68000 0x400>, + <0x5c11000 0x1000>; + reg-cam-base = <0x68000 0x11000>; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "cphy_rx_clk_src", + "tfe_1_cphy_rx_clk", + "gcc_camss_cphy_1_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_CPHY_1_CLK>; + clock-rates = + <240000000 0 0>, + <341333333 0 0>, + <384000000 0 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "cphy_rx_clk_src"; + clock-control-debugfs = "false"; + status = "ok"; + }; + + qcom,cam-ope { + compatible = "qcom,cam-ope"; + compat-hw-name = "qcom,ope"; + num-ope = <1>; + status = "ok"; + }; + + ope: qcom,ope@0x5c42000 { + cell-index = <0>; + compatible = "qcom,ope"; + reg = + <0x5c42000 0x400>, + <0x5c42400 0x200>, + <0x5c42600 0x200>, + <0x5c42800 0x4400>, + <0x5c46c00 0x190>, + <0x5c46d90 0xA00>; + reg-names = + "ope_cdm", + "ope_top", + "ope_qos", + "ope_pp", + "ope_bus_rd", + "ope_bus_wr"; + reg-cam-base = <0x42000 0x42400 0x42600 0x42800 0x46c00 0x46d90>; + interrupts = ; + interrupt-names = "ope"; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "ope_ahb_clk_src", + "ope_ahb_clk", + "ope_clk_src", + "ope_clk"; + clocks = + <&gcc GCC_CAMSS_OPE_AHB_CLK_SRC>, + <&gcc GCC_CAMSS_OPE_AHB_CLK>, + <&gcc GCC_CAMSS_OPE_CLK_SRC>, + <&gcc GCC_CAMSS_OPE_CLK>; + clock-rates = + <171428571 0 200000000 0>, + <171428571 0 266600000 0>, + <240000000 0 465000000 0>, + <240000000 0 580000000 0>; + clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; + src-clock-name = "ope_clk_src"; + status = "ok"; + }; +};