diff --git a/bindings/input/touchscreen/parade_pt.txt b/bindings/input/touchscreen/parade_pt.txt new file mode 100644 index 00000000..3a357980 --- /dev/null +++ b/bindings/input/touchscreen/parade_pt.txt @@ -0,0 +1,34 @@ +* Parade pt touch controller + +Please add this description here: The Parade Touch controller is connected to the +host processor via I2C. The controller generates interrupts when the user touches +the panel. The host controller is expected to read the touch coordinates over I2C and +pass the coordinates to the rest of the system. + +Required properties: + - compatible : should be "parade,pt_i2c_adapter" + - reg : i2c slave address of the device. + - vdd-supply : digital voltage power supply needed to power device. + - avdd-supply : analog voltage power supply needed to power device. + - novatek,reset-gpio : reset gpio. + - novatek,irq-gpio : irq gpio. + +Example: + &i2c_1 { + status = "ok"; + + /* Parade device tree node */ + tsc@24 { + compatible = "parade,pt_i2c_adapter"; + reg = <0x24>; + status = "ok"; + + vdd-supply = <&L29A>; + vcc_i2c-supply = <&L21A>; + + parade,core { + parade,rst_gpio = <&tlmm 71 0x00>; + parade,irq_gpio = <&tlmm 80 0x2008>; + }; + }; + }; diff --git a/bindings/interconnect/qcom,sdxbaagha.txt b/bindings/interconnect/qcom,sdxbaagha.txt new file mode 100644 index 00000000..2143431c --- /dev/null +++ b/bindings/interconnect/qcom,sdxbaagha.txt @@ -0,0 +1,26 @@ +Qualcomm Technologies, Inc. SDXBAAGHA Network-On-Chip interconnect driver binding +----------------------------------------------------------- + +SDXBAAGHA interconnect providers support system bandwidth requirements through +RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is +able to communicate with the BCM through the Resource State Coordinator (RSC) +associated with each execution environment. Provider nodes must point to at +least one RPMh device child node pertaining to their RSC and each provider +can map to multiple RPMh resources. + +Required properties : +- compatible : shall contain only one of the following: + "qcom,sdxbaagha-aggre_noc", + "qcom,sdxbaagha-cnoc_main", + "qcom,sdxbaagha-dc_noc_dch", + "qcom,sdxbaagha-mc_virt", + "qcom,sdxbaagha-mem_noc", + "qcom,sdxbaagha-snoc", +- #interconnect-cells : should contain 1 + +Examples: + +snoc: interconnect@15C0000 { + compatible = "qcom,sdxbaagha-snoc"; + #interconnect-cells = <1>; +}; diff --git a/bindings/soc/qcom/qcom,crm.yaml b/bindings/soc/qcom/qcom,crm.yaml new file mode 100644 index 00000000..57faa0a7 --- /dev/null +++ b/bindings/soc/qcom/qcom,crm.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom-crm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. (QTI) CRM bindings + +maintainers: + - Maulik Shah + +description: + Support for communication with the hardened-CRM blocks. A set of HW and + SW client DRVs in CRM provides interface to vote desired power state of + resources local to a subsystem. + +properties: + label: + $ref: /schemas/types.yaml#/definitions/string-array + maxItems: 1 + oneOf: + - items: + - const: cam_crm + - const: pcie_crm + - description: Specifies the name of the CRM. + + compatible: + enum: + - qcom,cam-crm + - qcom,pcie-crm + + reg: + maxItems: 1 + items: + - description: Should specify the base address for the CRM device. + + reg-names: + maxItems: 1 + items: + - const: base + + interrupts: + maxItems: 1 + items: + - description: SW drv vote completion IRQ. + + interrupt-names: + maxItems: 1 + oneOf: + - items: + - const: cam_crm + - const: pcie_crm + + qcom,hw-drv-ids: + description: List of HW DRV IDs. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 3 + items: + minimum: 0 + maximum: 2 + + qcom,sw-drv-ids: + description: List of SW DRV IDs. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 2 + items: + minimum: 0 + maximum: 1 + + clocks: + maxItems: 1 + items: + - description: Bus Clock + +required: + - label + - compatible + - reg + - reg-names + - clocks + +oneOf: + - required: + - qcom,hw-drv-ids + - required: + - qcom,sw-drv-ids + +if: + required: + - qcom,sw-drv-ids +then: + required: + - interrupts + - interrupt-names + +additionalProperties: false + +examples: + # Example of Camera CRM device with HW DRVs + - | + #include + #include + cam_crm: crm@add7000 { + label = "cam_crm"; + compatible = "qcom,cam-crm"; + reg = <0xadd7000 0x2000>; + clocks = <&camcc CAM_CC_DRV_AHB_CLK>; + qcom,hw-drv-ids = <0 1 2>; + }; + # Example of PCIe CRM device with SW DRVs + - | + #include + pcie_crm: crm@1d01000 { + label = "pcie_crm"; + compatible = "qcom,pcie-crm"; + reg = <0x1d01000 0x3000>; + interrupts = ; + interrupt-names = "pcie_crm"; + clocks = <&pcie_0_pipe_clk>; + qcom,sw-drv-ids = <0>; + }; +... diff --git a/qcom/Makefile b/qcom/Makefile index 7883573d..d231a7d4 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -126,8 +126,15 @@ MONACO_BASE_DTB += monaco.dtb monacop.dtb MONACO_BOARDS += \ monaco-idp-v1-overlay.dtbo \ + monaco-standalone-idp-v1-overlay.dtbo \ monaco-idp-v2-overlay.dtbo \ - monaco-idp-v3-overlay.dtbo + monaco-standalone-idp-v2-overlay.dtbo \ + monaco-idp-v3-overlay.dtbo \ + monaco-standalone-idp-v3-overlay.dtbo \ + monaco-wdp-v1-overlay.dtbo \ + monaco-standalone-wdp-v1-overlay.dtbo \ + monaco-atp-v1-overlay.dtbo \ + monaco-standalone-atp-v1-overlay.dtbo monaco-dtb-$(CONFIG_ARCH_MONACO) += \ $(call add-overlays, $(MONACO_BOARDS) ,$(MONACO_BASE_DTB)) @@ -228,15 +235,25 @@ SA8155_LA_GVM_BASE_DTB += sa8155-vm-la.dtb SA8155_LA_GVM_BOARDS += \ sa8155-vm-la-overlay.dtbo -autogvm-dtb-$(CONFIG_QTI_QUIN_GVM) += \ - $(call add-overlays, $(SA8155_LA_GVM_BOARDS),$(SA8155_LA_GVM_BASE_DTB)) -autogvm-overlays-dtb-$(CONFIG_QTI_QUIN_GVM) += $(SA8155_LA_GVM_BOARDS) $(SA8155_LA_GVM_BASE_DTB) +DIREWOLF_LV_GVM_BASE_DTB += direwolf-vm-lv.dtb +DIREWOLF_LV_GVM_BOARDS += \ + direwolf-vm-lv-overlay.dtbo + +autogvm-dtb-$(CONFIG_QTI_QUIN_GVM) += \ + $(call add-overlays, $(SA8155_LA_GVM_BOARDS),$(SA8155_LA_GVM_BASE_DTB)) \ + $(call add-overlays, $(DIREWOLF_LV_GVM_BOARDS),$(DIREWOLF_LV_GVM_BASE_DTB)) +autogvm-overlays-dtb-$(CONFIG_QTI_QUIN_GVM) += \ + $(SA8155_LA_GVM_BOARDS) $(DIREWOLF_LV_GVM_BOARDS) $(SA8155_LA_GVM_BASE_DTB) $(DIREWOLF_LV_GVM_BASE_DTB) dtb-y += $(autogvm-dtb-y) +SCUBA_AUTO_BASE_DTB += scuba_auto.dtb +SCUBA_AUTO_BOARDS += \ + scuba_auto-idp-overlay.dtbo \ + scuba_auto-qrd-overlay.dtbo scuba_auto-dtb-$(CONFIG_ARCH_SCUBA_AUTO) += \ - scuba_auto-idp.dtb \ - scuba_auto-qrd.dtb + $(call add-overlays, $(SCUBA_AUTO_BOARDS) ,$(SCUBA_AUTO_BASE_DTB)) +scuba_auto-overlays-dtb-$(CONFIG_ARCH_SCUBA_AUTO) += $(SCUBA_AUTO_BOARDS) $(SCUBA_AUTO_BASE_DTB) dtb-y += $(scuba_auto-dtb-y) endif diff --git a/qcom/bengal-thermal.dtsi b/qcom/bengal-thermal.dtsi index a3eda4d8..913eb910 100644 --- a/qcom/bengal-thermal.dtsi +++ b/qcom/bengal-thermal.dtsi @@ -823,7 +823,7 @@ xo-therm { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&pm6125_adc_tm ADC5_XO_THERM_100K_PU>; + thermal-sensors = <&pm6125_adc_tm 2>; trips { active-config0 { temperature = <125000>; @@ -842,7 +842,7 @@ pa-therm0 { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&pm6125_adc_tm ADC5_AMUX_THM1_100K_PU>; + thermal-sensors = <&pm6125_adc_tm 0>; trips { active-config0 { temperature = <125000>; @@ -855,140 +855,20 @@ quiet-therm { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&pm6125_adc_tm ADC5_AMUX_THM2_100K_PU>; - status = "disabled"; + thermal-sensors = <&pm6125_adc_tm 1>; trips { active-config0 { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; - - skin_batt_trip0: batt-trip0 { - temperature = <39000>; - hysteresis = <2000>; - type = "passive"; - }; - - skin_modem_trip0: modem-trip0 { - temperature = <40000>; - hysteresis = <4000>; - type = "passive"; - }; - - skin_gold_trip: gold-trip { - temperature = <40000>; - hysteresis = <0>; - type = "passive"; - }; - - skin_batt_trip1: batt-trip1 { - temperature = <41000>; - hysteresis = <2000>; - type = "passive"; - }; - - skin_silver_trip: silver-trip { - temperature = <41000>; - hysteresis = <0>; - type = "passive"; - }; - - skin_modem_trip1: modem-trip1 { - temperature = <42000>; - hysteresis = <4000>; - type = "passive"; - }; - - skin_modem_trip2: modem-trip2 { - temperature = <43000>; - hysteresis = <4000>; - type = "passive"; - }; - - skin_batt_trip2: batt-trip2 { - temperature = <43000>; - hysteresis = <2000>; - type = "passive"; - }; - - skin_gpu_trip: gpu-trip { - temperature = <43000>; - hysteresis = <0>; - type = "passive"; - }; - - skin_batt_trip3: batt-trip3 { - temperature = <45000>; - hysteresis = <2000>; - type = "passive"; - }; - - skin_modem_trip3: modem-trip3 { - temperature = <50000>; - hysteresis = <5000>; - type = "passive"; - }; - - skin_hvx_trip: hvx-trip { - temperature = <52000>; - hysteresis = <4000>; - type = "passive"; - }; - }; - - cooling-maps { - gold_cdev { - trip = <&skin_gold_trip>; - cooling-device = <&CPU4 0 3>; - }; - - silver_cdev { - trip = <&skin_silver_trip>; - cooling-device = <&CPU0 0 2>; - }; - - gpu_cdev { - trip = <&skin_gpu_trip>; - cooling-device = <&msm_gpu 0 3>; - }; - - hvx_cdev { - trip = <&skin_hvx_trip>; - cooling-device = <&cdsp_sw 4 4>; - }; - - mdm_cdev0 { - trip = <&skin_modem_trip0>; - cooling-device = <&modem_proc 1 1>; - }; - - mdm_cdev1 { - trip = <&skin_modem_trip1>; - cooling-device = <&modem_pa 1 1>; - }; - - mdm_cdev2 { - trip = <&skin_modem_trip2>; - cooling-device = <&modem_pa 2 2>; - }; - - mdm_cdev3 { - trip = <&skin_modem_trip3>; - cooling-device = <&modem_pa 3 3>; - }; - - mdm_cdev4 { - trip = <&skin_modem_trip3>; - cooling-device = <&modem_proc 3 3>; - }; }; }; camera-therm { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&pm6125_adc_tm_iio ADC5_GPIO1_100K_PU>; + thermal-sensors = <&pm6125_adc_tm_iio 0>; trips { active-config0 { temperature = <125000>; @@ -1001,7 +881,7 @@ emmc-ufs-therm { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&pm6125_adc_tm_iio ADC5_GPIO2_100K_PU>; + thermal-sensors = <&pm6125_adc_tm_iio 1>; trips { active-config0 { temperature = <125000>; diff --git a/qcom/cinder-ru-idp.dts b/qcom/cinder-ru-idp.dts index 6afc61c3..a7cefc73 100644 --- a/qcom/cinder-ru-idp.dts +++ b/qcom/cinder-ru-idp.dts @@ -6,5 +6,5 @@ / { model = "Qualcomm Technologies, Inc. Cinder RU IDP"; compatible = "qcom,cinder-idp", "qcom,cinder", "qcom,idp"; - qcom,board-id = <0x22 0x0>; + qcom,board-id = <0x22 0x600>; }; diff --git a/qcom/cinder-usb.dtsi b/qcom/cinder-usb.dtsi index 2a445056..6a05c105 100644 --- a/qcom/cinder-usb.dtsi +++ b/qcom/cinder-usb.dtsi @@ -1,5 +1,5 @@ #include -#include +#include &soc { usb0: ssusb@a600000 { diff --git a/qcom/cinder.dtsi b/qcom/cinder.dtsi index 2e892eea..fdc5b368 100644 --- a/qcom/cinder.dtsi +++ b/qcom/cinder.dtsi @@ -1546,6 +1546,9 @@ interrupts = ; clock-names = "sm_bus_xo_clk", "sm_bus_ahb_clk"; clocks = <&gcc GCC_SM_BUS_XO_CLK>, <&gcc GCC_SM_BUS_AHB_CLK>; + interconnect-names = "i2c-slave-config"; + interconnects = + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_SMBUS_CFG>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_slave_sda_active>, <&i2c_slave_scl_active>; pinctrl-1 = <&i2c_slave_sleep>; diff --git a/qcom/direwolf-vm-lv-overlay.dts b/qcom/direwolf-vm-lv-overlay.dts new file mode 100644 index 00000000..db42d935 --- /dev/null +++ b/qcom/direwolf-vm-lv-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "direwolf-vm.dtsi" +#include "direwolf-vm-lv.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Direwolf Single LV Virtual Machine"; + compatible = "qcom,direwolf", "qcom,quinvm"; + qcom,board-id = <0 0x1000002>; +}; diff --git a/qcom/direwolf-vm-lv.dts b/qcom/direwolf-vm-lv.dts new file mode 100644 index 00000000..6758100c --- /dev/null +++ b/qcom/direwolf-vm-lv.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "direwolf-vm.dtsi" +#include "direwolf-vm-lv.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Direwolf Single LV Virtual Machine"; + compatible = "qcom,direwolf", "qcom,quinvm"; + qcom,board-id = <0 0x1000002>; +}; diff --git a/qcom/direwolf-vm-lv.dtsi b/qcom/direwolf-vm-lv.dtsi new file mode 100644 index 00000000..17f1e228 --- /dev/null +++ b/qcom/direwolf-vm-lv.dtsi @@ -0,0 +1,2 @@ +&soc { +}; diff --git a/qcom/direwolf-vm.dtsi b/qcom/direwolf-vm.dtsi new file mode 100644 index 00000000..285fb72f --- /dev/null +++ b/qcom/direwolf-vm.dtsi @@ -0,0 +1,7 @@ +#include "quin-vm-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Direwolf Virtual Machine"; + qcom,msm-name = "SA_DIREWOLF_IVI"; + qcom,msm-id = <460 0x10000>; +}; diff --git a/qcom/kalama-thermal.dtsi b/qcom/kalama-thermal.dtsi index 1b8cf821..249a8dc7 100644 --- a/qcom/kalama-thermal.dtsi +++ b/qcom/kalama-thermal.dtsi @@ -5,7 +5,7 @@ }; &soc { - tsens0: thermal-sensor@c271000 { + tsens0: tsens0@c271000 { compatible = "qcom,tsens-v2"; reg = <0x0c271000 0x1ff>, /* TM */ <0x0c222000 0x1ff>; /* SROT */ @@ -16,7 +16,7 @@ #thermal-sensor-cells = <1>; }; - tsens1: thermal-sensor@c272000 { + tsens1: tsens1@c272000 { compatible = "qcom,tsens-v2"; reg = <0x0c272000 0x1ff>, /* TM */ <0x0c223000 0x1ff>; /* SROT */ @@ -27,7 +27,7 @@ #thermal-sensor-cells = <1>; }; - tsens2: thermal-sensor@c273000 { + tsens2: tsens2@c273000 { compatible = "qcom,tsens-v2"; reg = <0x0c273000 0x1ff>, /* TM */ <0x0c224000 0x1ff>; /* SROT */ diff --git a/qcom/khaje-atp.dtsi b/qcom/khaje-atp.dtsi index af91e0dd..8f0eb87b 100644 --- a/qcom/khaje-atp.dtsi +++ b/qcom/khaje-atp.dtsi @@ -115,15 +115,13 @@ }; &pm6125_adc_tm { - io-channels = <&pm6125_vadc ADC5_AMUX_THM1_100K_PU>, - <&pm6125_vadc ADC5_AMUX_THM2_100K_PU>, - <&pm6125_vadc ADC5_XO_THERM_100K_PU>, - <&pm6125_vadc ADC5_GPIO4_100K_PU>; + status = "ok"; rf_pa1_therm { - reg = ; + reg = <3>; + io-channels = <&pm6125_vadc ADC5_GPIO4_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; }; @@ -132,7 +130,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; - thermal-sensors = <&pm6125_adc_tm ADC5_GPIO4_100K_PU>; + thermal-sensors = <&pm6125_adc_tm 3>; wake-capable-sensor; trips { active-config0 { diff --git a/qcom/khaje-idp.dtsi b/qcom/khaje-idp.dtsi index d4d75671..213382a9 100644 --- a/qcom/khaje-idp.dtsi +++ b/qcom/khaje-idp.dtsi @@ -20,15 +20,13 @@ }; &pm6125_adc_tm { - io-channels = <&pm6125_vadc ADC5_AMUX_THM1_100K_PU>, - <&pm6125_vadc ADC5_AMUX_THM2_100K_PU>, - <&pm6125_vadc ADC5_XO_THERM_100K_PU>, - <&pm6125_vadc ADC5_GPIO4_100K_PU>; + status = "ok"; rf_pa1_therm { - reg = ; + reg = <3>; + io-channels = <&pm6125_vadc ADC5_GPIO4_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; }; @@ -37,7 +35,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; - thermal-sensors = <&pm6125_adc_tm ADC5_GPIO4_100K_PU>; + thermal-sensors = <&pm6125_adc_tm 3>; wake-capable-sensor; trips { active-config0 { diff --git a/qcom/khaje-pm7250b.dtsi b/qcom/khaje-pm7250b.dtsi index 26e0616e..b9f58431 100644 --- a/qcom/khaje-pm7250b.dtsi +++ b/qcom/khaje-pm7250b.dtsi @@ -25,20 +25,21 @@ }; &pm7250b_adc_tm { - io-channels = <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, - <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>; + status = "ok"; /* Channel nodes */ charger_skin_therm@4d { - reg = ; + reg = <0>; + io-channels = <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; conn_therm@4f { - reg = ; + reg = <1>; + io-channels = <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; }; @@ -47,7 +48,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; - thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM1_100K_PU>; + thermal-sensors = <&pm7250b_adc_tm 0>; wake-capable-sensor; trips { active-config0 { @@ -62,7 +63,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; - thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM3_100K_PU>; + thermal-sensors = <&pm7250b_adc_tm 1>; wake-capable-sensor; trips { active-config0 { diff --git a/qcom/khaje-qrd.dtsi b/qcom/khaje-qrd.dtsi index 4461431a..c628fabd 100644 --- a/qcom/khaje-qrd.dtsi +++ b/qcom/khaje-qrd.dtsi @@ -209,9 +209,6 @@ &thermal_zones { quiet-therm { polling-delay-passive = <2000>; - polling-delay = <0>; - thermal-sensors = <&pm6125_adc_tm ADC5_AMUX_THM2_100K_PU>; - trips { quiet_batt_trip0: batt-trip0 { temperature = <41000>; @@ -316,10 +313,6 @@ }; pa-therm0 { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm6125_adc_tm ADC5_AMUX_THM1_100K_PU>; - trips { pa_therm0_trip0: pa-therm0-trip0 { temperature = <52000>; diff --git a/qcom/khaje.dtsi b/qcom/khaje.dtsi index a3dac1fb..6c46439c 100644 --- a/qcom/khaje.dtsi +++ b/qcom/khaje.dtsi @@ -4151,24 +4151,20 @@ tpdm_turing_llm: tpdm@8861000 { &spmi_bus { qcom,pm6125@0 { pm6125_adc_tm_iio: adc_tm@3400 { - compatible = "qcom,adc-tm5-iio"; - reg = <0x3400 0x100>; + compatible = "qcom,spmi-adc-tm5-iio"; + reg = <0x3400>; #thermal-sensor-cells = <1>; #address-cells = <1>; #size-cells = <0>; - io-channels = <&pm6125_vadc ADC5_GPIO1_100K_PU>, - <&pm6125_vadc ADC5_GPIO2_100K_PU>; camera_flash_therm { - reg = ; - qcom,ratiometric; - qcom,hw-settle-time = <200>; + reg = <0>; + io-channels = <&pm6125_vadc ADC5_GPIO1_100K_PU>; }; emmc_ufs_therm { - reg = ; - qcom,ratiometric; - qcom,hw-settle-time = <200>; + reg = <1>; + io-channels = <&pm6125_vadc ADC5_GPIO2_100K_PU>; }; }; }; @@ -4177,27 +4173,27 @@ tpdm_turing_llm: tpdm@8861000 { &pm6125_adc_tm { #address-cells = <1>; #size-cells = <0>; - io-channels = <&pm6125_vadc ADC5_AMUX_THM1_100K_PU>, - <&pm6125_vadc ADC5_AMUX_THM2_100K_PU>, - <&pm6125_vadc ADC5_XO_THERM_100K_PU>; /* Channel nodes */ pa_therm0 { - reg = ; + reg = <0>; + io-channels = <&pm6125_vadc ADC5_AMUX_THM1_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; quiet_therm { - reg = ; + reg = <1>; + io-channels = <&pm6125_vadc ADC5_AMUX_THM2_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; xo_therm { - reg = ; + reg = <2>; + io-channels = <&pm6125_vadc ADC5_XO_THERM_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; }; diff --git a/qcom/khajeg.dtsi b/qcom/khajeg.dtsi index ed1fe0a9..bbaad82c 100644 --- a/qcom/khajeg.dtsi +++ b/qcom/khajeg.dtsi @@ -23,4 +23,8 @@ ipa_hw: qcom,ipa@0x5800000 { status = "disabled"; }; + + icnss: qcom,icnss@C800000 { + wlan-ipa-disabled; + }; }; diff --git a/qcom/lemans-adp-common.dtsi b/qcom/lemans-adp-common.dtsi index f82eb484..3316447c 100644 --- a/qcom/lemans-adp-common.dtsi +++ b/qcom/lemans-adp-common.dtsi @@ -1,3 +1,5 @@ +#include "lemans-pmic-overlay.dtsi" + / { model = "Qualcomm Technologies, Inc. Lemans ADP"; compatible = "qcom,lemans", "qcom,adp"; diff --git a/qcom/lemans-pinctrl.dtsi b/qcom/lemans-pinctrl.dtsi index 9f30c84a..9be9889c 100644 --- a/qcom/lemans-pinctrl.dtsi +++ b/qcom/lemans-pinctrl.dtsi @@ -1,2 +1,1473 @@ &tlmm { + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_active: qupv3_se0_i2c_active { + mux { + pins = "gpio20", "gpio21"; + function = "qup0_se0"; + }; + + config { + pins = "gpio20", "gpio21"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio20", "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio20", "gpio21"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se0_spi_pins: qupv3_se0_spi_pins { + qupv3_se0_spi_active: qupv3_se0_spi_active { + mux { + pins = "gpio20", "gpio21", + "gpio22", "gpio23"; + function = "qup0_se0"; + }; + + config { + pins = "gpio20", "gpio21", + "gpio22", "gpio23"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { + mux { + pins = "gpio20", "gpio21", + "gpio22", "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio20", "gpio21", + "gpio22", "gpio23"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { + qupv3_se1_i2c_active: qupv3_se1_i2c_active { + mux { + pins = "gpio24", "gpio25"; + function = "qup0_se1"; + }; + + config { + pins = "gpio24", "gpio25"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { + mux { + pins = "gpio24", "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio24", "gpio25"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se1_spi_pins: qupv3_se1_spi_pins { + qupv3_se1_spi_active: qupv3_se1_spi_active { + mux { + pins = "gpio24", "gpio25", + "gpio26", "gpio27"; + function = "qup0_se1"; + }; + + config { + pins = "gpio24", "gpio25", + "gpio26", "gpio27"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_sleep: qupv3_se1_spi_sleep { + mux { + pins = "gpio24", "gpio25", + "gpio26", "gpio27"; + function = "gpio"; + }; + + config { + pins = "gpio24", "gpio25", + "gpio26", "gpio27"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_active: qupv3_se2_i2c_active { + mux { + pins = "gpio36", "gpio37"; + function = "qup0_se2"; + }; + + config { + pins = "gpio36", "gpio37"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio36", "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio36", "gpio37"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_active: qupv3_se2_spi_active { + mux { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + function = "qup0_se2"; + }; + + config { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + function = "gpio"; + }; + + config { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { + qupv3_se3_i2c_active: qupv3_se3_i2c_active { + mux { + pins = "gpio28", "gpio29"; + function = "qup0_se3"; + }; + + config { + pins = "gpio28", "gpio29"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep { + mux { + pins = "gpio28", "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio29"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se3_spi_pins: qupv3_se3_spi_pins { + qupv3_se3_spi_active: qupv3_se3_spi_active { + mux { + pins = "gpio28", "gpio29", + "gpio30", "gpio31"; + function = "qup0_se3"; + }; + + config { + pins = "gpio28", "gpio29", + "gpio30", "gpio31"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se3_spi_sleep: qupv3_se3_spi_sleep { + mux { + pins = "gpio28", "gpio29", + "gpio30", "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio29", + "gpio30", "gpio31"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se4_i2c_pins: qupv3_se4_i2c_pins { + qupv3_se4_i2c_active: qupv3_se4_i2c_active { + mux { + pins = "gpio32", "gpio33"; + function = "qup0_se4"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep { + mux { + pins = "gpio32", "gpio33"; + function = "gpio"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se4_spi_pins: qupv3_se4_spi_pins { + qupv3_se4_spi_active: qupv3_se4_spi_active { + mux { + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + function = "qup0_se4"; + }; + + config { + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se4_spi_sleep: qupv3_se4_spi_sleep { + mux { + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { + qupv3_se5_i2c_active: qupv3_se5_i2c_active { + mux { + pins = "gpio36", "gpio37"; + function = "qup0_se5"; + }; + + config { + pins = "gpio36", "gpio37"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep { + mux { + pins = "gpio36", "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio36", "gpio37"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se5_spi_pins: qupv3_se5_spi_pins { + qupv3_se5_spi_active: qupv3_se5_spi_active { + mux { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + function = "qup0_se5"; + }; + + config { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_sleep: qupv3_se5_spi_sleep { + mux { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + function = "gpio"; + }; + + config { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se5_2uart_pins: qupv3_se5_2uart_pins { + qupv3_se5_2uart_active: qupv3_se5_2uart_active { + mux { + pins = "gpio38", "gpio39"; + function = "qup0_se5"; + }; + + config { + pins = "gpio38", "gpio39"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se5_2uart_sleep: qupv3_se5_2uart_sleep { + mux { + pins = "gpio38", "gpio39"; + function = "gpio"; + }; + + config { + pins = "gpio38", "gpio39"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se7_i2c_pins: qupv3_se7_i2c_pins { + qupv3_se7_i2c_active: qupv3_se7_i2c_active { + mux { + pins = "gpio40", "gpio41"; + function = "qup1_se0"; + }; + + config { + pins = "gpio40", "gpio41"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep { + mux { + pins = "gpio40", "gpio41"; + function = "gpio"; + }; + + config { + pins = "gpio40", "gpio41"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se7_spi_pins: qupv3_se7_spi_pins { + qupv3_se7_spi_active: qupv3_se7_spi_active { + mux { + pins = "gpio40", "gpio41", + "gpio42", "gpio43"; + function = "qup1_se0"; + }; + + config { + pins = "gpio40", "gpio41", + "gpio42", "gpio43"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se7_spi_sleep: qupv3_se7_spi_sleep { + mux { + pins = "gpio40", "gpio41", + "gpio42", "gpio43"; + function = "gpio"; + }; + + config { + pins = "gpio40", "gpio41", + "gpio42", "gpio43"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se8_i2c_pins: qupv3_se8_i2c_pins { + qupv3_se8_i2c_active: qupv3_se8_i2c_active { + mux { + pins = "gpio42", "gpio43"; + function = "qup1_se1"; + }; + + config { + pins = "gpio42", "gpio43"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep { + mux { + pins = "gpio42", "gpio43"; + function = "gpio"; + }; + + config { + pins = "gpio42", "gpio43"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se8_spi_pins: qupv3_se8_spi_pins { + qupv3_se8_spi_active: qupv3_se8_spi_active { + mux { + pins = "gpio42", "gpio43", + "gpio40", "gpio41"; + function = "qup1_se1"; + }; + + config { + pins = "gpio42", "gpio43", + "gpio40", "gpio41"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_sleep: qupv3_se8_spi_sleep { + mux { + pins = "gpio42", "gpio43", + "gpio40", "gpio41"; + function = "gpio"; + }; + + config { + pins = "gpio42", "gpio43", + "gpio40", "gpio41"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se9_i2c_pins: qupv3_se9_i2c_pins { + qupv3_se9_i2c_active: qupv3_se9_i2c_active { + mux { + pins = "gpio46", "gpio47"; + function = "qup1_se2"; + }; + + config { + pins = "gpio46", "gpio47"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep { + mux { + pins = "gpio46", "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio46", "gpio47"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se9_spi_pins: qupv3_se9_spi_pins { + qupv3_se9_spi_active: qupv3_se9_spi_active { + mux { + pins = "gpio46", "gpio47", + "gpio44", "gpio45"; + function = "qup1_se2"; + }; + + config { + pins = "gpio46", "gpio47", + "gpio44", "gpio45"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_sleep: qupv3_se9_spi_sleep { + mux { + pins = "gpio46", "gpio47", + "gpio44", "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio46", "gpio47", + "gpio44", "gpio45"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se9_2uart_pins: qupv3_se9_2uart_pins { + qupv3_se9_2uart_active: qupv3_se9_2uart_active { + mux { + pins = "gpio44", "gpio45"; + function = "qup1_se2"; + }; + + config { + pins = "gpio44", "gpio45"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se9_2uart_sleep: qupv3_se9_2uart_sleep { + mux { + pins = "gpio44", "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio44", "gpio45"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se10_i2c_pins: qupv3_se10_i2c_pins { + qupv3_se10_i2c_active: qupv3_se10_i2c_active { + mux { + pins = "gpio44", "gpio45"; + function = "qup1_se3"; + }; + + config { + pins = "gpio44", "gpio45"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep { + mux { + pins = "gpio44", "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio44", "gpio45"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se10_spi_pins: qupv3_se10_spi_pins { + qupv3_se10_spi_active: qupv3_se10_spi_active { + mux { + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + function = "qup1_se3"; + }; + + config { + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se10_spi_sleep: qupv3_se10_spi_sleep { + mux { + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se10_2uart_pins: qupv3_se10_2uart_pins { + qupv3_se10_2uart_active: qupv3_se10_2uart_active { + mux { + pins = "gpio46", "gpio47"; + function = "qup1_se3"; + }; + + config { + pins = "gpio46", "gpio47"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se10_2uart_sleep: qupv3_se10_2uart_sleep { + mux { + pins = "gpio46", "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio46", "gpio47"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se11_i2c_pins: qupv3_se11_i2c_pins { + qupv3_se11_i2c_active: qupv3_se11_i2c_active { + mux { + pins = "gpio48", "gpio49"; + function = "qup1_se4"; + }; + + config { + pins = "gpio48", "gpio49"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep { + mux { + pins = "gpio48", "gpio49"; + function = "gpio"; + }; + + config { + pins = "gpio48", "gpio49"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se11_spi_pins: qupv3_se11_spi_pins { + qupv3_se11_spi_active: qupv3_se11_spi_active { + mux { + pins = "gpio48", "gpio49", + "gpio50", "gpio51"; + function = "qup1_se4"; + }; + + config { + pins = "gpio48", "gpio49", + "gpio50", "gpio51"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se11_spi_sleep: qupv3_se11_spi_sleep { + mux { + pins = "gpio48", "gpio49", + "gpio50", "gpio51"; + function = "gpio"; + }; + + config { + pins = "gpio48", "gpio49", + "gpio50", "gpio51"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se12_i2c_pins: qupv3_se12_i2c_pins { + qupv3_se12_i2c_active: qupv3_se12_i2c_active { + mux { + pins = "gpio52", "gpio53"; + function = "qup1_se5"; + }; + + config { + pins = "gpio52", "gpio53"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep { + mux { + pins = "gpio52", "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio52", "gpio53"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se12_spi_pins: qupv3_se12_spi_pins { + qupv3_se12_spi_active: qupv3_se12_spi_active { + mux { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + function = "qup1_se5"; + }; + + config { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se12_spi_sleep: qupv3_se12_spi_sleep { + mux { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + function = "gpio"; + }; + + config { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se12_4uart_pins: qupv3_se12_4uart_pins { + qupv3_se12_default_cts: qupv3_se12_default_cts { + mux { + pins = "gpio52"; + function = "gpio"; + }; + + config { + pins = "gpio52"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se12_default_rtsrx: qupv3_se12_default_rtsrx { + mux { + pins = "gpio53", "gpio55"; + function = "gpio"; + }; + + config { + pins = "gpio53", "gpio55"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se12_default_tx: qupv3_se12_default_tx { + mux { + pins = "gpio54"; + function = "gpio"; + }; + + config { + pins = "gpio54"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se12_ctsrx: qupv3_se12_ctsrx { + mux { + pins = "gpio52", "gpio55"; + function = "qup1_se5"; + }; + + config { + pins = "gpio52", "gpio55"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se12_rts: qupv3_se12_rts { + mux { + pins = "gpio53"; + function = "qup1_se5"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se12_tx: qupv3_se12_tx { + mux { + pins = "gpio54"; + function = "qup1_se5"; + }; + + config { + pins = "gpio54"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se13_i2c_pins: qupv3_se13_i2c_pins { + qupv3_se13_i2c_active: qupv3_se13_i2c_active { + mux { + pins = "gpio56", "gpio57"; + function = "qup1_se6"; + }; + + config { + pins = "gpio56", "gpio57"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep { + mux { + pins = "gpio56", "gpio57"; + function = "gpio"; + }; + + config { + pins = "gpio56", "gpio57"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se14_i2c_pins: qupv3_se14_i2c_pins { + qupv3_se14_i2c_active: qupv3_se14_i2c_active { + mux { + pins = "gpio80", "gpio81"; + function = "qup2_se0"; + }; + + config { + pins = "gpio80", "gpio81"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se14_i2c_sleep: qupv3_se14_i2c_sleep { + mux { + pins = "gpio80", "gpio81"; + function = "gpio"; + }; + + config { + pins = "gpio80", "gpio81"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se14_spi_pins: qupv3_se14_spi_pins { + qupv3_se14_spi_active: qupv3_se14_spi_active { + mux { + pins = "gpio80", "gpio81", + "gpio82", "gpio83"; + function = "qup2_se0"; + }; + + config { + pins = "gpio80", "gpio81", + "gpio82", "gpio83"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se14_spi_sleep: qupv3_se14_spi_sleep { + mux { + pins = "gpio80", "gpio81", + "gpio82", "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio80", "gpio81", + "gpio82", "gpio83"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se15_i2c_pins: qupv3_se15_i2c_pins { + qupv3_se15_i2c_active: qupv3_se15_i2c_active { + mux { + pins = "gpio84", "gpio85"; + function = "qup2_se1"; + }; + + config { + pins = "gpio84", "gpio85"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep { + mux { + pins = "gpio84", "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio84", "gpio85"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se15_spi_pins: qupv3_se15_spi_pins { + qupv3_se15_spi_active: qupv3_se15_spi_active { + mux { + pins = "gpio84", "gpio85", + "gpio99", "gpio100"; + function = "qup2_se1"; + }; + + config { + pins = "gpio84", "gpio85", + "gpio99", "gpio100"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se15_spi_sleep: qupv3_se15_spi_sleep { + mux { + pins = "gpio84", "gpio85", + "gpio99", "gpio100"; + function = "gpio"; + }; + + config { + pins = "gpio84", "gpio85", + "gpio99", "gpio100"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se16_i2c_pins: qupv3_se16_i2c_pins { + qupv3_se16_i2c_active: qupv3_se16_i2c_active { + mux { + pins = "gpio86", "gpio87"; + function = "qup2_se2"; + }; + + config { + pins = "gpio86", "gpio87"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se16_i2c_sleep: qupv3_se16_i2c_sleep { + mux { + pins = "gpio86", "gpio87"; + function = "gpio"; + }; + + config { + pins = "gpio86", "gpio87"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se16_spi_pins: qupv3_se16_spi_pins { + qupv3_se16_spi_active: qupv3_se16_spi_active { + mux { + pins = "gpio86", "gpio87", + "gpio88", "gpio89"; + function = "qup2_se2"; + }; + + config { + pins = "gpio86", "gpio87", + "gpio88", "gpio89"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se16_spi_sleep: qupv3_se16_spi_sleep { + mux { + pins = "gpio86", "gpio87", + "gpio88", "gpio89"; + function = "gpio"; + }; + + config { + pins = "gpio86", "gpio87", + "gpio88", "gpio89"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se17_i2c_pins: qupv3_se17_i2c_pins { + qupv3_se17_i2c_active: qupv3_se17_i2c_active { + mux { + pins = "gpio91", "gpio92"; + function = "qup2_se3"; + }; + + config { + pins = "gpio91", "gpio92"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se17_i2c_sleep: qupv3_se17_i2c_sleep { + mux { + pins = "gpio91", "gpio92"; + function = "gpio"; + }; + + config { + pins = "gpio91", "gpio92"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se17_spi_pins: qupv3_se17_spi_pins { + qupv3_se17_spi_active: qupv3_se17_spi_active { + mux { + pins = "gpio91", "gpio92", + "gpio93", "gpio94"; + function = "qup2_se3"; + }; + + config { + pins = "gpio91", "gpio92", + "gpio93", "gpio94"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se17_spi_sleep: qupv3_se17_spi_sleep { + mux { + pins = "gpio91", "gpio92", + "gpio93", "gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio91", "gpio92", + "gpio93", "gpio94"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se17_4uart_pins: qupv3_se17_4uart_pins { + qupv3_se17_default_cts: qupv3_se17_default_cts { + mux { + pins = "gpio91"; + function = "gpio"; + }; + + config { + pins = "gpio91"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se17_default_rtsrx: qupv3_se17_default_rtsrx { + mux { + pins = "gpio92", "gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio92", "gpio94"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se17_default_tx: qupv3_se17_default_tx { + mux { + pins = "gpio93"; + function = "gpio"; + }; + + config { + pins = "gpio93"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se17_ctsrx: qupv3_se17_ctsrx { + mux { + pins = "gpio91", "gpio94"; + function = "qup2_se3"; + }; + + config { + pins = "gpio91", "gpio94"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se17_rts: qupv3_se17_rts { + mux { + pins = "gpio92"; + function = "qup2_se3"; + }; + + config { + pins = "gpio92"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se17_tx: qupv3_se17_tx { + mux { + pins = "gpio93"; + function = "qup2_se3"; + }; + + config { + pins = "gpio93"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se18_i2c_pins: qupv3_se18_i2c_pins { + qupv3_se18_i2c_active: qupv3_se18_i2c_active { + mux { + pins = "gpio95", "gpio96"; + function = "qup2_se4"; + }; + + config { + pins = "gpio95", "gpio96"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se18_i2c_sleep: qupv3_se18_i2c_sleep { + mux { + pins = "gpio95", "gpio96"; + function = "gpio"; + }; + + config { + pins = "gpio95", "gpio96"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se18_spi_pins: qupv3_se18_spi_pins { + qupv3_se18_spi_active: qupv3_se18_spi_active { + mux { + pins = "gpio95", "gpio96", + "gpio97", "gpio98"; + function = "qup2_se4"; + }; + + config { + pins = "gpio95", "gpio96", + "gpio97", "gpio98"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se18_spi_sleep: qupv3_se18_spi_sleep { + mux { + pins = "gpio95", "gpio96", + "gpio97", "gpio98"; + function = "gpio"; + }; + + config { + pins = "gpio95", "gpio96", + "gpio97", "gpio98"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se19_i2c_pins: qupv3_se19_i2c_pins { + qupv3_se19_i2c_active: qupv3_se19_i2c_active { + mux { + pins = "gpio99", "gpio100"; + function = "qup2_se5"; + }; + + config { + pins = "gpio99", "gpio100"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se19_i2c_sleep: qupv3_se19_i2c_sleep { + mux { + pins = "gpio99", "gpio100"; + function = "gpio"; + }; + + config { + pins = "gpio99", "gpio100"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se19_spi_pins: qupv3_se19_spi_pins { + qupv3_se19_spi_active: qupv3_se19_spi_active { + mux { + pins = "gpio99", "gpio100", + "gpio84", "gpio95"; + function = "qup2_se5"; + }; + + config { + pins = "gpio99", "gpio100", + "gpio84", "gpio95"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se19_spi_sleep: qupv3_se19_spi_sleep { + mux { + pins = "gpio99", "gpio100", + "gpio84", "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio99", "gpio100", + "gpio84", "gpio95"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se20_i2c_pins: qupv3_se20_i2c_pins { + qupv3_se20_i2c_active: qupv3_se20_i2c_active { + mux { + pins = "gpio97", "gpio98"; + function = "qup2_se6"; + }; + + config { + pins = "gpio97", "gpio98"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se20_i2c_sleep: qupv3_se20_i2c_sleep { + mux { + pins = "gpio97", "gpio98"; + function = "gpio"; + }; + + config { + pins = "gpio97", "gpio98"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se20_spi_pins: qupv3_se20_spi_pins { + qupv3_se20_spi_active: qupv3_se20_spi_active { + mux { + pins = "gpio97", "gpio98", + "gpio95", "gpio96"; + function = "qup2_se6"; + }; + + config { + pins = "gpio97", "gpio98", + "gpio95", "gpio96"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se20_spi_sleep: qupv3_se20_spi_sleep { + mux { + pins = "gpio97", "gpio98", + "gpio95", "gpio96"; + function = "gpio"; + }; + + config { + pins = "gpio97", "gpio98", + "gpio95", "gpio96"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se21_i2c_pins: qupv3_se21_i2c_pins { + qupv3_se21_i2c_active: qupv3_se21_i2c_active { + mux { + pins = "gpio13", "gpio14"; + function = "qup3_se0"; + }; + + config { + pins = "gpio13", "gpio14"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se21_i2c_sleep: qupv3_se21_i2c_sleep { + mux { + pins = "gpio13", "gpio14"; + function = "gpio"; + }; + + config { + pins = "gpio13", "gpio14"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se21_spi_pins: qupv3_se21_spi_pins { + qupv3_se21_spi_active: qupv3_se21_spi_active { + mux { + pins = "gpio13", "gpio14", + "gpio15", "gpio16"; + function = "qup3_se0"; + }; + + config { + pins = "gpio13", "gpio14", + "gpio15", "gpio16"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se21_spi_sleep: qupv3_se21_spi_sleep { + mux { + pins = "gpio13", "gpio14", + "gpio15", "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio13", "gpio14", + "gpio15", "gpio16"; + drive-strength = <2>; + bias-disable; + }; + }; + }; }; diff --git a/qcom/lemans-pmic-overlay.dtsi b/qcom/lemans-pmic-overlay.dtsi new file mode 100644 index 00000000..18ffd3dd --- /dev/null +++ b/qcom/lemans-pmic-overlay.dtsi @@ -0,0 +1,211 @@ +#include "pm8775.dtsi" + +&pm8775_1 { + /delete-node/ pon_pbs@800; + /delete-node/ pon_hlos@1200; + + pon_hlos@1200 { + compatible = "qcom,pm8998-pon"; + reg = <0x1200>, <0x800>; + reg-names = "pon_hlos", "pon_pbs"; + + pwrkey { + compatible = "qcom,pmk8350-pwrkey"; + interrupts = <0x0 0x12 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + }; + + resin { + compatible = "qcom,pmk8350-resin"; + interrupts = <0x0 0x12 0x6 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + }; + }; +}; + +&pm8775_2 { + /delete-node/ pon_pbs@800; + /delete-node/ pon_hlos@1200; + + pon_hlos@1200 { + compatible = "qcom,pm8998-pon"; + reg = <0x1200>, <0x800>; + reg-names = "pon_hlos", "pon_pbs"; + + pwrkey { + compatible = "qcom,pmk8350-pwrkey"; + interrupts = <0x2 0x12 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + }; + + resin { + compatible = "qcom,pmk8350-resin"; + interrupts = <0x2 0x12 0x6 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + }; + }; +}; + +&pm8775_3 { + /delete-node/ pon_pbs@800; + /delete-node/ pon_hlos@1200; + + pon_hlos@1200 { + compatible = "qcom,pm8998-pon"; + reg = <0x1200>, <0x800>; + reg-names = "pon_hlos", "pon_pbs"; + + pwrkey { + compatible = "qcom,pmk8350-pwrkey"; + interrupts = <0x4 0x12 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + }; + + resin { + compatible = "qcom,pmk8350-resin"; + interrupts = <0x4 0x12 0x6 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + }; + }; +}; + +&pm8775_4 { + /delete-node/ pon_pbs@800; + /delete-node/ pon_hlos@1200; + + pon_hlos@1200 { + compatible = "qcom,pm8998-pon"; + reg = <0x1200>, <0x800>; + reg-names = "pon_hlos", "pon_pbs"; + + pwrkey { + compatible = "qcom,pmk8350-pwrkey"; + interrupts = <0x6 0x12 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + }; + + resin { + compatible = "qcom,pmk8350-resin"; + interrupts = <0x6 0x12 0x6 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + }; + }; +}; + +&soc { + pmic-pon-log { + compatible = "qcom,pmic-pon-log"; + nvmem = <&pm8775_1_sdam_5>; + nvmem-names = "pon_log"; + }; +}; + +&thermal_zones { + pm8775_1_temp_alarm: pm8775_1_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8775_1_tz>; + + trips { + pm8775_1_trip0: trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8775_1_trip1: trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8775_1_trip2: trip2 { + temperature = <155000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pm8775_2_temp_alarm: pm8775_2_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8775_2_tz>; + + trips { + pm8775_2_trip0: trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8775_2_trip1: trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8775_2_trip2: trip2 { + temperature = <155000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pm8775_3_temp_alarm: pm8775_3_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8775_3_tz>; + + trips { + pm8775_3_trip0: trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8775_3_trip1: trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8775_3_trip2: trip2 { + temperature = <155000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pm8775_4_temp_alarm: pm8775_4_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8775_4_tz>; + + trips { + pm8775_4_trip0: trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8775_4_trip1: trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8775_4_trip2: trip2 { + temperature = <155000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; +}; diff --git a/qcom/lemans-qupv3.dtsi b/qcom/lemans-qupv3.dtsi new file mode 100644 index 00000000..2dc039a9 --- /dev/null +++ b/qcom/lemans-qupv3.dtsi @@ -0,0 +1,997 @@ +&soc { + /* QUPv3_0 wrapper instance */ + qupv3_0: qcom,qupv3_0_geni_se@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x9c0000 0x6000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus = <&apps_smmu 0x403 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + status = "ok"; + + qupv3_se0_i2c: i2c@980000 { + compatible = "qcom,i2c-geni"; + reg = <0x980000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se0_spi: spi@980000 { + compatible = "qcom,spi-geni"; + reg = <0x980000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se1_i2c: i2c@984000 { + compatible = "qcom,i2c-geni"; + reg = <0x984000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se1_spi: spi@984000 { + compatible = "qcom,spi-geni"; + reg = <0x984000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_spi_active>; + pinctrl-1 = <&qupv3_se1_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@988000 { + compatible = "qcom,i2c-geni"; + reg = <0x988000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se2_spi: spi@988000 { + compatible = "qcom,spi-geni"; + reg = <0x988000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se3_i2c: i2c@98c000 { + compatible = "qcom,i2c-geni"; + reg = <0x98c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_i2c_active>; + pinctrl-1 = <&qupv3_se3_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se3_spi: spi@98c000 { + compatible = "qcom,spi-geni"; + reg = <0x98c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_spi_active>; + pinctrl-1 = <&qupv3_se3_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se4_i2c: i2c@990000 { + compatible = "qcom,i2c-geni"; + reg = <0x990000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_i2c_active>; + pinctrl-1 = <&qupv3_se4_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se4_spi: spi@990000 { + compatible = "qcom,spi-geni"; + reg = <0x990000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_spi_active>; + pinctrl-1 = <&qupv3_se4_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se5_i2c: i2c@994000 { + compatible = "qcom,i2c-geni"; + reg = <0x994000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_i2c_active>; + pinctrl-1 = <&qupv3_se5_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se5_spi: spi@994000 { + compatible = "qcom,spi-geni"; + reg = <0x994000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_spi_active>; + pinctrl-1 = <&qupv3_se5_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se5_2uart: qcom,qup_uart@994000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x994000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_2uart_active>; + pinctrl-1 = <&qupv3_se5_2uart_sleep>; + status = "disabled"; + }; + }; + + /* QUPv3_1 wrapper instance */ + qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0xac0000 0x6000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0x443 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + + qupv3_se7_i2c: i2c@a80000 { + compatible = "qcom,i2c-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_i2c_active>; + pinctrl-1 = <&qupv3_se7_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se7_spi: spi@a80000 { + compatible = "qcom,spi-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_spi_active>; + pinctrl-1 = <&qupv3_se7_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se8_i2c: i2c@a84000 { + compatible = "qcom,i2c-geni"; + reg = <0xa84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_i2c_active>; + pinctrl-1 = <&qupv3_se8_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se8_spi: spi@a84000 { + compatible = "qcom,spi-geni"; + reg = <0xa84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_spi_active>; + pinctrl-1 = <&qupv3_se8_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se9_i2c: i2c@a88000 { + compatible = "qcom,i2c-geni"; + reg = <0xa88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_i2c_active>; + pinctrl-1 = <&qupv3_se9_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se9_spi: spi@a88000 { + compatible = "qcom,spi-geni"; + reg = <0xa88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_spi_active>; + pinctrl-1 = <&qupv3_se9_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* Debug UART Instance for RUMI*/ + qupv3_se9_2uart: qcom,qup_uart@a88000 { + compatible = "qcom,geni-debug-uart"; + reg = <0xa88000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_2uart_active>; + pinctrl-1 = <&qupv3_se9_2uart_sleep>; + status = "disabled"; + }; + + qupv3_se10_i2c: i2c@a8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_i2c_active>; + pinctrl-1 = <&qupv3_se10_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se10_spi: spi@a8c000 { + compatible = "qcom,spi-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_spi_active>; + pinctrl-1 = <&qupv3_se10_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* Debug UART Instance */ + qupv3_se10_2uart: qcom,qup_uart@a8c000 { + compatible = "qcom,geni-debug-uart"; + reg = <0xa8c000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_2uart_active>; + pinctrl-1 = <&qupv3_se10_2uart_sleep>; + status = "disabled"; + }; + + qupv3_se11_i2c: i2c@a90000 { + compatible = "qcom,i2c-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_i2c_active>; + pinctrl-1 = <&qupv3_se11_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se11_spi: spi@a90000 { + compatible = "qcom,spi-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_spi_active>; + pinctrl-1 = <&qupv3_se11_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se12_i2c: i2c@a94000 { + compatible = "qcom,i2c-geni"; + reg = <0xa94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_i2c_active>; + pinctrl-1 = <&qupv3_se12_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se12_spi: spi@a94000 { + compatible = "qcom,spi-geni"; + reg = <0xa94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_spi_active>; + pinctrl-1 = <&qupv3_se12_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se12_4uart: qcom,qup_uart@a94000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0xa94000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "active", "sleep", "shutdown"; + pinctrl-0 = <&qupv3_se12_default_cts>, + <&qupv3_se12_default_rtsrx>, <&qupv3_se12_default_tx>; + pinctrl-1 = <&qupv3_se12_ctsrx>, <&qupv3_se12_rts>, + <&qupv3_se12_tx>; + pinctrl-2 = <&qupv3_se12_ctsrx>, <&qupv3_se12_rts>, + <&qupv3_se12_tx>; + pinctrl-3 = <&qupv3_se12_default_cts>, + <&qupv3_se12_default_rtsrx>, <&qupv3_se12_default_tx>; + status = "disabled"; + }; + + qupv3_se13_i2c: i2c@a98000 { + compatible = "qcom,i2c-geni"; + reg = <0xa98000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_i2c_active>; + pinctrl-1 = <&qupv3_se13_i2c_sleep>; + status = "disabled"; + }; + }; + + /* QUPv3_2 wrapper instance */ + qupv3_2: qcom,qupv3_2_geni_se@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x8c0000 0x6000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + iommus = <&apps_smmu 0x5a3 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + + qupv3_se14_i2c: i2c@880000 { + compatible = "qcom,i2c-geni"; + reg = <0x880000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se14_i2c_active>; + pinctrl-1 = <&qupv3_se14_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se14_spi: spi@880000 { + compatible = "qcom,spi-geni"; + reg = <0x880000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se14_spi_active>; + pinctrl-1 = <&qupv3_se14_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se15_i2c: i2c@884000 { + compatible = "qcom,i2c-geni"; + reg = <0x884000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_i2c_active>; + pinctrl-1 = <&qupv3_se15_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se15_spi: spi@884000 { + compatible = "qcom,spi-geni"; + reg = <0x884000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_spi_active>; + pinctrl-1 = <&qupv3_se15_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se16_i2c: i2c@888000 { + compatible = "qcom,i2c-geni"; + reg = <0x888000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se16_i2c_active>; + pinctrl-1 = <&qupv3_se16_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se16_spi: spi@888000 { + compatible = "qcom,spi-geni"; + reg = <0x888000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se16_spi_active>; + pinctrl-1 = <&qupv3_se16_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se17_i2c: i2c@88c000 { + compatible = "qcom,i2c-geni"; + reg = <0x88c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se17_i2c_active>; + pinctrl-1 = <&qupv3_se17_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se17_spi: spi@88c000 { + compatible = "qcom,spi-geni"; + reg = <0x88c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se17_spi_active>; + pinctrl-1 = <&qupv3_se17_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* BT UART Instance */ + qupv3_se17_4uart: qcom,qup_uart@88c000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x88c000 0x4000>; + reg-names = "se_phys"; + interrupts-extended = <&intc GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 94 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "active", "sleep", "shutdown"; + pinctrl-0 = <&qupv3_se17_default_cts>, + <&qupv3_se17_default_rtsrx>, <&qupv3_se17_default_tx>; + pinctrl-1 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>, + <&qupv3_se17_tx>; + pinctrl-2 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>, + <&qupv3_se17_tx>; + pinctrl-3 = <&qupv3_se17_default_cts>, + <&qupv3_se17_default_rtsrx>, <&qupv3_se17_default_tx>; + qcom,wakeup-byte = <0xFD>; + status = "disabled"; + }; + + qupv3_se18_i2c: i2c@890000 { + compatible = "qcom,i2c-geni"; + reg = <0x890000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se18_i2c_active>; + pinctrl-1 = <&qupv3_se18_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se18_spi: spi@890000 { + compatible = "qcom,spi-geni"; + reg = <0x890000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se18_spi_active>; + pinctrl-1 = <&qupv3_se18_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se19_i2c: i2c@894000 { + compatible = "qcom,i2c-geni"; + reg = <0x894000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se19_i2c_active>; + pinctrl-1 = <&qupv3_se19_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se19_spi: spi@894000 { + compatible = "qcom,spi-geni"; + reg = <0x894000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se19_spi_active>; + pinctrl-1 = <&qupv3_se19_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se20_i2c: i2c@898000 { + compatible = "qcom,i2c-geni"; + reg = <0x898000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se20_i2c_active>; + pinctrl-1 = <&qupv3_se20_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se20_spi: spi@898000 { + compatible = "qcom,spi-geni"; + reg = <0x898000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se20_spi_active>; + pinctrl-1 = <&qupv3_se20_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + }; + + /* QUPv3_3 wrapper instance */ + qupv3_3: qcom,qupv3_3_geni_se@bc0000 { + compatible = "qcom,geni-se-qup"; + reg = <0xbc0000 0x6000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; + iommus = <&apps_smmu 0x43 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + status = "ok"; + + qupv3_se21_i2c: i2c@b80000 { + compatible = "qcom,i2c-geni"; + reg = <0xb80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_3 &clk_virt SLAVE_QUP_CORE_3>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_3>, + <&aggre1_noc MASTER_QUP_3 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se21_i2c_active>; + pinctrl-1 = <&qupv3_se21_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se21_spi: spi@b80000 { + compatible = "qcom,spi-geni"; + reg = <0xb80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_3 &clk_virt SLAVE_QUP_CORE_3>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_3>, + <&aggre1_noc MASTER_QUP_3 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se21_spi_active>; + pinctrl-1 = <&qupv3_se21_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + }; +}; diff --git a/qcom/lemans.dtsi b/qcom/lemans.dtsi index 1d366d21..c7ef9af7 100644 --- a/qcom/lemans.dtsi +++ b/qcom/lemans.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include / { model = "Qualcomm Technologies, Inc. Lemans"; @@ -22,7 +23,10 @@ chosen: chosen { }; - aliases { }; + aliases { + serial0 = &qupv3_se10_2uart; + ufshc1 = &ufshc_mem; /* Embedded UFS slot */ + }; soc: soc { }; @@ -598,6 +602,15 @@ interrupts = ; }; + ipcc_mproc: qcom,ipcc@408000 { + compatible = "qcom,ipcc"; + reg = <0x408000 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + clocks { xo_board: xo_board { compatible = "fixed-clock"; @@ -955,6 +968,172 @@ vendor_hooks: qcom,cpu-vendor-hooks { compatible = "qcom,cpu-vendor-hooks"; }; + + spmi_bus: qcom,spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc440000 0x1100>, + <0xc600000 0x2000000>, + <0xe600000 0x100000>, + <0xe700000 0xa0000>, + <0xc40a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + cell-index = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + }; + + thermal_zones: thermal-zones { + }; + + ufsphy_mem: ufsphy_mem@1d87000 { + reg = <0x1d87000 0xe10>; + reg-names = "phy_mem"; + #phy-cells = <0>; + + lanes-per-direction = <2>; + clock-names = "ref_clk_src", + "ref_clk", + "ref_aux_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + resets = <&ufshc_mem 0>; + status = "disabled"; + }; + + ufshc_mem: ufshc@1d84000 { + compatible = "qcom,ufshc"; + reg = <0x1d84000 0x3000>; + reg-names = "ufs_mem"; + interrupts = ; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + #reset-cells = <1>; + + lanes-per-direction = <2>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + + freq-table-hz = + <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + qcom,ufs-bus-bw,name = "ufshc_mem"; + qcom,ufs-bus-bw,num-cases = <26>; + qcom,ufs-bus-bw,num-paths = <2>; + qcom,ufs-bus-bw,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <0 0>, <0 0>, /* No vote */ + <922 0>, <1000 0>, /* PWM G1 */ + <1844 0>, <1000 0>, /* PWM G2 */ + <3688 0>, <1000 0>, /* PWM G3 */ + <7376 0>, <1000 0>, /* PWM G4 */ + <1844 0>, <1000 0>, /* PWM G1 L2 */ + <3688 0>, <1000 0>, /* PWM G2 L2 */ + <7376 0>, <1000 0>, /* PWM G3 L2 */ + <14752 0>, <1000 0>, /* PWM G4 L2 */ + <127796 0>, <1000 0>, /* HS G1 RA */ + <255591 0>, <1000 0>, /* HS G2 RA */ + <1492582 0>, <102400 0>, /* HS G3 RA */ + <2915200 0>, <204800 0>, /* HS G4 RA */ + <255591 0>, <1000 0>, /* HS G1 RA L2 */ + <511181 0>, <1000 0>, /* HS G2 RA L2 */ + <1492582 0>, <204800 0>, /* HS G3 RA L2 */ + <2915200 0>, <409600 0>, /* HS G4 RA L2 */ + <149422 0>, <1000 0>, /* HS G1 RB */ + <298189 0>, <1000 0>, /* HS G2 RB */ + <1492582 0>, <102400 0>, /* HS G3 RB */ + <2915200 0>, <204800 0>, /* HS G4 RB */ + <298189 0>, <1000 0>, /* HS G1 RB L2 */ + <596378 0>, <1000 0>, /* HS G2 RB L2 */ + /* As UFS working in HS G3 RB L2 mode, aggregated + * bandwidth (AB) should take care of providing + * optimum throughput requested. However, as tested, + * in order to scale up CNOC clock, instantaneous + * bindwidth (IB) needs to be given a proper value too. + */ + <1492582 0>, <204800 409600>, /* HS G3 RB L2 KBPs */ + <2915200 0>, <409600 409600>, /* HS G4 RB L2 */ + <7643136 0>, <307200 0>; /* Max. bandwidth */ + + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", + "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", + "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", + "MAX"; + + reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + iommus = <&apps_smmu 0x100 0x0>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + qcom,disable-lpm; + + status = "disabled"; + + qos0 { + mask = <0xf0>; + vote = <44>; + }; + + qos1 { + mask = <0x0f>; + vote = <44>; + }; + }; }; #include "lemans-4pmic-regulators.dtsi" @@ -1117,4 +1296,40 @@ status = "ok"; }; +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-waipio"; + + vdda-phy-supply = <&L4A>; + vdda-pll-supply = <&L1C>; + vdda-phy-max-microamp = <137000>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + + vcc-supply = <&L8A>; + vcc-voltage-level = <2504000 2506000>; + vcc-max-microamp = <1100000>; + + vccq-supply = <&L4C>; + vccq-max-microamp = <1200000>; + + vccq2-supply = <&S4A>; + vccq2-max-microamp = <800000>; + + qcom,vddp-ref-clk-supply = <&L4C>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; + #include "lemans-debug.dtsi" +#include "lemans-qupv3.dtsi" + +&qupv3_se10_2uart { + status = "ok"; +}; diff --git a/qcom/monaco-atp-v1-overlay.dts b/qcom/monaco-atp-v1-overlay.dts new file mode 100644 index 00000000..acea30f5 --- /dev/null +++ b/qcom/monaco-atp-v1-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "monaco-atp-v1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco ATP V1.0"; + qcom,board-id = <0x010021 0x0>; +}; diff --git a/qcom/monaco-atp-v1.dtsi b/qcom/monaco-atp-v1.dtsi new file mode 100644 index 00000000..6fea5bc4 --- /dev/null +++ b/qcom/monaco-atp-v1.dtsi @@ -0,0 +1 @@ +#include "monaco-idp-v1.dtsi" diff --git a/qcom/monaco-standalone-atp-v1-overlay.dts b/qcom/monaco-standalone-atp-v1-overlay.dts new file mode 100644 index 00000000..fdd0c502 --- /dev/null +++ b/qcom/monaco-standalone-atp-v1-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "monaco-standalone-atp-v1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco standalone ATP V1.0"; + qcom,board-id = <0x010021 0x1>; +}; diff --git a/qcom/monaco-standalone-atp-v1.dtsi b/qcom/monaco-standalone-atp-v1.dtsi new file mode 100644 index 00000000..d8a5c8c6 --- /dev/null +++ b/qcom/monaco-standalone-atp-v1.dtsi @@ -0,0 +1 @@ +#include "monaco-standalone-idp-v1.dtsi" diff --git a/qcom/monaco-standalone-idp-v1-overlay.dts b/qcom/monaco-standalone-idp-v1-overlay.dts new file mode 100644 index 00000000..22c69bed --- /dev/null +++ b/qcom/monaco-standalone-idp-v1-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "monaco-standalone-idp-v1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco standalone IDP V1.0"; + qcom,board-id = <0x010022 0x1>; +}; diff --git a/qcom/monaco-standalone-idp-v1.dtsi b/qcom/monaco-standalone-idp-v1.dtsi new file mode 100644 index 00000000..b897432c --- /dev/null +++ b/qcom/monaco-standalone-idp-v1.dtsi @@ -0,0 +1 @@ +#include "monaco-idp-v1-common.dtsi" diff --git a/qcom/monaco-standalone-idp-v2-overlay.dts b/qcom/monaco-standalone-idp-v2-overlay.dts new file mode 100644 index 00000000..a3d1a924 --- /dev/null +++ b/qcom/monaco-standalone-idp-v2-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "monaco-standalone-idp-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco standalone IDP V2.0"; + qcom,board-id = <0x020022 0x1>; +}; diff --git a/qcom/monaco-standalone-idp-v2.dtsi b/qcom/monaco-standalone-idp-v2.dtsi new file mode 100644 index 00000000..272f2670 --- /dev/null +++ b/qcom/monaco-standalone-idp-v2.dtsi @@ -0,0 +1,2 @@ + +#include "monaco-standalone-idp-v1.dtsi" diff --git a/qcom/monaco-standalone-idp-v3-overlay.dts b/qcom/monaco-standalone-idp-v3-overlay.dts new file mode 100644 index 00000000..253330f8 --- /dev/null +++ b/qcom/monaco-standalone-idp-v3-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "monaco-standalone-idp-v3.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco standalone IDP V3.0"; + qcom,board-id = <0x030022 0x1>; +}; diff --git a/qcom/monaco-standalone-idp-v3.dtsi b/qcom/monaco-standalone-idp-v3.dtsi new file mode 100644 index 00000000..d8a5c8c6 --- /dev/null +++ b/qcom/monaco-standalone-idp-v3.dtsi @@ -0,0 +1 @@ +#include "monaco-standalone-idp-v1.dtsi" diff --git a/qcom/monaco-standalone-wdp-v1-overlay.dts b/qcom/monaco-standalone-wdp-v1-overlay.dts new file mode 100644 index 00000000..66f93312 --- /dev/null +++ b/qcom/monaco-standalone-wdp-v1-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "monaco-standalone-wdp-v1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco standalone WDP V1.0"; + qcom,board-id = <0x010024 0x1>; +}; diff --git a/qcom/monaco-standalone-wdp-v1.dtsi b/qcom/monaco-standalone-wdp-v1.dtsi new file mode 100644 index 00000000..d8a5c8c6 --- /dev/null +++ b/qcom/monaco-standalone-wdp-v1.dtsi @@ -0,0 +1 @@ +#include "monaco-standalone-idp-v1.dtsi" diff --git a/qcom/monaco-thermal-overlay.dtsi b/qcom/monaco-thermal-overlay.dtsi index eba02e00..d9b05e60 100644 --- a/qcom/monaco-thermal-overlay.dtsi +++ b/qcom/monaco-thermal-overlay.dtsi @@ -12,12 +12,12 @@ trip1_cpu2 { trip = <&pm5100_trip0>; - cooling-device = <&cpu2_isolate 1 1>; + cooling-device = <&cpu2_pause 1 1>; }; trip1_cpu3 { trip = <&pm5100_trip0>; - cooling-device = <&cpu3_isolate 1 1>; + cooling-device = <&cpu3_pause 1 1>; }; }; }; @@ -33,12 +33,12 @@ cpu2_cdev { trip = <&bcl_lvl0>; - cooling-device = <&cpu2_isolate 1 1>; + cooling-device = <&cpu2_pause 1 1>; }; cpu3_cdev { trip = <&bcl_lvl0>; - cooling-device = <&cpu3_isolate 1 1>; + cooling-device = <&cpu3_pause 1 1>; }; gpu_cdev { @@ -60,7 +60,7 @@ cpu1_cdev { trip = <&bcl_lvl1>; - cooling-device = <&cpu1_isolate 1 1>; + cooling-device = <&cpu1_pause 1 1>; }; gpu_cdev { @@ -88,12 +88,12 @@ soc_cpu2 { trip = <&socd_trip>; - cooling-device = <&cpu2_isolate 1 1>; + cooling-device = <&cpu2_pause 1 1>; }; soc_cpu3 { trip = <&socd_trip>; - cooling-device = <&cpu3_isolate 1 1>; + cooling-device = <&cpu3_pause 1 1>; }; gpu_cdev { diff --git a/qcom/monaco-thermal.dtsi b/qcom/monaco-thermal.dtsi index 31ccb318..ae46ae06 100644 --- a/qcom/monaco-thermal.dtsi +++ b/qcom/monaco-thermal.dtsi @@ -1,6 +1,10 @@ #include -&cpufreq_hw { +&msm_gpu { + #cooling-cells = <2>; +}; + +&soc { #address-cells = <1>; #size-cells = <1>; lmh_dcvs0: qcom,limits-dcvs@f550800 { @@ -9,42 +13,61 @@ qcom,affinity = <0>; reg = <0xf550800 0x1000>, <0xf521000 0x1000>; - qcom,no-cooling-device-register; }; - qcom,cpu-isolation { - compatible = "qcom,cpu-isolate"; - cpu0_isolate: cpu0-isolate { - qcom,cpu = <&CPU0>; + qcom,cpu-pause { + compatible = "qcom,thermal-pause"; + + cpu0_pause: cpu0-pause { + qcom,cpus = <&CPU0>; #cooling-cells = <2>; }; - cpu1_isolate: cpu1-isolate { - qcom,cpu = <&CPU1>; + cpu1_pause: cpu1-pause { + qcom,cpus = <&CPU1>; #cooling-cells = <2>; }; - cpu2_isolate: cpu2-isolate { - qcom,cpu = <&CPU2>; + cpu2_pause: cpu2-pause { + qcom,cpus = <&CPU2>; #cooling-cells = <2>; }; - cpu3_isolate: cpu3-isolate { - qcom,cpu = <&CPU3>; + cpu3_pause: cpu3-pause { + qcom,cpus = <&CPU3>; #cooling-cells = <2>; }; + + /* Thermal-engine cooling devices */ + pause-cpu0 { + qcom,cpus = <&CPU0>; + qcom,cdev-alias = "pause-cpu0"; + }; + + pause-cpu1 { + qcom,cpus = <&CPU1>; + qcom,cdev-alias = "pause-cpu1"; + }; + + pause-cpu2 { + qcom,cpus = <&CPU2>; + qcom,cdev-alias = "pause-cpu2"; + }; + + pause-cpu3 { + qcom,cpus = <&CPU3>; + qcom,cdev-alias = "pause-cpu3"; + }; }; -}; -&soc { tsens0:tsens@4410000 { compatible = "qcom,tsens26xx"; reg = <0x04410000 0x20>, <0x04411000 0x140>; reg-names = "tsens_srot_physical", "tsens_tm_physical"; - interrupts-extended = <&intc 0 275 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 190 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <&mpm 89 IRQ_TYPE_EDGE_RISING>; interrupt-names = "tsens-upper-lower", "tsens-critical", @@ -111,15 +134,218 @@ reg = <0xf550800 0x1000>; #cooling-cells = <2>; }; + + qcom,devfreq-cdev { + compatible = "qcom,devfreq-cdev"; + qcom,devfreq = <&msm_gpu>; + }; + + qcom,cpufreq-cdev { + compatible = "qcom,cpufreq-cdev"; + qcom,cpus = <&CPU0>; + }; }; &thermal_zones { - gpu-step { - polling-delay-passive = <10>; + mapss { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 0>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + wlan { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 1>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 2>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu0_2_config: cpu-0-2-config { + temperature = <100000>; + hysteresis = <10000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu0_cdev { + trip = <&cpu0_2_config>; + cooling-device = <&cpu0_pause 1 1>; + }; + + cpu2_cdev { + trip = <&cpu0_2_config>; + cooling-device = <&cpu2_pause 1 1>; + }; + }; + }; + + cpuss-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 3>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu1_3_config: cpu-1-3-config { + temperature = <100000>; + hysteresis = <10000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu1_cdev { + trip = <&cpu1_3_config>; + cooling-device = <&cpu1_pause 1 1>; + }; + + cpu3_cdev { + trip = <&cpu1_3_config>; + cooling-device = <&cpu3_pause 1 1>; + }; + }; + }; + + mdm-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdm0_cx_mon: mdm0-cx-mon { + temperature = <90000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + mdm0-cx-cdev0 { + trip = <&mdm0_cx_mon>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + mdm0-cx-cdev1 { + trip = <&mdm0_cx_mon>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; + + mdm-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdm1_cx_mon: mdm1-cx-mon { + temperature = <90000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + mdm1-cx-cdev0 { + trip = <&mdm1_cx_mon>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + mdm1-cx-cdev1 { + trip = <&mdm1_cx_mon>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; + + gpu { + polling-delay-passive = <0>; polling-delay = <0>; - thermal-governor = "step_wise"; thermal-sensors = <&tsens0 6>; trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + gpu_step_trip: gpu-trip { temperature = <85000>; hysteresis = <0>; @@ -132,6 +358,11 @@ type = "passive"; }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; }; cooling-maps { @@ -154,277 +385,29 @@ }; }; - cpuss-0-step { + camera { polling-delay-passive = <0>; polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 2>; - trips { - cpu0_2_config: cpu-0-2-config { - temperature = <100000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - - cooling-maps { - cpu0_cdev { - trip = <&cpu0_2_config>; - cooling-device = <&cpu0_isolate 1 1>; - }; - - cpu2_cdev { - trip = <&cpu0_2_config>; - cooling-device = <&cpu2_isolate 1 1>; - }; - }; - }; - - cpuss-1-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 3>; - trips { - cpu1_3_config: cpu-1-3-config { - temperature = <100000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - - cooling-maps { - cpu1_cdev { - trip = <&cpu1_3_config>; - cooling-device = <&cpu1_isolate 1 1>; - }; - - cpu3_cdev { - trip = <&cpu1_3_config>; - cooling-device = <&cpu3_isolate 1 1>; - }; - }; - }; - - mdm-0-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 4>; - trips { - mdm0_cx_mon: mdm0-cx-mon { - temperature = <90000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - - cooling-maps { - mdm0-cx-cdev0 { - trip = <&mdm0_cx_mon>; - cooling-device = <&msm_gpu THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - - mdm0-cx-cdev1 { - trip = <&mdm0_cx_mon>; - cooling-device = <&modem_tj 3 3>; - }; - }; - }; - - mdm-1-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 5>; - trips { - mdm1_cx_mon: mdm1-cx-mon { - temperature = <90000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - - cooling-maps { - mdm1-cx-cdev0 { - trip = <&mdm1_cx_mon>; - cooling-device = <&msm_gpu THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - - mdm1-cx-cdev1 { - trip = <&mdm1_cx_mon>; - cooling-device = <&modem_tj 3 3>; - }; - }; - }; - - mapss-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens0 0>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <105000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - wlan-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens0 1>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <105000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpuss-0-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens0 2>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <105000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpuss-1-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens0 3>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <105000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - mdm-0-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens0 4>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <105000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - mdm-1-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens0 5>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <105000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - gpu-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens0 6>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <105000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - camera-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; thermal-sensors = <&tsens0 7>; trips { - active-config0 { + thermal-engine-config { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; reset-mon-cfg { - temperature = <105000>; + temperature = <115000>; hysteresis = <5000>; type = "passive"; }; }; }; - zeroc-0-step { + zeroc { polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&tsens0 16>; - thermal-governor = "step_wise"; trips { zeroc_0_trip: active-config0 { temperature = <1>; @@ -461,7 +444,6 @@ polling-delay = <0>; thermal-sensors = <&qmi_sensor (QMI_MODEM_INST_ID)>; - thermal-governor = "step_wise"; trips { rf_cal_trip: rf-cal-config { temperature = <2000>; diff --git a/qcom/monaco-wdp-v1-overlay.dts b/qcom/monaco-wdp-v1-overlay.dts new file mode 100644 index 00000000..f146b0b7 --- /dev/null +++ b/qcom/monaco-wdp-v1-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "monaco-wdp-v1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco WDP V1.0"; + qcom,board-id = <0x010024 0x0>; +}; diff --git a/qcom/monaco-wdp-v1.dtsi b/qcom/monaco-wdp-v1.dtsi new file mode 100644 index 00000000..6fea5bc4 --- /dev/null +++ b/qcom/monaco-wdp-v1.dtsi @@ -0,0 +1 @@ +#include "monaco-idp-v1.dtsi" diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 4f5518a3..856c0ea1 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -198,29 +198,29 @@ reg = <0x0 0x4ab00000 0x0 0x5E00000>; }; - pil_video_mem: pil_video_region@50900000 { + video_mem: video_region@50900000 { no-map; - reg = <0x0 0x50900000 0x0 0x500000>; + reg = <0x0 0x50900000 0x0 0x700000>; }; - pil_adsp_mem: adsp_regions@50E00000 { + pil_adsp_mem: adsp_regions@51000000 { no-map; - reg = <0x0 0x50E00000 0x0 0x1900000>; + reg = <0x0 0x51000000 0x0 0x1900000>; }; - pil_ipa_fw_mem: ips_fw_region@52700000 { + pil_ipa_fw_mem: ips_fw_region@52900000 { no-map; - reg = <0x0 0x52700000 0x0 0x10000>; + reg = <0x0 0x52900000 0x0 0x10000>; }; - pil_ipa_gsi_mem: ipa_gsi_region@52710000 { + pil_ipa_gsi_mem: ipa_gsi_region@52910000 { no-map; - reg = <0x0 0x52710000 0x0 0x5000>; + reg = <0x0 0x52910000 0x0 0x5000>; }; - pil_gpu_mem: gpu_region@52715000 { + pil_gpu_mem: gpu_region@52915000 { no-map; - reg = <0x0 0x52715000 0x0 0x2000>; + reg = <0x0 0x52915000 0x0 0x2000>; }; stats_region: stats_region@60000000 { @@ -1878,6 +1878,128 @@ io-channel-names = "chg_type"; }; +&qupv3_se1_i2c { + status = "ok"; + + tsc@24 { + compatible = "parade,pt_i2c_adapter"; + reg = <0x24>; + status = "ok"; + interrupt-parent = <&tlmm>; + interrupts = <80 0x2008>; + parade,adapter_id = "pt_i2c_adapter"; + vcc_i2c-supply = <&L21A>; + vdd-supply = <&L29A>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + + parade,core { + parade,name = "pt_core"; + + parade,irq_gpio = <&tlmm 13 0x2008>; + parade,rst_gpio = <&tlmm 12 0x00>; + parade,hid_desc_register = <1>; + /* + * PT_CORE_FLAG_NONE = 0x00 + * PT_CORE_FLAG_POWEROFF_ON_SLEEP = 0x02 + * PT_CORE_FLAG_RESTORE_PARAMETERS = 0x04 + * PT_CORE_FLAG_DEEP_STANDBY = 0x08 + * PT_CORE_FLAG_SKIP_SYS_SLEEP = 0x10 + * PT_CORE_FLAG_SKIP_RUNTIME = 0x20 + * PT_CORE_FLAG_SKIP_RESUME = 0x40 + */ + parade,flags = <6>; + /* PT_CORE_EWG_NONE */ + parade,easy_wakeup_gesture = <1>; + /* 0:AUTO 1:PIP1_ONLY 2:PIP2_CAPABLE*/ + parade,config_dut_generation = <1>; + /* 0:False 1:True*/ + parade,watchdog_force_stop = <0>; + /* + * PT_PANEL_ID_DISABLE = 0x00 + * PT_PANEL_ID_BY_BL = 0x01 + * PT_PANEL_ID_BY_SYS_INFO = 0x02 + * PT_PANEL_ID_BY_MFG_DATA = 0x04 + */ + parade,panel_id_support = <0>; + parade,btn_keys = <172 /* KEY_HOMEPAGE */ + /* previously was KEY_HOME, new Android versions use KEY_HOMEPAGE */ + 139 /* KEY_MENU */ + 158 /* KEY_BACK */ + 217 /* KEY_SEARCH */ + 114 /* KEY_VOLUMEDOWN */ + 115 /* KEY_VOLUMEUP */ + 212 /* KEY_CAMERA */ + 116>; /* KEY_POWER */ + parade,btn_keys-tag = <0>; + + parade,mt { + parade,name = "pt_mt"; + parade,inp_dev_name = "pt_mt"; + /* + * PT_MT_FLAG_NONE = 0x00 + * PT_MT_FLAG_FLIP = 0x08 + * PT_MT_FLAG_INV_X = 0x10 + * PT_MT_FLAG_INV_Y = 0x20 + * PT_MT_FLAG_VKEYS = 0x40 + */ + parade,flags = <0x08>; + parade,abs = + /* ABS_MT_POSITION_X, CY_ABS_MIN_X, CY_ABS_MAX_X, 0, 0 */ + <0x35 0 880 0 0 + /* ABS_MT_POSITION_Y, CY_ABS_MIN_Y, CY_ABS_MAX_Y, 0, 0 */ + 0x36 0 1280 0 0 + /* ABS_MT_PRESSURE, CY_ABS_MIN_P, CY_ABS_MAX_P, 0, 0 */ + 0x3a 0 255 0 0 + /* CY_IGNORE_VALUE, CY_ABS_MIN_W, CY_ABS_MAX_W, 0, 0 */ + 0xffff 0 255 0 0 + /* ABS_MT_TRACKING_ID, CY_ABS_MIN_T, CY_ABS_MAX_T, 0, 0 */ + 0x39 0 15 0 0 + /* ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0 */ + 0x30 0 255 0 0 + /* ABS_MT_TOUCH_MINOR, 0, 255, 0, 0 */ + 0x31 0 255 0 0 + /* ABS_MT_ORIENTATION, -127, 127, 0, 0 */ + 0x34 0xffffff81 127 0 0 + /* ABS_MT_TOOL_TYPE, 0, MT_TOOL_MAX, 0, 0 */ + 0x37 0 1 0 0 + /* ABS_DISTANCE, 0, 255, 0, 0 */ + 0x19 0 255 0 0>; + + parade,vkeys_x = <720>; + parade,vkeys_y = <1280>; + + parade,virtual_keys = /* KeyCode CenterX CenterY Width Height */ + /* KEY_BACK */ + <158 90 1360 160 180 + /* KEY_MENU */ + 139 270 1360 160 180 + /* KEY_HOMEPAGE */ + 172 450 1360 160 180 + /* KEY SEARCH */ + 217 630 1360 160 180>; + }; + + parade,btn { + parade,name = "pt_btn"; + + parade,inp_dev_name = "pt_btn"; + }; + + parade,proximity { + parade,name = "pt_proximity"; + + parade,inp_dev_name = "pt_proximity"; + parade,abs = + <0x19 0 1 0 0>; + }; + }; + }; +}; + &qupv3_se6_2uart { status = "ok"; }; diff --git a/qcom/msm-arm-smmu-lemans.dtsi b/qcom/msm-arm-smmu-lemans.dtsi index e3487485..488884d9 100644 --- a/qcom/msm-arm-smmu-lemans.dtsi +++ b/qcom/msm-arm-smmu-lemans.dtsi @@ -281,6 +281,192 @@ }; }; + pcie_smmu: pcie-smmu@0x15200000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15200000 0x80000>, + <0x152F2000 0x28>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,split-tables; + #global-interrupts = <2>; + #size-cells = <1>; + #address-cells = <1>; + #tcu-testbus-version = <1>; + ranges; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + pcie_0_tbu: pcie_0_tbu@152f9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x152F9000 0x1000>, + <0x152F2200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + qcom,iova-width = <36>; + }; + + pcie_1_tbu: pcie_1_tbu@152fb000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x152FB000 0x1000>, + <0x152F3200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + qcom,iova-width = <36>; + }; + }; + + kgsl_smmu: kgsl-smmu@3da0000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x3da0000 0x20000>, + <0x3dca000 0x28>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,split-tables; + #global-interrupts = <2>; + #size-cells = <1>; + #address-cells = <1>; + #tcu-testbus-version = <1>; + ranges; + dma-coherent; + qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cc_cx_gdsc>; + + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>; + + clock-names = "gcc_gpu_memnoc_gfx", + "gcc_gpu_snoc_dvm_gfx", + "gpu_cc_ahb", + "gpu_cc_hlos1_vote_gpu_smmu_clk", + "gpu_cc_cx_gmu_clk", + "gpu_cc_hub_cx_int_clk", + "gpu_cc_hub_aon_clk"; + + + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + + gfx_0_tbu: gfx_0_tbu@3dd1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x3DD1000 0x1000>, + <0x3DCA200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + qcom,iova-width = <49>; + }; + + gfx_1_tbu: gfx_1_tbu@3dd3000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x3DD3000 0x1000>, + <0x3DCA208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + qcom,iova-width = <49>; + }; + + gfx_2_tbu: gfx_2_tbu@3dd9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x3DD9000 0x1000>, + <0x3DCB200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x800 0x400>; + qcom,iova-width = <49>; + }; + + gfx_3_tbu: gfx_3_tbu@3ddb000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x3DDB000 0x1000>, + <0x3DCB208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0xC00 0x400>; + qcom,iova-width = <49>; + }; + }; + iommu_test_device { compatible = "qcom,iommu-debug-test"; @@ -307,5 +493,51 @@ iommus = <&apps_smmu 0x581 0>; dma-coherent; }; + + usecase0_pcie { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&pcie_smmu 0x440 0x0>; + }; + + usecase1_pcie_fastmap { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&pcie_smmu 0x440 0x0>; + qcom,iommu-dma = "fastmap"; + }; + + usecase2_pcie_atomic { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&pcie_smmu 0x440 0x0>; + qcom,iommu-dma = "atomic"; + }; + + usecase3_pcie_dma { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&pcie_smmu 0x440 0x0>; + dma-coherent; + }; + + usecase0_kgsl { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&kgsl_smmu 0x7 0xC00>; + }; + + usecase1_kgsl_fastmap { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&kgsl_smmu 0x7 0xC00>; + qcom,iommu-dma = "fastmap"; + }; + + usecase2_kgsl_atomic { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&kgsl_smmu 0x7 0xC00>; + qcom,iommu-dma = "atomic"; + }; + + usecase3_kgsl_dma { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&kgsl_smmu 0x407 0xC00>; + dma-coherent; + }; }; }; diff --git a/qcom/msm-arm-smmu-monaco.dtsi b/qcom/msm-arm-smmu-monaco.dtsi index 8f7d889c..5ae347c6 100644 --- a/qcom/msm-arm-smmu-monaco.dtsi +++ b/qcom/msm-arm-smmu-monaco.dtsi @@ -16,11 +16,9 @@ vdd-supply = <&gpu_cx_gdsc>; clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, - <&gpucc GPU_CC_AHB_CLK>, <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; clock-names = "gcc_gpu_memnoc_gfx", "gcc_gpu_snoc_dvm_gfx", - "gpu_cc_ahb", "gpu_cc_hlos1_vote_gpu_smmu_clk"; #size-cells = <1>; #address-cells = <1>; diff --git a/qcom/msm-arm-smmu-sm8150-v2.dtsi b/qcom/msm-arm-smmu-sm8150-v2.dtsi index f1bc17f9..0a438d2d 100644 --- a/qcom/msm-arm-smmu-sm8150-v2.dtsi +++ b/qcom/msm-arm-smmu-sm8150-v2.dtsi @@ -2,7 +2,7 @@ &soc { kgsl_smmu: kgsl-smmu@2ca0000 { - compatible = "qcom,qsmmu-v500"; + compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu"; reg = <0x2ca0000 0x10000>, <0x2cc2000 0x20>; reg-names = "base", "tcu-base"; diff --git a/qcom/pm5100.dtsi b/qcom/pm5100.dtsi index 39cce56e..121c119a 100644 --- a/qcom/pm5100.dtsi +++ b/qcom/pm5100.dtsi @@ -570,7 +570,6 @@ pm5100-ibat-lvl0 { polling-delay-passive = <0>; polling-delay = <0>; - thermal-governor = "step_wise"; thermal-sensors = <&pm5100_bcl 0>; trips { @@ -585,7 +584,6 @@ pm5100-ibat-lvl1 { polling-delay-passive = <0>; polling-delay = <0>; - thermal-governor = "step_wise"; thermal-sensors = <&pm5100_bcl 1>; trips { @@ -600,10 +598,15 @@ pm5100-bcl-lvl0 { polling-delay-passive = <100>; polling-delay = <0>; - thermal-governor = "step_wise"; thermal-sensors = <&pm5100_bcl 5>; trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + bcl_lvl0: bcl-lvl0 { temperature = <1>; hysteresis = <1>; @@ -615,10 +618,15 @@ pm5100-bcl-lvl1 { polling-delay-passive = <100>; polling-delay = <0>; - thermal-governor = "step_wise"; thermal-sensors = <&pm5100_bcl 6>; trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + bcl_lvl1: bcl-lvl1 { temperature = <1>; hysteresis = <1>; @@ -630,10 +638,15 @@ pm5100-bcl-lvl2 { polling-delay-passive = <100>; polling-delay = <0>; - thermal-governor = "step_wise"; thermal-sensors = <&pm5100_bcl 7>; trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + bcl_lvl2: bcl-lvl2 { temperature = <1>; hysteresis = <1>; @@ -645,10 +658,15 @@ socd { polling-delay-passive = <100>; polling-delay = <0>; - thermal-governor = "step_wise"; thermal-sensors = <&bcl_soc>; trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + socd_trip:socd-trip { temperature = <90>; hysteresis = <0>; diff --git a/qcom/pm6125.dtsi b/qcom/pm6125.dtsi index 486d0063..bfcf95e2 100644 --- a/qcom/pm6125.dtsi +++ b/qcom/pm6125.dtsi @@ -71,12 +71,6 @@ qcom,pre-scaling = <1 3>; }; - vcoin { - reg = ; - label = "vcoin"; - qcom,pre-scaling = <1 3>; - }; - xo_therm { reg = ; label = "xo_therm"; @@ -87,10 +81,10 @@ }; pm6125_adc_tm: adc_tm@3500 { - compatible = "qcom,adc-tm5"; + compatible = "qcom,spmi-adc-tm5"; reg = <0x3500>; interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "thr-int-en"; + interrupt-names = "pm-adc-tm5"; #address-cells = <1>; #size-cells = <0>; #thermal-sensor-cells = <1>; diff --git a/qcom/pm7250b.dtsi b/qcom/pm7250b.dtsi index 4ed03d3b..e8a39c45 100644 --- a/qcom/pm7250b.dtsi +++ b/qcom/pm7250b.dtsi @@ -382,10 +382,10 @@ }; pm7250b_adc_tm: adc_tm@3500 { - compatible = "qcom,adc-tm5"; + compatible = "qcom,spmi-adc-tm5"; reg = <0x3500>; interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "thr-int-en"; + interrupt-names = "pm-adc-tm5"; #address-cells = <1>; #size-cells = <0>; #thermal-sensor-cells = <1>; diff --git a/qcom/pm8150-vm.dtsi b/qcom/pm8150-vm.dtsi new file mode 100644 index 00000000..0e8d9700 --- /dev/null +++ b/qcom/pm8150-vm.dtsi @@ -0,0 +1,62 @@ +#include +#include +#include +#include + +&spmi_bus { + qcom,pm8150@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8150_gpios: pinctrl@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm8150_rtc: qcom,pm8150_rtc { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_LEVEL_HIGH>; + qcom,disable-alarm-wakeup; + }; + }; +}; + +&pm8150_gpios { + key_home { + key_home_default: key_home_default { + pins = "gpio1"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; + + storage_sd_detect { + storage_cd_default: storage_cd_default { + pins = "gpio4"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; + + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <1>; + }; + }; +}; diff --git a/qcom/pm8775.dtsi b/qcom/pm8775.dtsi new file mode 100644 index 00000000..8f6caf84 --- /dev/null +++ b/qcom/pm8775.dtsi @@ -0,0 +1,233 @@ +#include +#include +#include +#include +#include + + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + pm8775_1: qcom,pm8775@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8775_1_tz: qcom,temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x0 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pon_pbs@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + qcom,system-reset; + qcom,store-hard-reset-reason; + }; + + pon_hlos@1200 { + compatible = "qcom,qpnp-power-on"; + reg = <0x1200>, <0x800>; + reg-names = "pon_hlos", "pon_pbs"; + interrupts = <0x0 0x12 0x7 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x6 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "kpdpwr", "resin"; + qcom,kpdpwr-sw-debounce; + + qcom,pon_1 { + qcom,pon-type = ; + linux,code = ; + }; + + qcom,pon_2 { + qcom,pon-type = ; + linux,code = ; + }; + }; + + pm8775_1_clkdiv: clock-controller@5700 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5700>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm8775_1_div_clk1", + "pm8775_1_div_clk2"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm8775_1_rtc: qcom,pm8775_1_rtc { + compatible = "qcom,pmk8350-rtc"; + reg = <0x6100>, <0x6200>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x62 0x1 IRQ_TYPE_NONE>; + }; + + pm8775_1_gpios: pinctrl@8800 { + compatible = "qcom,pm8775-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm8775_1_sdam_2: sdam@7100 { + compatible = "qcom,spmi-sdam"; + reg = <0x7100>; + #address-cells = <1>; + #size-cells = <1>; + }; + + pm8775_1_sdam_5: sdam@7400 { + compatible = "qcom,spmi-sdam"; + reg = <0x7400>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; + + /* below definitions are for the second instance of pm8775 */ + pm8775_2: qcom,pm8775@2 { + compatible = "qcom,spmi-pmic"; + reg = <2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8775_2_tz: qcom,temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pon_pbs@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + }; + + pon_hlos@1200 { + compatible = "qcom,qpnp-power-on"; + reg = <0x1200>, <0x800>; + reg-names = "pon_hlos", "pon_pbs"; + }; + + pm8775_2_clkdiv: clock-controller@5700 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5700>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm8775_2_div_clk1", + "pm8775_2_div_clk2"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm8775_2_gpios: pinctrl@8800 { + compatible = "qcom,pm8775-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + /* below definitions are for the third instance of pm8775 */ + pm8775_3: qcom,pm8775@4 { + compatible = "qcom,spmi-pmic"; + reg = <4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8775_3_tz: qcom,temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pon_pbs@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + }; + + pon_hlos@1200 { + compatible = "qcom,qpnp-power-on"; + reg = <0x1200>, <0x800>; + reg-names = "pon_hlos", "pon_pbs"; + }; + + pm8775_3_clkdiv: clock-controller@5700 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5700>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm8775_3_div_clk1", + "pm8775_3_div_clk2"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm8775_3_gpios: pinctrl@8800 { + compatible = "qcom,pm8775-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + /* below definitions are for the fourth instance of pm8775 */ + pm8775_4: qcom,pm8775@6 { + compatible = "qcom,spmi-pmic"; + reg = <6 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8775_4_tz: qcom,temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pon_pbs@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + }; + + pon_hlos@1200 { + compatible = "qcom,qpnp-power-on"; + reg = <0x1200>, <0x800>; + reg-names = "pon_hlos", "pon_pbs"; + }; + + pm8775_4_clkdiv: clock-controller@5700 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5700>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm8775_4_div_clk1", + "pm8775_4_div_clk2"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm8775_4_gpios: pinctrl@8800 { + compatible = "qcom,pm8775-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/qcom/quin-vm-common.dtsi b/qcom/quin-vm-common.dtsi index 55b31f2d..ba8d6096 100644 --- a/qcom/quin-vm-common.dtsi +++ b/qcom/quin-vm-common.dtsi @@ -22,7 +22,7 @@ #size-cells = <2>; ranges; - linux,cma { + system_cma: linux,cma { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x0 0x0 0xffffffff>; reusable; @@ -61,6 +61,19 @@ ranges = <0x0 0x0 0x0 0xffffffff>; compatible = "simple-bus"; + wdog: qcom,wdt@17c10000 { + compatible = "qcom,msm-watchdog"; + reg = <0x17c10000 0x1000>; + reg-names = "wdt-base"; + interrupts = , + ; + }; + + vm_restart: restart { + compatible = "qcom,vm-restart"; + status = "ok"; + }; + intc: vgic@0 { qvm,vdev = "gic"; #interrupt-cells = <3>; @@ -83,6 +96,95 @@ }; }; + hab: qcom,hab { + compatible = "qcom,hab"; + vmid = <2>; + + mmidgrp100: mmidgrp100 { + grp-start-id = <100>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp200: mmidgrp200 { + grp-start-id = <200>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp300: mmidgrp300 { + grp-start-id = <300>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp400: mmidgrp400 { + grp-start-id = <400>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp500: mmidgrp500 { + grp-start-id = <500>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp600: mmidgrp600 { + grp-start-id = <600>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp700: mmidgrp700 { + grp-start-id = <700>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp800: mmidgrp800 { + grp-start-id = <800>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp900: mmidgrp900 { + grp-start-id = <900>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp1000: mmidgrp1000 { + grp-start-id = <1000>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp1100: mmidgrp1100 { + grp-start-id = <1100>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp1200: mmidgrp1200 { + grp-start-id = <1200>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp1400: mmidgrp1400 { + grp-start-id = <1400>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp1500: mmidgrp1500 { + grp-start-id = <1500>; + role = "fe"; + remote-vmids = <0>; + }; + }; + qcom,msm-imem@14680000 { compatible = "qcom,msm-imem"; reg = <0x14680000 0x1000>; @@ -101,5 +203,18 @@ reg = <0xc221000 0x1000>; clock-frequency = <32768>; }; + + spmi_bus: virtio-spmi@1c800000 { + compatible = "virtio,mmio"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1c800000 0x1100>; + interrupt-names = "periph_irq"; + interrupts = ; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + status = "okay"; + }; }; diff --git a/qcom/sa410m-dma-heap.dtsi b/qcom/sa410m-dma-heap.dtsi new file mode 100644 index 00000000..527e869e --- /dev/null +++ b/qcom/sa410m-dma-heap.dtsi @@ -0,0 +1,26 @@ + +#include + +&soc { + qcom,dma-heaps { + compatible = "qcom,dma-heaps"; + + qcom,qseecom { + qcom,dma-heap-name = "qcom,qseecom"; + qcom,dma-heap-type = ; + memory-region = <&qseecom_mem>; + }; + + qcom,qseecom_ta { + qcom,dma-heap-name = "qcom,qseecom-ta"; + qcom,dma-heap-type = ; + memory-region = <&qseecom_ta_mem>; + }; + + qcom,user_contig { + qcom,dma-heap-name = "qcom,user-contig"; + qcom,dma-heap-type = ; + memory-region = <&user_contig_mem>; + }; + }; +}; diff --git a/qcom/sa410m-pinctrl.dtsi b/qcom/sa410m-pinctrl.dtsi index db93d342..ce0b7470 100644 --- a/qcom/sa410m-pinctrl.dtsi +++ b/qcom/sa410m-pinctrl.dtsi @@ -109,6 +109,112 @@ }; }; + qupv3_se0_4uart_pins: qupv3_se0_4uart_pins { + qupv3_se0_default_cts: qupv3_se0_default_cts { + mux { + pins = "gpio0"; + function = "gpio"; + }; + + config { + pins = "gpio0"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se0_default_rts: qupv3_se0_default_rts { + mux { + pins = "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio1"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se0_default_tx: qupv3_se0_default_tx { + mux { + pins = "gpio2"; + function = "gpio"; + }; + + config { + pins = "gpio2"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_default_rx: qupv3_se0_default_rx { + mux { + pins = "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio3"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se0_cts: qupv3_se0_cts { + mux { + pins = "gpio0"; + function = "qup0_se0_l0"; + }; + + config { + pins = "gpio0"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se0_rts: qupv3_se0_rts { + mux { + pins = "gpio1"; + function = "qup0_se0_l1"; + }; + + config { + pins = "gpio1"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se0_tx: qupv3_se0_tx { + mux { + pins = "gpio2"; + function = "qup0_se0_l2"; + }; + + config { + pins = "gpio2"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_rx: qupv3_se0_rx { + mux { + pins = "gpio3"; + function = "qup0_se0_l3"; + }; + + config { + pins = "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { qupv3_se1_i2c_sda_active: qupv3_se1_i2c_sda_active { mux { diff --git a/qcom/sa410m-qupv3.dtsi b/qcom/sa410m-qupv3.dtsi index d96903a1..cf6bfdad 100644 --- a/qcom/sa410m-qupv3.dtsi +++ b/qcom/sa410m-qupv3.dtsi @@ -71,8 +71,8 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, - <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + <&bimc_noc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&sys_noc MASTER_QUP_0 &bimc_noc SLAVE_EBI_CH0>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>; pinctrl-1 = <&qupv3_se0_i2c_sleep>; @@ -94,8 +94,8 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, - <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + <&bimc_noc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&sys_noc MASTER_QUP_0 &bimc_noc SLAVE_EBI_CH0>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se0_spi_mosi_active>, <&qupv3_se0_spi_miso_active>, <&qupv3_se0_spi_clk_active>, <&qupv3_se0_spi_cs_active>; @@ -117,8 +117,8 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, - <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + <&bimc_noc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&sys_noc MASTER_QUP_0 &bimc_noc SLAVE_EBI_CH0>; pinctrl-names = "default", "active", "sleep", "shutdown"; pinctrl-0 = <&qupv3_se0_default_cts>, <&qupv3_se0_default_rts>, <&qupv3_se0_default_tx>, <&qupv3_se0_default_rx>; @@ -142,8 +142,8 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, - <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + <&bimc_noc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&sys_noc MASTER_QUP_0 &bimc_noc SLAVE_EBI_CH0>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se1_i2c_sda_active>, <&qupv3_se1_i2c_scl_active>; pinctrl-1 = <&qupv3_se1_i2c_sleep>; @@ -165,8 +165,8 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, - <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + <&bimc_noc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&sys_noc MASTER_QUP_0 &bimc_noc SLAVE_EBI_CH0>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se1_spi_mosi_active>, <&qupv3_se1_spi_miso_active>, <&qupv3_se1_spi_clk_active>, <&qupv3_se1_spi_cs_active>; @@ -189,8 +189,8 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, - <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + <&bimc_noc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&sys_noc MASTER_QUP_0 &bimc_noc SLAVE_EBI_CH0>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se2_i2c_sda_active>, <&qupv3_se2_i2c_scl_active>; pinctrl-1 = <&qupv3_se2_i2c_sleep>; @@ -212,8 +212,8 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, - <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + <&bimc_noc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&sys_noc MASTER_QUP_0 &bimc_noc SLAVE_EBI_CH0>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se2_spi_mosi_active>, <&qupv3_se2_spi_miso_active>, <&qupv3_se2_spi_clk_active>, <&qupv3_se2_spi_cs_active>; @@ -236,8 +236,8 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, - <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + <&bimc_noc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&sys_noc MASTER_QUP_0 &bimc_noc SLAVE_EBI_CH0>; pinctrl-names = "default", "active", "sleep", "shutdown"; pinctrl-0 = <&qupv3_se3_default_cts>, <&qupv3_se3_default_rts>, <&qupv3_se3_default_tx>, <&qupv3_se3_default_rx>; @@ -262,8 +262,8 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, - <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + <&bimc_noc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&sys_noc MASTER_QUP_0 &bimc_noc SLAVE_EBI_CH0>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se5_i2c_sda_active>, <&qupv3_se5_i2c_scl_active>; pinctrl-1 = <&qupv3_se5_i2c_sleep>; @@ -285,8 +285,8 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, - <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + <&bimc_noc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&sys_noc MASTER_QUP_0 &bimc_noc SLAVE_EBI_CH0>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se5_spi_mosi_active>, <&qupv3_se5_spi_miso_active>, <&qupv3_se5_spi_clk_active>, <&qupv3_se5_spi_cs_active>; diff --git a/qcom/sa410m.dtsi b/qcom/sa410m.dtsi index cdbe4f95..bd53a80f 100644 --- a/qcom/sa410m.dtsi +++ b/qcom/sa410m.dtsi @@ -291,6 +291,14 @@ clock-frequency = <19200000>; }; + qcom_tzlog: tz-log@c125720 { + compatible = "qcom,tz-log"; + reg = <0xc125720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + }; + memtimer: timer@f120000 { #address-cells = <1>; #size-cells = <1>; @@ -386,6 +394,20 @@ clock-output-names = "chip_sleep_clk"; #clock-cells = <0>; }; + + pcie_0_pipe_clk: pcie_0_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; + }; + + usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + #clock-cells = <0>; + }; }; rpmcc: clock-controller { @@ -453,6 +475,11 @@ }; thermal_zones: thermal-zones { }; + + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; }; #include "sa410m-stub-regulators.dtsi" @@ -460,28 +487,12 @@ #include "scuba-thermal.dtsi" &thermal_zones { - gpu { - trips { - gpu-cxip-trip { - temperature = <105000>; - }; - - gpu-trip { - temperature = <105000>; - }; - - gpu-cx-mon { - temperature = <115000>; - }; - }; - - cooling-maps { - /delete-node/ gpu_cdev; - /delete-node/ gpu-cx-cdev0; - }; + wlan { + thermal-sensors = <&tsens0 1>; }; cpuss-0 { + thermal-sensors = <&tsens0 2>; trips { cpu-0-2-config { temperature = <115000>; @@ -490,6 +501,7 @@ }; cpuss-1 { + thermal-sensors = <&tsens0 3>; trips { cpu-1-3-configs { temperature = <115000>; @@ -498,6 +510,7 @@ }; mdm-0 { + thermal-sensors = <&tsens0 4>; trips { mdm0-cx-mon { temperature = <105000>; @@ -526,6 +539,7 @@ }; mdm-1 { + thermal-sensors = <&tsens0 5>; trips { mdm1-cx-mon { temperature = <105000>; @@ -552,12 +566,24 @@ }; }; }; + + video { + thermal-sensors = <&tsens0 6>; + }; + + hm-center { + thermal-sensors = <&tsens0 7>; + }; + + /delete-node/ gpu; + /delete-node/ camera; }; #include "msm-arm-smmu-sa410m.dtsi" #include "sa410m-pinctrl.dtsi" #include "monaco-gdsc.dtsi" #include "sa410m-qupv3.dtsi" +#include "sa410m-dma-heap.dtsi" &gcc_emac0_gdsc { status = "ok"; diff --git a/qcom/sa8155-adp-common.dtsi b/qcom/sa8155-adp-common.dtsi index ce71d404..e5923968 100644 --- a/qcom/sa8155-adp-common.dtsi +++ b/qcom/sa8155-adp-common.dtsi @@ -80,3 +80,21 @@ status = "ok"; }; + +&qupv3_se10_i2c { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + asm330@6a { + compatible = "st,asm330lhh"; + reg = <0x6a>; + vio-supply = <&pm8150_2_l7>; + vdd-supply = <&pm8150_2_l16>; + interrupt-parent = <&tlmm>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sensor_int1_default + &sensor_int2_default>; + }; +}; diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi index 5e8d65ae..e73d66f4 100644 --- a/qcom/sa8155-vm.dtsi +++ b/qcom/sa8155-vm.dtsi @@ -1,4 +1,5 @@ #include "quin-vm-common.dtsi" +#include "pm8150-vm.dtsi" / { model = "Qualcomm Technologies, Inc. SA8155 Guest Virtual Machine"; @@ -130,6 +131,109 @@ }; }; +&soc { + apps_smmu: apps-smmu@0x15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x100000>, + <0x15182000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,disable-atos; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + dma_dev@0x0 { + compatible = "qcom,iommu-dma"; + memory-region = <&system_cma>; + }; +}; + #include "sm8150-pinctrl.dtsi" &tlmm { diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi index a14fd8f9..5ce5c715 100644 --- a/qcom/sa8155.dtsi +++ b/qcom/sa8155.dtsi @@ -222,7 +222,7 @@ hsi2s: qcom,hsi2s { }; ethqos_hw: qcom,ethernet@00020000 { - compatible = "qcom,stmmac-ethqos"; + compatible = "qcom,stmmac-ethqos", "snps,dwmac-4.20a"; qcom,arm-smmu; reg = <0x20000 0x10000>, <0x36000 0x100>, @@ -291,7 +291,6 @@ hsi2s: qcom,hsi2s { snps,reset-delays-us = <0 11000 70000>; phy-mode = "rgmii"; eth-c22-mdio-probe; - status = "disabled"; ethqos_emb_smmu: ethqos_emb_smmu { compatible = "qcom,emac-smmu-embedded"; diff --git a/qcom/sa8195p.dtsi b/qcom/sa8195p.dtsi index 7244db28..b40320fd 100644 --- a/qcom/sa8195p.dtsi +++ b/qcom/sa8195p.dtsi @@ -50,6 +50,7 @@ vcc-max-microamp = <750000>; vccq-max-microamp = <750000>; vccq2-max-microamp = <750000>; + qcom,disable-lpm; qcom,vddp-ref-clk-supply = <&pm8195_2_l5>; qcom,vddp-ref-clk-max-microamp = <100>; diff --git a/qcom/scuba_auto-dma-heap.dtsi b/qcom/scuba_auto-dma-heap.dtsi new file mode 100644 index 00000000..527e869e --- /dev/null +++ b/qcom/scuba_auto-dma-heap.dtsi @@ -0,0 +1,26 @@ + +#include + +&soc { + qcom,dma-heaps { + compatible = "qcom,dma-heaps"; + + qcom,qseecom { + qcom,dma-heap-name = "qcom,qseecom"; + qcom,dma-heap-type = ; + memory-region = <&qseecom_mem>; + }; + + qcom,qseecom_ta { + qcom,dma-heap-name = "qcom,qseecom-ta"; + qcom,dma-heap-type = ; + memory-region = <&qseecom_ta_mem>; + }; + + qcom,user_contig { + qcom,dma-heap-name = "qcom,user-contig"; + qcom,dma-heap-type = ; + memory-region = <&user_contig_mem>; + }; + }; +}; diff --git a/qcom/scuba_auto-idp.dts b/qcom/scuba_auto-idp-overlay.dts similarity index 89% rename from qcom/scuba_auto-idp.dts rename to qcom/scuba_auto-idp-overlay.dts index b2085f9c..14b319c6 100644 --- a/qcom/scuba_auto-idp.dts +++ b/qcom/scuba_auto-idp-overlay.dts @@ -1,6 +1,6 @@ /dts-v1/; +/plugin/; -#include "scuba_auto.dtsi" #include "scuba_auto-idp.dtsi" / { diff --git a/qcom/scuba_auto-qrd.dts b/qcom/scuba_auto-qrd-overlay.dts similarity index 88% rename from qcom/scuba_auto-qrd.dts rename to qcom/scuba_auto-qrd-overlay.dts index 195a2fad..e38a0032 100644 --- a/qcom/scuba_auto-qrd.dts +++ b/qcom/scuba_auto-qrd-overlay.dts @@ -1,7 +1,7 @@ /dts-v1/; +/plugin/; #include "scuba_auto.dtsi" -#include "scuba_auto-qrd.dtsi" / { model = "Qualcomm Technologies, Inc. SCUBA AUTO QRD"; diff --git a/qcom/scuba_auto.dts b/qcom/scuba_auto.dts new file mode 100644 index 00000000..574e96eb --- /dev/null +++ b/qcom/scuba_auto.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "scuba_auto.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SCUBA AUTO"; + compatible = "qcom,sa410m"; + qcom,msm-id = <441 0x10000>, <471 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/qcom/scuba_auto.dtsi b/qcom/scuba_auto.dtsi index 794d734b..6ff28f5a 100644 --- a/qcom/scuba_auto.dtsi +++ b/qcom/scuba_auto.dtsi @@ -20,7 +20,9 @@ reserved_memory: reserved-memory { }; - chosen: chosen { }; + chosen: chosen { + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + }; mem-offline { compatible = "qcom,mem-offline"; @@ -144,9 +146,9 @@ reg = <0x0 0x45600000 0x0 0x700000>; }; - xbl_aop_mem: xbl_aop_mem@45e00000 { + xbl_aop_mem: xbl_aop_mem@45d00000 { no-map; - reg = <0x0 0x45e00000 0x0 0x100000>; + reg = <0x0 0x45d00000 0x0 0x200000>; }; sec_apps_mem: sec_apps_region@45fff000 { @@ -184,9 +186,14 @@ reg = <0x0 0x52910000 0x0 0x5000>; }; - removed_region: removed_region@60000000 { + tz_stat: tz_stat@53200000 { no-map; - reg = <0x0 0x60000000 0x0 0x3900000>; + reg = <0x0 0x53200000 0x0 0x100000>; + }; + + pimem_vault: pimem_vault@53300000 { + no-map; + reg = <0x0 0x53300000 0x0 0x1500000>; }; adsp_mem: adsp_region { @@ -204,29 +211,6 @@ size = <0 0x800000>; }; - secure_display_memory: secure_display_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0 0x00000000 0 0xffffffff>; - reusable; - alignment = <0 0x400000>; - size = <0 0x5c00000>; - }; - - cont_splash_memory: cont_splash_region@5c000000 { - reg = <0x0 0x5c000000 0x0 0x00f00000>; - label = "cont_splash_region"; - }; - - dfps_data_memory: dfps_data_region@5cf00000 { - reg = <0x0 0x5cf00000 0x0 0x0100000>; - label = "dfps_data_region"; - }; - - disp_rdump_memory: disp_rdump_region@5c000000 { - reg = <0x0 0x5c000000 0x0 0x00f00000>; - label = "disp_rdump_region"; - }; - user_contig_mem: user_contig_region { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; @@ -240,7 +224,7 @@ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; reusable; alignment = <0x0 0x400000>; - size = <0x0 0x1400000>; + size = <0x0 0x700000>; }; qseecom_ta_mem: qseecom_ta_region { @@ -248,7 +232,7 @@ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; reusable; alignment = <0x0 0x400000>; - size = <0x0 0x1000000>; + size = <0x0 0x400000>; }; memshare_mem: memshare_region { @@ -259,15 +243,8 @@ size = <0x0 0x800000>; }; - dump_mem: mem_dump_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - size = <0 0x800000>; - }; - /* global autoconfigured region for contiguous allocations */ - system_cma: linux,cma { + system_cma:linux,cma { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; reusable; @@ -276,10 +253,6 @@ linux,cma-default; }; - smem_mem: smem@46000000 { - no-map; - reg = <0x0 0x46000000 0x0 0x200000>; - }; }; &soc { @@ -317,6 +290,14 @@ clock-frequency = <19200000>; }; + qcom_tzlog: tz-log@c125720 { + compatible = "qcom,tz-log"; + reg = <0xc125720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + }; + memtimer: timer@f120000 { #address-cells = <1>; #size-cells = <1>; @@ -626,60 +607,10 @@ smem: qcom,smem { compatible = "qcom,smem"; - memory-region = <&smem_mem>; + memory-region = <&smem_region>; hwlocks = <&tcsr_mutex 3>; }; - qcom,glink { - compatible = "qcom,glink"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - glink_modem: modem { - qcom,remote-pid = <1>; - transport = "smem"; - mboxes = <&apcs_glb 12>; - mbox-names = "mpss_smem"; - interrupts = ; - - label = "modem"; - qcom,glink-label = "mpss"; - - qcom,modem_qrtr { - qcom,glink-channels = "IPCRTR"; - qcom,low-latency; - qcom,intents = <0x800 5 - 0x2000 3 - 0x4400 2>; - }; - }; - - glink_adsp: adsp { - qcom,remote-pid = <2>; - transport = "smem"; - mboxes = <&apcs_glb 8>; - mbox-names = "adsp_smem"; - interrupts = ; - - label = "adsp"; - qcom,glink-label = "lpass"; - - qcom,adsp_qrtr { - qcom,glink-channels = "IPCRTR"; - qcom,low-latency; - qcom,intents = <0x800 5 - 0x2000 3 - 0x4400 2>; - }; - - qcom,apr_tal_rpmsg { - qcom,glink-channels = "apr_audio_svc"; - qcom,intents = <0x200 20>; - }; - }; - }; - qcom,glinkpkt { compatible = "qcom,glinkpkt"; @@ -798,6 +729,25 @@ /* Outputs to mss */ qcom,smem-states = <&modem_smp2p_out 0>; qcom,smem-state-names = "stop"; + + glink_modem: glink-edge { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&apcs_glb 12>; + mbox-names = "mpss_smem"; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + }; }; @@ -834,6 +784,30 @@ /* Outputs to lpass */ qcom,smem-states = <&adsp_smp2p_out 0>; qcom,smem-state-names = "stop"; + + glink_adsp: glink-edge { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&apcs_glb 8>; + mbox-names = "adsp_smem"; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,apr_tal_rpmsg { + qcom,glink-channels = "apr_audio_svc"; + qcom,intents = <0x200 20>; + }; + }; }; qcom,ipa_fws { @@ -1158,6 +1132,7 @@ #include "msm-arm-smmu-scuba_auto.dtsi" #include "scuba_auto-qupv3.dtsi" +#include "scuba_auto-dma-heap.dtsi" &sdhc_1 { vdd-supply = <&L20A>; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index f3f17c9e..8551143c 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -24,6 +24,7 @@ #address-cells = <2>; #size-cells = <2>; memory { device_type = "memory"; reg = <0 0 0 0>; }; + ddr-regions { }; aliases { ufshc1 = &ufshc_mem; /* Embedded UFS slot */ @@ -1593,7 +1594,7 @@ compatible = "qcom,ufshc"; reg = <0x1d84000 0x3000>, <0x1d90000 0x8000>; - reg-names = "ufs_mem", "ice"; + reg-names = "ufs_mem", "ufs_ice"; interrupts = ; phys = <&ufsphy_mem>; phy-names = "ufsphy"; diff --git a/qcom/sdxbaagha-rumi.dts b/qcom/sdxbaagha-rumi.dts index 475e673a..695024cd 100644 --- a/qcom/sdxbaagha-rumi.dts +++ b/qcom/sdxbaagha-rumi.dts @@ -7,5 +7,5 @@ model = "Qualcomm Technologies, Inc. SDXBAAGHA RUMI"; compatible = "qcom,sdxbaagha-rumi", "qcom,sdxbaagha", "qcom,rumi"; - qcom,board-id = <0x0F 0>; + qcom,board-id = <0x0F 0x400>; }; diff --git a/qcom/sdxbaagha-rumi.dtsi b/qcom/sdxbaagha-rumi.dtsi index 84c43d30..e2f47e70 100644 --- a/qcom/sdxbaagha-rumi.dtsi +++ b/qcom/sdxbaagha-rumi.dtsi @@ -18,8 +18,40 @@ qcom,no-l0s-supported; qcom,no-aux-clk-sync; }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + usb_emuphy: phy@a71c000 { + compatible = "qcom,usb-emu-phy"; + reg = <0xA71C000 0x9500>; + + qcom,emu-init-seq = <0xfff0 0x4 + 0xfff3 0x4 + 0xfff0 0x4 + 0x100000 0x20 + 0x0 0x20 + 0x1e0 0x20 + 0x100000 0x3c + 0x0 0x3c + 0x4 0x3c + 0x0 0x4 + 0x9 0x14>; + }; }; &qupv3_se3_2uart { qcom,rumi_platform; }; + +&gcc { + clocks = <&bi_tcxo>, <&pcie_pipe_clk>, <&sleep_clk>; +}; + +&usb0 { + dwc3@a600000 { + usb-phy = <&usb_emuphy>, <&usb_nop_phy>; + dr_mode = "peripheral"; + }; +}; diff --git a/qcom/sdxbaagha-usb.dtsi b/qcom/sdxbaagha-usb.dtsi new file mode 100644 index 00000000..14d8e38b --- /dev/null +++ b/qcom/sdxbaagha-usb.dtsi @@ -0,0 +1,46 @@ +#include + +&soc { + usb0: hsusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa600000 0x100000>; + reg-names = "core_base"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + USB3_GDSC-supply = <&gcc_usb20_gdsc>; + + clocks = <&gcc GCC_USB20_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB_SF_AXI_CLK>, + <&gcc GCC_USB20_SLEEP_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>; + + clock-names = "core_clk", "iface_clk", "sleep_clk", "utmi_clk"; + + resets = <&gcc GCC_USB20_BCR>; + reset-names = "core_reset"; + + interrupts = ; + interrupt-names = "pwr_event_irq"; + + qcom,core-clk-rate = <60000000>; + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0xa600000 0xd93c>; + + interrupts = ; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + maximum-speed = "high-speed"; + dr_mode = "otg"; + usb-role-switch; + }; + }; +}; diff --git a/qcom/sdxbaagha.dtsi b/qcom/sdxbaagha.dtsi index 2cffd768..e347f5a7 100644 --- a/qcom/sdxbaagha.dtsi +++ b/qcom/sdxbaagha.dtsi @@ -2,6 +2,8 @@ #include #include #include +#include +#include / { #address-cells = <1>; @@ -383,28 +385,47 @@ }; gcc: clock-controller@80000 { - compatible = "qcom,dummycc"; - clock-output-names = "gcc_clocks"; + compatible = "qcom,sdxbaagha-gcc", "syscon"; + reg = <0x80000 0x1f4200>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mxa-supply = <&VDD_MXA_LEVEL>; + vdd_mxc-supply = <&VDD_MXC_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&pcie_pipe_clk>, + <&sleep_clk>; + clock-names = "bi_tcxo", + "pcie_pipe_clk", + "sleep_clk"; #clock-cells = <1>; #reset-cells = <1>; }; /* GCC GDSCs */ gcc_emac0_gdsc: qcom,gdsc@f1004 { - compatible = "qcom,stub-regulator"; + compatible = "qcom,gdsc"; + reg = <0xf1004 0x4>; regulator-name = "gcc_emac0_gdsc"; + parent-supply = <&VDD_MXC_LEVEL>; + qcom,retain-regs; qcom,support-hw-trigger; }; gcc_pcie_gdsc: qcom,gdsc@d3004 { - compatible = "qcom,stub-regulator"; + compatible = "qcom,gdsc"; + reg = <0xd3004 0x4>; regulator-name = "gcc_pcie_gdsc"; + parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; qcom,support-hw-trigger; }; gcc_usb20_gdsc: qcom,gdsc@a7004 { - compatible = "qcom,stub-regulator"; + compatible = "qcom,gdsc"; + reg = <0xa7004 0x4>; regulator-name = "gcc_usb20_gdsc"; + parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; }; ipcc_mproc: qcom,ipcc@408000 { @@ -415,6 +436,54 @@ #interrupt-cells = <3>; #mbox-cells = <2>; }; + + mc_virt: interconnect@0 { + compatible = "qcom,sdxbaagha-mc_virt"; + #interconnect-cells = <1>; + qcom,stub; + qcom,skip-qos; + }; + + aggre_noc: interconnect@1640000 { + reg = <0x1640000 0x33400>; + compatible = "qcom,sdxbaagha-aggre_noc"; + #interconnect-cells = <1>; + qcom,stub; + qcom,skip-qos; + }; + + cnoc_main: interconnect@1580000 { + reg = <0x01580000 0x19200>; + compatible = "qcom,sdxbaagha-cnoc_main"; + #interconnect-cells = <1>; + qcom,stub; + qcom,skip-qos; + }; + + dc_noc_dch: interconnect@190E0000 { + reg = <0x190E0000 0x5080>; + compatible = "qcom,sdxbaagha-dc_noc_dch"; + #interconnect-cells = <1>; + qcom,stub; + qcom,skip-qos; + }; + + mem_noc: interconnect@19100000 { + reg = <0x19100000 0x2D080>; + compatible = "qcom,sdxbaagha-mem_noc"; + #interconnect-cells = <1>; + qcom,stub; + qcom,skip-qos; + }; + + snoc: interconnect@15C0000 { + reg = <0x15C0000 0x14080>; + compatible = "qcom,sdxbaagha-snoc"; + #interconnect-cells = <1>; + qcom,stub; + qcom,skip-qos; + }; + }; #include "sdxbaagha-pinctrl.dtsi" @@ -422,6 +491,7 @@ #include "msm-arm-smmu-sdxbaagha.dtsi" #include "sdxbaagha-pcie.dtsi" #include "sdxbaagha-qupv3.dtsi" +#include "sdxbaagha-usb.dtsi" &qupv3_se3_2uart { status = "ok"; diff --git a/qcom/sdxpinn-coresight.dtsi b/qcom/sdxpinn-coresight.dtsi index 266bb98a..542344b9 100644 --- a/qcom/sdxpinn-coresight.dtsi +++ b/qcom/sdxpinn-coresight.dtsi @@ -217,6 +217,7 @@ atid = <78>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + status = "disabled"; out-ports { port { @@ -473,6 +474,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,cmb-msr-skip; + status = "disabled"; out-ports { port { @@ -495,6 +497,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,cmb-msr-skip; + status = "disabled"; out-ports { port { @@ -516,6 +519,7 @@ atid = <78>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + status = "disabled"; out-ports { port { @@ -599,10 +603,11 @@ reg-names = "tpdm-base"; coresight-name = "coresight-tpdm-pcie-rscc"; - atid = <78>; + atid = <88>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,cmb-msr-skip; + status = "disabled"; out-ports { port { @@ -666,7 +671,7 @@ reg-names = "tpdm-base"; status = "disabled"; - atid = <67>; + atid = <87>; coresight-name = "coresight-tpdm-modem-rscc"; clocks = <&aoss_qmp>; @@ -742,6 +747,7 @@ coresight-name = "coresight-funnel-mvm"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + status = "disabled"; in-ports { @@ -1012,7 +1018,7 @@ qcom,tpda-atid = <67>; qcom,dsb-elem-size = <0 32>; - qcom,cmb-elem-size = <0 64>; + qcom,cmb-elem-size = <1 64>; coresight-name = "coresight-tpda-modem"; @@ -1058,9 +1064,8 @@ reg = <0x2480e000 0x1000>; reg-names = "tpda-base"; - qcom,tpda-atid = <67>; + qcom,tpda-atid = <87>; - qcom,dsb-elem-size = <0 32>; qcom,cmb-elem-size = <0 64>; coresight-name = "coresight-tpda-modem-rscc"; @@ -1099,10 +1104,9 @@ reg = <0x24c09000 0x1000>; reg-names = "tpda-base"; - qcom,tpda-atid = <67>; + qcom,tpda-atid = <88>; - qcom,dsb-elem-size = <0 32>; - qcom,cmb-elem-size = <0 64>; + qcom,cmb-elem-size = <0 8>; coresight-name = "coresight-tpda-pcie-rscc"; @@ -1247,7 +1251,7 @@ qcom,dsb-elem-size = <4 32>; qcom,cmb-elem-size = <0 32>, - <2 64>; + <3 64>; in-ports { @@ -1508,25 +1512,18 @@ qcom,tpda-atid = <78>; - qcom,dsb-elem-size = <0 32>, - <4 32>, - <5 32>, - <7 32>, + qcom,dsb-elem-size = <9 32>, + <11 32>, <15 32>, - <17 32>, <20 32>, <21 32>, - <25 32>, + <23 32>, <26 32>; - qcom,cmb-elem-size = <0 32>, - <7 32>, - <8 64>, - <13 64>, - <14 64>, - <16 32>, + qcom,cmb-elem-size = <5 32>, <19 32>, - <22 32>, - <25 64>, + <20 32>, + <23 64>, + <24 32>, <27 64>; in-ports { @@ -1905,7 +1902,7 @@ qcom,tpda-atid = <71>; - qcom,dsb-elem-size = <2 32>; + qcom,dsb-elem-size = <4 32>; qcom,cmb-elem-size = <0 64>, <1 64>, <2 64>, diff --git a/qcom/sdxpinn-pcie.dtsi b/qcom/sdxpinn-pcie.dtsi index a2b9f59e..e1d95457 100644 --- a/qcom/sdxpinn-pcie.dtsi +++ b/qcom/sdxpinn-pcie.dtsi @@ -76,8 +76,8 @@ RPMH_REGULATOR_LEVEL_NOM 100000000>; - //interconnect-names = "icc_path"; - //interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; + interconnect-names = "icc_path"; + interconnects = <&pcie_anoc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; clocks = <&gcc GCC_PCIE_PIPE_CLK>, <&rpmhcc RPMH_CXO_CLK>, @@ -108,9 +108,9 @@ reset-names = "pcie_core_reset", "pcie_phy_reset"; - //qcom,smmu-sid-base = <0x0800>; - //iommu-map = <0x0 &apps_smmu 0x0800 0x1>, - // <0x100 &apps_smmu 0x0801 0x1>; + qcom,smmu-sid-base = <0x0800>; + iommu-map = <0x0 &apps_smmu 0x0800 0x1>, + <0x100 &apps_smmu 0x0801 0x1>; qcom,aux-clk-freq = <20>; /* 19.2 MHz */ qcom,tpwr-on-scale = <1>; @@ -119,6 +119,177 @@ qcom,slv-addr-space-size = <0x4000000>; qcom,ep-latency = <10>; qcom,num-parf-testbus-sel = <0xb9>; + qcom,target-link-speed = <3>; + + qcom,pcie-phy-ver = <100>; + qcom,phy-status-offset = <0x1214>; + qcom,phy-status-bit = <7>; + qcom,phy-power-down-offset = <0x1240>; + qcom,phy-sequence = <0x1240 0x03 0x0 + 0x0030 0x1d 0x0 + 0x0034 0x03 0x0 + 0x0078 0x01 0x0 + 0x007c 0x00 0x0 + 0x0080 0x51 0x0 + 0x00ac 0x34 0x0 + 0x0208 0x0c 0x0 + 0x020c 0x0a 0x0 + 0x0218 0x04 0x0 + 0x0220 0x16 0x0 + 0x0234 0x00 0x0 + 0x029c 0x80 0x0 + 0x02a0 0x7c 0x0 + 0x02b4 0x05 0x0 + 0x02e8 0x0a 0x0 + 0x030c 0x0d 0x0 + 0x0320 0x0b 0x0 + 0x0348 0x1c 0x0 + 0x0388 0x20 0x0 + 0x0394 0x30 0x0 + 0x03dc 0x09 0x0 + 0x03f4 0x14 0x0 + 0x03f8 0xb3 0x0 + 0x03fc 0x58 0x0 + 0x0400 0x9a 0x0 + 0x0404 0x26 0x0 + 0x0408 0xb6 0x0 + 0x040c 0xee 0x0 + 0x0410 0xdb 0x0 + 0x0414 0xdb 0x0 + 0x0418 0xa0 0x0 + 0x041c 0xdf 0x0 + 0x0420 0x78 0x0 + 0x0424 0x76 0x0 + 0x0428 0xff 0x0 + 0x0830 0x1d 0x0 + 0x0834 0x03 0x0 + 0x0878 0x01 0x0 + 0x087c 0x00 0x0 + 0x0880 0x51 0x0 + 0x08ac 0x34 0x0 + 0x0a08 0x0c 0x0 + 0x0a0c 0x0a 0x0 + 0x0a18 0x04 0x0 + 0x0a20 0x16 0x0 + 0x0a34 0x00 0x0 + 0x0a9c 0x80 0x0 + 0x0aa0 0x7c 0x0 + 0x0ab4 0x05 0x0 + 0x0ae8 0x0a 0x0 + 0x0b0c 0x0d 0x0 + 0x0b20 0x0b 0x0 + 0x0b48 0x1c 0x0 + 0x0b88 0x20 0x0 + 0x0b94 0x30 0x0 + 0x0bdc 0x09 0x0 + 0x0bf4 0x14 0x0 + 0x0bf8 0xb3 0x0 + 0x0bfc 0x58 0x0 + 0x0c00 0x9a 0x0 + 0x0c04 0x26 0x0 + 0x0c08 0xb6 0x0 + 0x0c0c 0xee 0x0 + 0x0c10 0xdb 0x0 + 0x0c14 0xdb 0x0 + 0x0c18 0xa0 0x0 + 0x0c1c 0xdf 0x0 + 0x0c20 0x78 0x0 + 0x0c24 0x76 0x0 + 0x0c28 0xff 0x0 + 0x0ea0 0x01 0x0 + 0x0eb4 0x00 0x0 + 0x0ec4 0x00 0x0 + 0x0ec8 0x1f 0x0 + 0x0ed4 0x12 0x0 + 0x0ed8 0x12 0x0 + 0x0edc 0xdb 0x0 + 0x0ee0 0x9a 0x0 + 0x0ee4 0x38 0x0 + 0x0ee8 0xb6 0x0 + 0x0eec 0x64 0x0 + 0x0ef0 0x1f 0x0 + 0x0ef4 0x1f 0x0 + 0x0ef8 0x1f 0x0 + 0x0efc 0x1f 0x0 + 0x0f00 0x1f 0x0 + 0x0f04 0x1f 0x0 + 0x0f0c 0x1f 0x0 + 0x0f14 0x1f 0x0 + 0x0f1c 0x1f 0x0 + 0x0f28 0x5b 0x0 + 0x1000 0x97 0x0 + 0x1004 0x0c 0x0 + 0x1010 0x06 0x0 + 0x1014 0x16 0x0 + 0x1018 0x36 0x0 + 0x101c 0x04 0x0 + 0x1020 0x14 0x0 + 0x1024 0x34 0x0 + 0x1028 0xd0 0x0 + 0x1030 0x55 0x0 + 0x1034 0x55 0x0 + 0x1038 0x05 0x0 + 0x103c 0x12 0x0 + 0x1060 0xde 0x0 + 0x1064 0x07 0x0 + 0x1070 0x06 0x0 + 0x1074 0x16 0x0 + 0x1078 0x36 0x0 + 0x107c 0x0a 0x0 + 0x1080 0x0a 0x0 + 0x1084 0x1a 0x0 + 0x1088 0x82 0x0 + 0x1090 0x55 0x0 + 0x1094 0x55 0x0 + 0x1098 0x03 0x0 + 0x109c 0x00 0x0 + 0x10bc 0x0e 0x0 + 0x10c0 0x01 0x0 + 0x10cc 0x31 0x0 + 0x10d0 0x01 0x0 + 0x10d8 0x40 0x0 + 0x10dc 0x14 0x0 + 0x10e0 0x90 0x0 + 0x10e4 0x82 0x0 + 0x10f4 0x0f 0x0 + 0x1110 0x08 0x0 + 0x1120 0x46 0x0 + 0x1124 0x04 0x0 + 0x1140 0x14 0x0 + 0x1164 0x34 0x0 + 0x1170 0xa0 0x0 + 0x1174 0x06 0x0 + 0x1184 0x88 0x0 + 0x1188 0x14 0x0 + 0x1198 0x0f 0x0 + 0x1378 0x2e 0x0 + 0x1390 0xcc 0x0 + 0x13f8 0x00 0x0 + 0x13fc 0x22 0x0 + 0x141c 0xc1 0x0 + 0x129c 0x83 0x0 + 0x12a0 0x09 0x0 + 0x12a4 0xa2 0x0 + 0x1450 0x03 0x0 + 0x1490 0x00 0x0 + 0x14a0 0x16 0x0 + 0x1508 0x02 0x0 + 0x155c 0x2e 0x0 + 0x157c 0x03 0x0 + 0x1584 0x28 0x0 + 0x13dc 0x04 0x0 + 0x13e0 0x02 0x0 + 0x1418 0xc0 0x0 + 0x140c 0x1d 0x0 + 0x158c 0x0f 0x0 + 0x15ac 0xf2 0x0 + 0x15c0 0xf2 0x0 + 0x1828 0x00 0x0 + 0x1c28 0x00 0x0 + 0x1e24 0x00 0x0 + 0x1e28 0x00 0x0 + 0x1200 0x00 0x0 + 0x1244 0x03 0x0>; pcie0_rp: pcie0_rp { reg = <0 0 0 0 0>; @@ -212,8 +383,8 @@ RPMH_REGULATOR_LEVEL_LOW_SVS 100000000>; - //interconnect-names = "icc_path"; - //interconnects = <&system_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>; + interconnect-names = "icc_path"; + interconnects = <&pcie_anoc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>; clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&rpmhcc RPMH_CXO_CLK>, @@ -244,9 +415,9 @@ reset-names = "pcie_1_core_reset", "pcie_1_phy_reset"; - //qcom,smmu-sid-base = <0x0880>; - //iommu-map = <0x0 &apps_smmu 0x0880 0x1>, - // <0x100 &apps_smmu 0x0881 0x1>; + qcom,smmu-sid-base = <0x0880>; + iommu-map = <0x0 &apps_smmu 0x0880 0x1>, + <0x100 &apps_smmu 0x0881 0x1>; qcom,aux-clk-freq = <20>; /* 19.2 MHz */ qcom,tpwr-on-scale = <1>; @@ -256,6 +427,124 @@ qcom,ep-latency = <10>; qcom,num-parf-testbus-sel = <0xb9>; + qcom,pcie-phy-ver = <101>; + qcom,phy-status-offset = <0x214>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x240>; + qcom,phy-sequence = <0x0240 0x03 0x0 + 0x00c0 0x01 0x0 + 0x00cc 0x31 0x0 + 0x00d0 0x01 0x0 + 0x0060 0xff 0x0 + 0x0064 0x06 0x0 + 0x0000 0x4c 0x0 + 0x0004 0x06 0x0 + 0x00e0 0x90 0x0 + 0x00e4 0x82 0x0 + 0x00f4 0x07 0x0 + 0x0070 0x02 0x0 + 0x0010 0x02 0x0 + 0x0074 0x16 0x0 + 0x0014 0x16 0x0 + 0x0078 0x36 0x0 + 0x0018 0x36 0x0 + 0x0110 0x08 0x0 + 0x00bc 0x0e 0x0 + 0x0120 0x42 0x0 + 0x0080 0x0a 0x0 + 0x0084 0x1a 0x0 + 0x0020 0x14 0x0 + 0x0024 0x34 0x0 + 0x0088 0x82 0x0 + 0x0028 0x68 0x0 + 0x0090 0xab 0x0 + 0x0094 0xea 0x0 + 0x0098 0x02 0x0 + 0x0030 0xab 0x0 + 0x0034 0xaa 0x0 + 0x0038 0x02 0x0 + 0x0140 0x14 0x0 + 0x0164 0x34 0x0 + 0x003c 0x01 0x0 + 0x001c 0x04 0x0 + 0x0174 0x16 0x0 + 0x01bc 0x0f 0x0 + 0x0170 0xa0 0x0 + 0x11a4 0x38 0x0 + 0x10dc 0x11 0x0 + 0x1160 0xbf 0x0 + 0x1164 0xbf 0x0 + 0x1168 0xb7 0x0 + 0x116c 0xea 0x0 + 0x115c 0x3f 0x0 + 0x1174 0x5c 0x0 + 0x1178 0x9c 0x0 + 0x117c 0x1a 0x0 + 0x1180 0x89 0x0 + 0x1170 0xdc 0x0 + 0x1188 0x94 0x0 + 0x118c 0x5b 0x0 + 0x1190 0x1a 0x0 + 0x1194 0x89 0x0 + 0x10cc 0x00 0x0 + 0x1008 0x09 0x0 + 0x1014 0x05 0x0 + 0x104c 0x08 0x0 + 0x1050 0x08 0x0 + 0x10d8 0x0f 0x0 + 0x1118 0x1c 0x0 + 0x10f8 0x07 0x0 + 0x11f8 0x08 0x0 + 0x0e84 0x15 0x0 + 0x0e90 0x3f 0x0 + 0x0ee4 0x02 0x0 + 0x0e40 0x06 0x0 + 0x0e3c 0x18 0x0 + 0x19a4 0x38 0x0 + 0x18dc 0x11 0x0 + 0x1960 0xbf 0x0 + 0x1964 0xbf 0x0 + 0x1968 0xb7 0x0 + 0x196c 0xea 0x0 + 0x195c 0x3f 0x0 + 0x1974 0x5c 0x0 + 0x1978 0x9c 0x0 + 0x197c 0x1a 0x0 + 0x1980 0x89 0x0 + 0x1970 0xdc 0x0 + 0x1988 0x94 0x0 + 0x198c 0x5b 0x0 + 0x1990 0x1a 0x0 + 0x1994 0x89 0x0 + 0x18cc 0x00 0x0 + 0x1808 0x09 0x0 + 0x1814 0x05 0x0 + 0x184c 0x08 0x0 + 0x1850 0x08 0x0 + 0x18d8 0x0f 0x0 + 0x1918 0x1c 0x0 + 0x18f8 0x07 0x0 + 0x19f8 0x08 0x0 + 0x1684 0x15 0x0 + 0x1690 0x3f 0x0 + 0x16e4 0x02 0x0 + 0x1640 0x06 0x0 + 0x163c 0x18 0x0 + 0x02dc 0x05 0x0 + 0x0388 0x77 0x0 + 0x0398 0x0b 0x0 + 0x06a4 0x1e 0x0 + 0x03e0 0x0f 0x0 + 0x060c 0x1d 0x0 + 0x0614 0x07 0x0 + 0x0620 0xc1 0x0 + 0x0694 0x00 0x0 + 0x03d0 0x8c 0x0 + 0x1424 0x00 0x0 + 0x1428 0x00 0x0 + 0x0200 0x00 0x0 + 0x0244 0x03 0x0>; + pcie1_rp: pcie1_rp { reg = <0 0 0 0 0>; @@ -349,8 +638,8 @@ RPMH_REGULATOR_LEVEL_LOW_SVS 100000000>; - //interconnect-names = "icc_path"; - //interconnects = <&system_noc MASTER_PCIE_2 &mc_virt SLAVE_EBI1>; + interconnect-names = "icc_path"; + interconnects = <&pcie_anoc MASTER_PCIE_2 &mc_virt SLAVE_EBI1>; clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, <&rpmhcc RPMH_CXO_CLK>, @@ -381,9 +670,9 @@ reset-names = "pcie_2_core_reset", "pcie_2_phy_reset"; - //qcom,smmu-sid-base = <0x0900>; - //iommu-map = <0x0 &apps_smmu 0x0900 0x1>, - // <0x100 &apps_smmu 0x0901 0x1>; + qcom,smmu-sid-base = <0x0900>; + iommu-map = <0x0 &apps_smmu 0x0900 0x1>, + <0x100 &apps_smmu 0x0901 0x1>; qcom,aux-clk-freq = <20>; /* 19.2 MHz */ qcom,tpwr-on-scale = <1>; @@ -393,6 +682,92 @@ qcom,ep-latency = <10>; qcom,num-parf-testbus-sel = <0xb9>; + qcom,pcie-phy-ver = <001>; + qcom,phy-status-offset = <0x214>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x240>; + qcom,phy-sequence = <0x0240 0x03 0x0 + 0x0000 0x4c 0x0 + 0x0004 0x06 0x0 + 0x0010 0x02 0x0 + 0x0014 0x16 0x0 + 0x0018 0x36 0x0 + 0x001c 0x04 0x0 + 0x0020 0x14 0x0 + 0x0024 0x34 0x0 + 0x0028 0x68 0x0 + 0x0030 0xab 0x0 + 0x0034 0xaa 0x0 + 0x0038 0x02 0x0 + 0x003c 0x01 0x0 + 0x0060 0xde 0x0 + 0x0064 0x07 0x0 + 0x0070 0x02 0x0 + 0x0074 0x16 0x0 + 0x0078 0x36 0x0 + 0x0080 0x0a 0x0 + 0x0084 0x1a 0x0 + 0x0088 0x82 0x0 + 0x0090 0x55 0x0 + 0x0094 0x55 0x0 + 0x0098 0x03 0x0 + 0x00bc 0x0e 0x0 + 0x00c0 0x00 0x0 + 0x00cc 0x31 0x0 + 0x00d0 0x01 0x0 + 0x00e0 0x90 0x0 + 0x00e4 0x82 0x0 + 0x00f4 0x07 0x0 + 0x0110 0x04 0x0 + 0x0120 0x42 0x0 + 0x0140 0x14 0x0 + 0x0164 0x34 0x0 + 0x0170 0xa0 0x0 + 0x0174 0x16 0x0 + 0x01bc 0x0f 0x0 + 0x02dc 0x05 0x0 + 0x0388 0x77 0x0 + 0x0398 0x0b 0x0 + 0x03e0 0x0f 0x0 + 0x060c 0x1d 0x0 + 0x061c 0x8c 0x0 + 0x0620 0xc1 0x0 + 0x0654 0x00 0x0 + 0x0694 0x00 0x0 + 0x0e3c 0x17 0x0 + 0x0e40 0x06 0x0 + 0x0e84 0x15 0x0 + 0x0e90 0x3f 0x0 + 0x0ee4 0x02 0x0 + 0x1008 0x09 0x0 + 0x1014 0x05 0x0 + 0x104c 0x08 0x0 + 0x1050 0x08 0x0 + 0x10cc 0xf0 0x0 + 0x10d8 0x0f 0x0 + 0x10dc 0x11 0x0 + 0x10f8 0x07 0x0 + 0x1118 0x0c 0x0 + 0x115c 0x3f 0x0 + 0x1160 0xbf 0x0 + 0x1164 0xbf 0x0 + 0x1168 0xb7 0x0 + 0x116c 0xea 0x0 + 0x1170 0xdc 0x0 + 0x1174 0x5c 0x0 + 0x1178 0x9c 0x0 + 0x117c 0x1a 0x0 + 0x1180 0x89 0x0 + 0x1188 0x94 0x0 + 0x118c 0x5b 0x0 + 0x1190 0x1a 0x0 + 0x1194 0x89 0x0 + 0x11a4 0x38 0x0 + 0x11f8 0x08 0x0 + 0x0200 0x00 0x0 + 0x0244 0x03 0x0>; + + pcie2_rp: pcie2_rp { reg = <0 0 0 0 0>; }; diff --git a/qcom/sdxpinn-pinctrl.dtsi b/qcom/sdxpinn-pinctrl.dtsi index d56e0874..184fd03f 100644 --- a/qcom/sdxpinn-pinctrl.dtsi +++ b/qcom/sdxpinn-pinctrl.dtsi @@ -3,7 +3,7 @@ qupv3_se1_2uart_tx_active: qupv3_se1_2uart_tx_active { mux { pins = "gpio12"; - function = "qup_se1_l2"; + function = "qup_se1_l2_mira"; }; config { @@ -16,7 +16,7 @@ qupv3_se1_2uart_rx_active: qupv3_se1_2uart_rx_active { mux { pins = "gpio13"; - function = "qup_se1_l3"; + function = "qup_se1_l3_mira"; }; config { @@ -40,6 +40,785 @@ }; }; + qupv3_se3_4uart_pins: qupv3_se3_4uart_pins { + qupv3_se3_default_cts: qupv3_se3_default_cts { + mux { + pins = "gpio52"; + function = "gpio"; + }; + + config { + pins = "gpio52"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se3_default_rts: qupv3_se3_default_rts { + mux { + pins = "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se3_default_tx: qupv3_se3_default_tx { + mux { + pins = "gpio54"; + function = "gpio"; + }; + + config { + pins = "gpio54"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_default_rx: qupv3_se3_default_rx { + mux { + pins = "gpio55"; + function = "gpio"; + }; + + config { + pins = "gpio55"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se3_cts: qupv3_se3_cts { + mux { + pins = "gpio52"; + function = "qup_se3_l0"; + }; + + config { + pins = "gpio52"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se3_rts: qupv3_se3_rts { + mux { + pins = "gpio53"; + function = "qup_se3_l1"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se3_tx: qupv3_se3_tx { + mux { + pins = "gpio54"; + function = "qup_se3_l2"; + }; + + config { + pins = "gpio54"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_rx: qupv3_se3_rx { + mux { + pins = "gpio55"; + function = "qup_se3_l3"; + }; + + config { + pins = "gpio55"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_sda_active: qupv3_se0_i2c_sda_active { + mux { + pins = "gpio8"; + function = "qup_se0_l0"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_i2c_scl_active: qupv3_se0_i2c_scl_active { + mux { + pins = "gpio9"; + function = "qup_se0_l1"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio8", "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se0_spi_pins: qupv3_se0_spi_pins { + qupv3_se0_spi_miso_active: qupv3_se0_spi_miso_active { + mux { + pins = "gpio8"; + function = "qup_se0_l0"; + }; + + config { + pins = "gpio8"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se0_spi_mosi_active: qupv3_se0_spi_mosi_active { + mux { + pins = "gpio9"; + function = "qup_se0_l1"; + }; + + config { + pins = "gpio9"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se0_spi_clk_active: qupv3_se0_spi_clk_active { + mux { + pins = "gpio10"; + function = "qup_se0_l2"; + }; + + config { + pins = "gpio10"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se0_spi_cs_active: qupv3_se0_spi_cs_active { + mux { + pins = "gpio11"; + function = "qup_se0_l3"; + }; + + config { + pins = "gpio11"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_sda_active: qupv3_se2_i2c_sda_active { + mux { + pins = "gpio14"; + function = "qup_se2_l0"; + }; + + config { + pins = "gpio14"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se2_i2c_scl_active: qupv3_se2_i2c_scl_active { + mux { + pins = "gpio15"; + function = "qup_se2_l1"; + }; + + config { + pins = "gpio15"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio14", "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_miso_active: qupv3_se2_spi_miso_active { + mux { + pins = "gpio14"; + function = "qup_se2_l0"; + }; + + config { + pins = "gpio14"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se2_spi_mosi_active: qupv3_se2_spi_mosi_active { + mux { + pins = "gpio15"; + function = "qup_se2_l1"; + }; + + config { + pins = "gpio15"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se2_spi_clk_active: qupv3_se2_spi_clk_active { + mux { + pins = "gpio16"; + function = "qup_se2_l2"; + }; + + config { + pins = "gpio16"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se2_spi_cs_active: qupv3_se2_spi_cs_active { + mux { + pins = "gpio17"; + function = "qup_se2_l3"; + }; + + config { + pins = "gpio17"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio14", "gpio15", + "gpio16", "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio14", "gpio15", + "gpio16", "gpio17"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { + qupv3_se3_i2c_sda_active: qupv3_se3_i2c_sda_active { + mux { + pins = "gpio52"; + function = "qup_se3_l0"; + }; + + config { + pins = "gpio52"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_i2c_scl_active: qupv3_se3_i2c_scl_active { + mux { + pins = "gpio53"; + function = "qup_se3_l1"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep { + mux { + pins = "gpio52", "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio52", "gpio53"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se3_spi_pins: qupv3_se3_spi_pins { + qupv3_se3_spi_miso_active: qupv3_se3_spi_miso_active { + mux { + pins = "gpio52"; + function = "qup_se3_l0"; + }; + + config { + pins = "gpio52"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se3_spi_mosi_active: qupv3_se3_spi_mosi_active { + mux { + pins = "gpio53"; + function = "qup_se3_l1"; + }; + + config { + pins = "gpio53"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se3_spi_clk_active: qupv3_se3_spi_clk_active { + mux { + pins = "gpio54"; + function = "qup_se3_l2"; + }; + + config { + pins = "gpio54"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se3_spi_cs_active: qupv3_se3_spi_cs_active { + mux { + pins = "gpio55"; + function = "qup_se3_l3"; + }; + + config { + pins = "gpio55"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se3_spi_sleep: qupv3_se3_spi_sleep { + mux { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + function = "gpio"; + }; + + config { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se4_2uart_pins: qupv3_se4_2uart_pins { + qupv3_se4_2uart_tx_active: qupv3_se4_2uart_tx_active { + mux { + pins = "gpio64"; + function = "qup_se4_l2"; + }; + + config { + pins = "gpio64"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se4_2uart_rx_active: qupv3_se4_2uart_rx_active { + mux { + pins = "gpio65"; + function = "qup_se4_l3"; + }; + + config { + pins = "gpio65"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se4_2uart_sleep: qupv3_se4_2uart_sleep { + mux { + pins = "gpio64", "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio64", "gpio65"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { + qupv3_se5_i2c_sda_active: qupv3_se5_i2c_sda_active { + mux { + pins = "gpio110"; + function = "qup_se5_l0"; + }; + + config { + pins = "gpio110"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se5_i2c_scl_active: qupv3_se5_i2c_scl_active { + mux { + pins = "gpio111"; + function = "qup_se5_l1"; + }; + + config { + pins = "gpio111"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep { + mux { + pins = "gpio110", "gpio111"; + function = "gpio"; + }; + + config { + pins = "gpio110", "gpio111"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { + qupv3_se6_i2c_sda_active: qupv3_se6_i2c_sda_active { + mux { + pins = "gpio112"; + function = "qup_se6_l0"; + }; + + config { + pins = "gpio112"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se6_i2c_scl_active: qupv3_se6_i2c_scl_active { + mux { + pins = "gpio113"; + function = "qup_se6_l1"; + }; + + config { + pins = "gpio113"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { + mux { + pins = "gpio112", "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio112", "gpio113"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se6_spi_pins: qupv3_se6_spi_pins { + qupv3_se6_spi_miso_active: qupv3_se6_spi_miso_active { + mux { + pins = "gpio112"; + function = "qup_se6_l0"; + }; + + config { + pins = "gpio112"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se6_spi_mosi_active: qupv3_se6_spi_mosi_active { + mux { + pins = "gpio113"; + function = "qup_se6_l1"; + }; + + config { + pins = "gpio113"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se6_spi_clk_active: qupv3_se6_spi_clk_active { + mux { + pins = "gpio114"; + function = "qup_se6_l2"; + }; + + config { + pins = "gpio114"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se6_spi_cs_active: qupv3_se6_spi_cs_active { + mux { + pins = "gpio115"; + function = "qup_se6_l3"; + }; + + config { + pins = "gpio115"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { + mux { + pins = "gpio112", "gpio113", + "gpio114", "gpio115"; + function = "gpio"; + }; + + config { + pins = "gpio112", "gpio113", + "gpio114", "gpio115"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se7_i2c_pins: qupv3_se7_i2c_pins { + qupv3_se7_i2c_sda_active: qupv3_se7_i2c_sda_active { + mux { + pins = "gpio116"; + function = "qup_se7_l0"; + }; + + config { + pins = "gpio116"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se7_i2c_scl_active: qupv3_se7_i2c_scl_active { + mux { + pins = "gpio117"; + function = "qup_se7_l1"; + }; + + config { + pins = "gpio117"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep { + mux { + pins = "gpio116", "gpio117"; + function = "gpio"; + }; + + config { + pins = "gpio116", "gpio117"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se7_spi_pins: qupv3_se7_spi_pins { + qupv3_se7_spi_miso_active: qupv3_se7_spi_miso_active { + mux { + pins = "gpio116"; + function = "qup_se7_l0"; + }; + + config { + pins = "gpio116"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se7_spi_mosi_active: qupv3_se7_spi_mosi_active { + mux { + pins = "gpio117"; + function = "qup_se7_l1"; + }; + + config { + pins = "gpio117"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se7_spi_clk_active: qupv3_se7_spi_clk_active { + mux { + pins = "gpio118"; + function = "qup_se7_l2"; + }; + + config { + pins = "gpio118"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se7_spi_cs_active: qupv3_se7_spi_cs_active { + mux { + pins = "gpio119"; + function = "qup_se7_l3"; + }; + + config { + pins = "gpio119"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se7_spi_sleep: qupv3_se7_spi_sleep { + mux { + pins = "gpio116", "gpio117", + "gpio118", "gpio119"; + function = "gpio"; + }; + + config { + pins = "gpio116", "gpio117", + "gpio118", "gpio119"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se8_2uart_pins: qupv3_se8_2uart_pins { + qupv3_se8_2uart_tx_active: qupv3_se8_2uart_tx_active { + mux { + pins = "gpio124"; + function = "qup_se8_l2"; + }; + + config { + pins = "gpio124"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se8_2uart_rx_active: qupv3_se8_2uart_rx_active { + mux { + pins = "gpio125"; + function = "qup_se8_l3"; + }; + + config { + pins = "gpio125"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se8_2uart_sleep: qupv3_se8_2uart_sleep { + mux { + pins = "gpio124", "gpio125"; + function = "gpio"; + }; + + config { + pins = "gpio124", "gpio125"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + sdc1_on: sdc1_on { clk { pins = "sdc1_clk"; diff --git a/qcom/sdxpinn-qupv3.dtsi b/qcom/sdxpinn-qupv3.dtsi index 808caa83..6b5d3a59 100644 --- a/qcom/sdxpinn-qupv3.dtsi +++ b/qcom/sdxpinn-qupv3.dtsi @@ -1,4 +1,44 @@ &soc { + /* QUPv3 SE Instances + * Qup0 0: SE 0 + * Qup0 1: SE 1 + * Qup0 2: SE 2 + * Qup0 3: SE 3 + * Qup0 4: SE 4 + * Qup0 5: SE 5 + * Qup0 6: SE 6 + * Qup0 7: SE 7 + * Qup0 8: SE 8 + */ + + /* GPI Instance */ + gpi_dma0: qcom,gpi-dma@900000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0x900000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0xf6 0x0>; + qcom,max-num-gpii = <12>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,gpii-mask = <0xfff>; + qcom,ev-factor = <2>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + qcom,gpi-ee-offset = <0x10000>; + dma-coherent; + status = "ok"; + }; + /* QUPv3_0 wrapper instance */ qupv3_0: qcom,qupv3_0_geni_se@9c0000 { compatible = "qcom,geni-se-qup"; @@ -8,10 +48,15 @@ clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus = <&apps_smmu 0xe3 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + dma-coherent; ranges; status = "ok"; - /*PORed Debug UART Instance */ + /* PORed Debug UART Instance */ qupv3_se1_2uart: qcom,qup_uart@984000 { compatible = "qcom,geni-debug-uart"; reg = <0x984000 0x4000>; @@ -19,10 +64,337 @@ interrupts = ; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se1_2uart_tx_active>, <&qupv3_se1_2uart_rx_active>; pinctrl-1 = <&qupv3_se1_2uart_sleep>; status = "disabled"; }; + + /* HS UART Instance */ + qupv3_se3_4uart: qcom,qup_uart@98c000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x98c000 0x4000>; + reg-names = "se_phys"; + interrupts-extended = <&intc GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 55 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "active", "sleep", "shutdown"; + pinctrl-0 = <&qupv3_se3_default_cts>, <&qupv3_se3_default_rts>, + <&qupv3_se3_default_tx>, <&qupv3_se3_default_rx>; + pinctrl-1 = <&qupv3_se3_cts>, <&qupv3_se3_rts>, + <&qupv3_se3_tx>, <&qupv3_se3_rx>; + pinctrl-2 = <&qupv3_se3_cts>, <&qupv3_se3_rts>, + <&qupv3_se3_tx>, <&qupv3_se3_default_rx>; + pinctrl-3 = <&qupv3_se3_default_cts>, <&qupv3_se3_default_rts>, + <&qupv3_se3_default_tx>, <&qupv3_se3_default_rx>; + qcom,wakeup-byte = <0xFD>; + status = "disabled"; + }; + + qupv3_se0_i2c: i2c@980000 { + compatible = "qcom,i2c-geni"; + reg = <0x980000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + dmas = <&gpi_dma0 0 0 3 64 0>, + <&gpi_dma0 1 0 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se0_spi: spi@980000 { + compatible = "qcom,spi-geni"; + reg = <0x980000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_mosi_active>, <&qupv3_se0_spi_miso_active>, + <&qupv3_se0_spi_clk_active>, <&qupv3_se0_spi_cs_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + dmas = <&gpi_dma0 0 0 1 64 0>, + <&gpi_dma0 1 0 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@988000 { + compatible = "qcom,i2c-geni"; + reg = <0x988000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_sda_active>, <&qupv3_se2_i2c_scl_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + dmas = <&gpi_dma0 0 2 3 64 0>, + <&gpi_dma0 1 2 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se2_spi: spi@988000 { + compatible = "qcom,spi-geni"; + reg = <0x988000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_mosi_active>, <&qupv3_se2_spi_miso_active>, + <&qupv3_se2_spi_clk_active>, <&qupv3_se2_spi_cs_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + dmas = <&gpi_dma0 0 2 1 64 0>, + <&gpi_dma0 1 2 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se3_i2c: i2c@98c000 { + compatible = "qcom,i2c-geni"; + reg = <0x98c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_i2c_sda_active>, <&qupv3_se3_i2c_scl_active>; + pinctrl-1 = <&qupv3_se3_i2c_sleep>; + dmas = <&gpi_dma0 0 3 3 64 0>, + <&gpi_dma0 1 3 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se3_spi: spi@98c000 { + compatible = "qcom,spi-geni"; + reg = <0x98c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_spi_mosi_active>, <&qupv3_se3_spi_miso_active>, + <&qupv3_se3_spi_clk_active>, <&qupv3_se3_spi_cs_active>; + pinctrl-1 = <&qupv3_se3_spi_sleep>; + dmas = <&gpi_dma0 0 3 1 64 0>, + <&gpi_dma0 1 3 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* CV2X UART1 Instance */ + qupv3_se4_2uart: qcom,qup_uart@990000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x990000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_2uart_tx_active>, <&qupv3_se4_2uart_rx_active>; + pinctrl-1 = <&qupv3_se4_2uart_sleep>; + status = "disabled"; + }; + + qupv3_se5_i2c: i2c@994000 { + compatible = "qcom,i2c-geni"; + reg = <0x994000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_i2c_sda_active>, <&qupv3_se5_i2c_scl_active>; + pinctrl-1 = <&qupv3_se5_i2c_sleep>; + dmas = <&gpi_dma0 0 5 3 64 0>, + <&gpi_dma0 1 5 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se6_i2c: i2c@998000 { + compatible = "qcom,i2c-geni"; + reg = <0x998000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_i2c_sda_active>, <&qupv3_se6_i2c_scl_active>; + pinctrl-1 = <&qupv3_se6_i2c_sleep>; + dmas = <&gpi_dma0 0 6 3 64 0>, + <&gpi_dma0 1 6 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se6_spi: spi@998000 { + compatible = "qcom,spi-geni"; + reg = <0x998000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_spi_mosi_active>, <&qupv3_se6_spi_miso_active>, + <&qupv3_se6_spi_clk_active>, <&qupv3_se6_spi_cs_active>; + pinctrl-1 = <&qupv3_se6_spi_sleep>; + dmas = <&gpi_dma0 0 6 1 64 0>, + <&gpi_dma0 1 6 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se7_i2c: i2c@99c000 { + compatible = "qcom,i2c-geni"; + reg = <0x99c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_i2c_sda_active>, <&qupv3_se7_i2c_scl_active>; + pinctrl-1 = <&qupv3_se7_i2c_sleep>; + dmas = <&gpi_dma0 0 7 3 64 0>, + <&gpi_dma0 1 7 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se7_spi: spi@99c000 { + compatible = "qcom,spi-geni"; + reg = <0x99c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_spi_mosi_active>, <&qupv3_se7_spi_miso_active>, + <&qupv3_se7_spi_clk_active>, <&qupv3_se7_spi_cs_active>; + pinctrl-1 = <&qupv3_se7_spi_sleep>; + dmas = <&gpi_dma0 0 7 1 64 0>, + <&gpi_dma0 1 7 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* CV2X UART2 Instance */ + qupv3_se8_2uart: qcom,qup_uart@9a0000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x9a0000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_2uart_tx_active>, <&qupv3_se8_2uart_rx_active>; + pinctrl-1 = <&qupv3_se8_2uart_sleep>; + status = "disabled"; + }; }; }; diff --git a/qcom/sdxpinn-rumi.dtsi b/qcom/sdxpinn-rumi.dtsi index 4d0e7198..25d8a6f4 100644 --- a/qcom/sdxpinn-rumi.dtsi +++ b/qcom/sdxpinn-rumi.dtsi @@ -211,7 +211,7 @@ }; &rpmhcc { - compatible = "fixed-clock"; + compatible = "qcom,dummycc"; clock-output-names = "rpmh_clocks"; }; @@ -221,8 +221,11 @@ }; &gcc { - clocks = <&bi_tcxo>, <&pcie20_phy_aux_clk>, <&pcie_1_pipe_clk>, <&pcie_2_pipe_clk>, - <&pcie_pipe_clk>, <&sleep_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + clocks = <&bi_tcxo>, <&emac0_sgmiiphy_mac_rclk>, <&emac0_sgmiiphy_mac_tclk>, + <&emac0_sgmiiphy_rclk>, <&emac0_sgmiiphy_tclk>, <&emac1_sgmiiphy_mac_rclk>, + <&emac1_sgmiiphy_mac_tclk>, <&emac1_sgmiiphy_rclk>, <&emac1_sgmiiphy_tclk>, + <&pcie20_phy_aux_clk>, <&pcie_1_pipe_clk>, <&pcie_2_pipe_clk>, <&pcie_pipe_clk>, + <&sleep_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; }; &gcc_emac0_gdsc { diff --git a/qcom/sdxpinn.dtsi b/qcom/sdxpinn.dtsi index d79a0b4e..fc2cef49 100644 --- a/qcom/sdxpinn.dtsi +++ b/qcom/sdxpinn.dtsi @@ -6,6 +6,8 @@ #include #include #include +#include +#include / { model = "Qualcomm Technologies, Inc. SDXPINN"; @@ -20,11 +22,12 @@ reserved_memory: reserved-memory { }; chosen: chosen { - bootargs = "disable_dma32=on swiotlb=noforce kpti=off cpufreq.default_governor=performance"; + bootargs = "disable_dma32=on swiotlb=noforce kpti=off cpufreq.default_governor=performance pcie_ports=compat"; }; aliases { serial0 = &qupv3_se1_2uart; + hsuart0 = &qupv3_se3_4uart; mmc0 = &sdhc_1; /*SDC1 eMMC slot*/ mmc1 = &sdhc_2; /* SDC2 SD card slot */ }; @@ -297,6 +300,10 @@ ; }; + apps_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + }; + rpmhcc: clock-controller { compatible = "qcom,sdxpinn-rpmh-clk"; #clock-cells = <1>; @@ -500,6 +507,62 @@ #clock-cells = <0>; }; + emac0_sgmiiphy_mac_rclk: emac0_sgmiiphy_mac_rclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac0_sgmiiphy_mac_rclk"; + #clock-cells = <0>; + }; + + emac0_sgmiiphy_mac_tclk: emac0_sgmiiphy_mac_tclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac0_sgmiiphy_mac_tclk"; + #clock-cells = <0>; + }; + + emac0_sgmiiphy_rclk: emac0_sgmiiphy_rclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac0_sgmiiphy_rclk"; + #clock-cells = <0>; + }; + + emac0_sgmiiphy_tclk: emac0_sgmiiphy_tclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac0_sgmiiphy_tclk"; + #clock-cells = <0>; + }; + + emac1_sgmiiphy_mac_rclk: emac1_sgmiiphy_mac_rclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac1_sgmiiphy_mac_rclk"; + #clock-cells = <0>; + }; + + emac1_sgmiiphy_mac_tclk: emac1_sgmiiphy_mac_tclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac1_sgmiiphy_mac_tclk"; + #clock-cells = <0>; + }; + + emac1_sgmiiphy_rclk: emac1_sgmiiphy_rclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac1_sgmiiphy_rclk"; + #clock-cells = <0>; + }; + + emac1_sgmiiphy_tclk: emac1_sgmiiphy_tclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac1_sgmiiphy_tclk"; + #clock-cells = <0>; + }; + pcie20_phy_aux_clk: pcie20_phy_aux_clk { compatible = "fixed-clock"; clock-frequency = <1000>; @@ -543,6 +606,14 @@ vdd_cx-supply = <&VDD_CX_LEVEL>; vdd_mx-supply = <&VDD_MXA_LEVEL>; clocks = <&rpmhcc RPMH_CXO_CLK>, + <&emac0_sgmiiphy_mac_rclk>, + <&emac0_sgmiiphy_mac_tclk>, + <&emac0_sgmiiphy_rclk>, + <&emac0_sgmiiphy_tclk>, + <&emac1_sgmiiphy_mac_rclk>, + <&emac1_sgmiiphy_mac_tclk>, + <&emac1_sgmiiphy_rclk>, + <&emac1_sgmiiphy_tclk>, <&pcie20_phy_aux_clk>, <&pcie_1_pipe_clk>, <&pcie_2_pipe_clk>, @@ -550,6 +621,14 @@ <&sleep_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; clock-names = "bi_tcxo", + "emac0_sgmiiphy_mac_rclk", + "emac0_sgmiiphy_mac_tclk", + "emac0_sgmiiphy_rclk", + "emac0_sgmiiphy_tclk", + "emac1_sgmiiphy_mac_rclk", + "emac1_sgmiiphy_mac_tclk", + "emac1_sgmiiphy_rclk", + "emac1_sgmiiphy_tclk", "pcie20_phy_aux_clk", "pcie_1_pipe_clk", "pcie_2_pipe_clk", @@ -701,6 +780,19 @@ clock-names = "core_clk"; clocks = <&rpmhcc RPMH_QPIC_CLK>; + interconnects = <&system_noc MASTER_QPIC &mc_virt SLAVE_EBI1>; + interconnect-names = "nand-ddr"; + qcom,msm-bus,name = "qpic_nand"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <0 0>, + /* Voting for max b/w on PNOC bus for now */ + <1057800 725760>; + + iommus = <&apps_smmu 0x100 0x7>; + qcom,iommu-dma = "bypass"; + status = "disabled"; }; @@ -892,6 +984,45 @@ status = "disabled"; }; + modem_pas: remoteproc-mss@04080000 { + compatible = "qcom,sdxpinn-modem-pas"; + reg = <0x4080000 0x10000>, + <0x4180000 0x10000>; + status = "disabled"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + cx-supply = <&VDD_CX_LEVEL>; + cx-uV-uA = ; + mx-supply = <&VDD_MODEM_LEVEL>; + mx-uV-uA = ; + reg-names = "cx", "mx"; + + qcom,signal-aop; + qcom,qmp = <&aoss_qmp>; + memory-region = <&mpssadsp_mem>; + + /* Inputs from mss */ + interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 3 0>, + <&modem_smp2p_in 7 0>; + + interrupt-names = "wdog", + "fatal", + "handover", + "ready", + "stop-ack", + "shutdown-ack"; + + /* Outputs to mss */ + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + }; + spmi_bus: qcom,spmi@c42d000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc42d000 0x4000>, @@ -1029,14 +1160,166 @@ qcom,pcie-vendor-id = /bits/ 16 <0x17cb>; qcom,pcie-device-id = /bits/ 16 <0x0309>; qcom,pcie-link-speed = <4>; - qcom,pcie-phy-ver = <7>; + qcom,pcie-phy-ver = <8>; qcom,pcie-active-config; qcom,pcie-aggregated-irq; qcom,pcie-mhi-a7-irq; qcom,phy-status-reg2 = <0x1214>; - qcom,mhi-soc-reset-offset = <0xb01b8>; + qcom,mhi-soc-reset-offset = <0xb001b8>; qcom,aoss-rst-clr; qcom,aux-clk = <0x13>; + qcom,phy-init = <0x1240 0x01 0x0 + 0x0030 0x1d 0x0 + 0x0034 0x03 0x0 + 0x0078 0x01 0x0 + 0x007c 0x00 0x0 + 0x0080 0x51 0x0 + 0x00ac 0x34 0x0 + 0x0208 0x0c 0x0 + 0x020c 0x0a 0x0 + 0x0218 0x04 0x0 + 0x0220 0x16 0x0 + 0x0234 0x00 0x0 + 0x029c 0x80 0x0 + 0x02a0 0x7c 0x0 + 0x02b4 0x05 0x0 + 0x02e8 0x0a 0x0 + 0x030c 0x0d 0x0 + 0x0320 0x0b 0x0 + 0x0348 0x1c 0x0 + 0x0388 0x20 0x0 + 0x0394 0x30 0x0 + 0x03dc 0x09 0x0 + 0x03f4 0x14 0x0 + 0x03f8 0xb3 0x0 + 0x03fc 0x58 0x0 + 0x0400 0x9a 0x0 + 0x0404 0x26 0x0 + 0x0408 0xb6 0x0 + 0x040c 0xee 0x0 + 0x0410 0xdb 0x0 + 0x0414 0xdb 0x0 + 0x0418 0xa0 0x0 + 0x041c 0xdf 0x0 + 0x0420 0x78 0x0 + 0x0424 0x76 0x0 + 0x0428 0xff 0x0 + 0x0830 0x1d 0x0 + 0x0834 0x03 0x0 + 0x0878 0x01 0x0 + 0x087c 0x00 0x0 + 0x0880 0x51 0x0 + 0x08ac 0x34 0x0 + 0x0a08 0x0c 0x0 + 0x0a0c 0x0a 0x0 + 0x0a18 0x04 0x0 + 0x0a20 0x16 0x0 + 0x0a34 0x00 0x0 + 0x0a9c 0x80 0x0 + 0x0aa0 0x7c 0x0 + 0x0ab4 0x05 0x0 + 0x0ae8 0x0a 0x0 + 0x0b0c 0x0d 0x0 + 0x0b20 0x0b 0x0 + 0x0b48 0x1c 0x0 + 0x0b88 0x20 0x0 + 0x0b94 0x30 0x0 + 0x0bdc 0x09 0x0 + 0x0bf4 0x14 0x0 + 0x0bf8 0xb3 0x0 + 0x0bfc 0x58 0x0 + 0x0c00 0x9a 0x0 + 0x0c04 0x26 0x0 + 0x0c08 0xb6 0x0 + 0x0c0c 0xee 0x0 + 0x0c10 0xdb 0x0 + 0x0c14 0xdb 0x0 + 0x0c18 0xa0 0x0 + 0x0c1c 0xdf 0x0 + 0x0c20 0x78 0x0 + 0x0c24 0x76 0x0 + 0x0c28 0xff 0x0 + 0x0ea0 0x01 0x0 + 0x0eb4 0x00 0x0 + 0x0ec4 0x00 0x0 + 0x0ec8 0x1f 0x0 + 0x0ed4 0x12 0x0 + 0x0ed8 0x12 0x0 + 0x0edc 0xdb 0x0 + 0x0ee0 0x9a 0x0 + 0x0ee4 0x38 0x0 + 0x0ee8 0xb6 0x0 + 0x0eec 0x64 0x0 + 0x0ef0 0x1f 0x0 + 0x0ef4 0x1f 0x0 + 0x0ef8 0x1f 0x0 + 0x0efc 0x1f 0x0 + 0x0f00 0x1f 0x0 + 0x0f04 0x1f 0x0 + 0x0f0c 0x1f 0x0 + 0x0f14 0x1f 0x0 + 0x0f1c 0x1f 0x0 + 0x0f28 0x5b 0x0 + 0x1010 0x28 0x0 + 0x1014 0x10 0x0 + 0x1018 0x00 0x0 + 0x101c 0x04 0x0 + 0x1020 0xff 0x0 + 0x1024 0x09 0x0 + 0x1028 0x28 0x0 + 0x103c 0x12 0x0 + 0x1040 0xfb 0x0 + 0x1044 0x01 0x0 + 0x1070 0x28 0x0 + 0x1074 0x0d 0x0 + 0x1078 0x00 0x0 + 0x107c 0x0a 0x0 + 0x1080 0xff 0x0 + 0x1084 0x04 0x0 + 0x1088 0x19 0x0 + 0x109c 0x00 0x0 + 0x10a0 0xfb 0x0 + 0x10a4 0x01 0x0 + 0x10bc 0x06 0x0 + 0x10d8 0x40 0x0 + 0x10dc 0x14 0x0 + 0x10e4 0x07 0x0 + 0x10f4 0x0f 0x0 + 0x1110 0x00 0x0 + 0x1120 0x46 0x0 + 0x1124 0x04 0x0 + 0x1140 0x14 0x0 + 0x1170 0xa0 0x0 + 0x1174 0x06 0x0 + 0x1184 0x88 0x0 + 0x1188 0x14 0x0 + 0x1198 0x0f 0x0 + 0x1378 0x2e 0x0 + 0x1390 0xcc 0x0 + 0x13f8 0x00 0x0 + 0x13fc 0x22 0x0 + 0x129c 0x83 0x0 + 0x12a0 0x09 0x0 + 0x12a4 0xa2 0x0 + 0x1450 0x02 0x0 + 0x1478 0x10 0x0 + 0x14a0 0x16 0x0 + 0x1508 0x02 0x0 + 0x155c 0x2e 0x0 + 0x157c 0x03 0x0 + 0x1584 0x28 0x0 + 0x13dc 0x04 0x0 + 0x13e0 0x02 0x0 + 0x1418 0xc0 0x0 + 0x158c 0x0f 0x0 + 0x15ac 0xf2 0x0 + 0x15c0 0xf2 0x0 + 0x1828 0x00 0x0 + 0x1c28 0x00 0x0 + 0x1e24 0x00 0x0 + 0x1e28 0x00 0x0 + 0x1200 0x00 0x0 + 0x1244 0x03 0x0>; status = "disabled"; }; @@ -1079,6 +1362,53 @@ qcom,mem-buf-msgq { compatible = "qcom,mem-buf-msgq"; }; + + clk_virt: interconnect@0 { + compatible = "qcom,sdxpinn-clk_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect@1 { + compatible = "qcom,sdxpinn-mc_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + dc_noc: interconnect@190E0000 { + compatible = "qcom,sdxpinn-dc_noc"; + reg = <0x190E0000 0x8200>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect@19100000 { + compatible = "qcom,sdxpinn-gem_noc"; + reg = <0x19100000 0x34080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + pcie_anoc: interconnect@16C0000 { + compatible = "qcom,sdxpinn-pcie_anoc"; + reg = <0x16C0000 0x14200>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1640000 { + compatible = "qcom,sdxpinn-system_noc"; + reg = <0x1640000 0x4B400>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + }; &firmware { diff --git a/qcom/slate.dtsi b/qcom/slate.dtsi new file mode 100644 index 00000000..b6cfc1e9 --- /dev/null +++ b/qcom/slate.dtsi @@ -0,0 +1,13 @@ +&soc { + qupv3_se4_spi: spi@4a90000 { /* BLSP4 QUP3*/ + status = "ok"; + qcom,shared_ee; + qcom,slate-spi { + compatible = "qcom,slate-spi"; + reg = <0>; + spi-max-frequency = <737000>; + interrupt-parent = <&tlmm>; + qcom,irq-gpio = <&tlmm 95 1>; + }; + }; +}; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 24c58512..f8f273a3 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -25,6 +25,7 @@ #address-cells = <2>; #size-cells = <2>; memory { device_type = "memory"; reg = <0 0 0 0>; }; + ddr-regions { }; aliases { mmc1 = &sdhc_2; /* SDC2 SD card slot */