From e0f025c92ed56ad318137fb62fe9fc86498959a5 Mon Sep 17 00:00:00 2001 From: Chetan C R Date: Wed, 13 Jul 2022 13:14:28 +0530 Subject: [PATCH 01/65] ARM: dts: msm: Add interconnect property for Khaje Add interconnect support for usb, qseecom, qcedev, sdhci, ipa and qcrypto for Khaje. Change-Id: Icf18e27c33237995d960ab4bc1dc49223b86520b --- qcom/khaje-usb.dtsi | 16 +++++ qcom/khaje.dtsi | 107 +++++++++++++++++++++++++++++++++- qcom/msm-arm-smmu-bengal.dtsi | 19 ++++++ 3 files changed, 139 insertions(+), 3 deletions(-) diff --git a/qcom/khaje-usb.dtsi b/qcom/khaje-usb.dtsi index 1fd1d219..81891652 100644 --- a/qcom/khaje-usb.dtsi +++ b/qcom/khaje-usb.dtsi @@ -44,6 +44,22 @@ 0x1a4>; /* GSI_IF_STS */ qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; + + interconnects = <&system_noc MASTER_USB3 &bimc SLAVE_EBI_CH0>, + <&system_noc MASTER_USB3 &config_noc SLAVE_IPA_CFG>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_USB3>; + + qcom,interconnect-values-nom = /* NOMINAL Votes */ + <240000 700000>, + <0 2400>, + <0 40000>; + + qcom,interconnect-values-svs = /* SVS Votes */ + <240000 700000>, + <0 2400>, + <0 40000>; + dwc3@4e00000 { compatible = "snps,dwc3"; reg = <0x4e00000 0xe000>; diff --git a/qcom/khaje.dtsi b/qcom/khaje.dtsi index ad6a4d89..7d2b25b8 100644 --- a/qcom/khaje.dtsi +++ b/qcom/khaje.dtsi @@ -1907,6 +1907,8 @@ qcom,fde-key-size; qcom,appsbl-qseecom-support; qcom,commonlib64-loaded-by-uefi; + interconnect-names = "data_path"; + interconnects = <&system_noc MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI_CH0>; clock-names = "core_clk_src", "core_clk", "iface_clk", "bus_clk"; @@ -1931,8 +1933,10 @@ reg = <0x1b53000 0x1000>; qcom,msm-rng-iface-clk; qcom,no-qrng-config; - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "iface_clk"; + interconnect-names = "data_path"; + interconnects = <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_HWKM_CORE>; + clock-names = "km_clk_src"; + clocks = <&rpmcc RPM_SMD_HWKM_CLK>; }; qcom_tzlog: tz-log@c125720 { @@ -1954,6 +1958,8 @@ qcom,ce-device = <0>; qcom,ce-hw-shared; qcom,bam-ee = <0>; + interconnect-names = "data_path"; + interconnects = <&system_noc MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI_CH0>; clock-names = "core_clk_src", "core_clk", "iface_clk", "bus_clk"; @@ -2001,6 +2007,8 @@ qcom,bam-ee = <0>; qcom,ce-hw-shared; qcom,clk-mgmt-sus-res; + interconnect-names = "data_path"; + interconnects = <&system_noc MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI_CH0>; clock-names = "core_clk_src", "core_clk", "iface_clk", "bus_clk"; @@ -2520,6 +2528,42 @@ qcom,ice-clk-rates = <300000000 100000000>; + interconnects = <&system_noc MASTER_SDCC_1 &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_SDCC_1>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + qcom,msm-bus,name = "sdhc1"; + qcom,msm-bus,num-cases = <9>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <0 0>, <0 0>, + /* 400 KB/s*/ + <1046 1600>, + <1600 1600>, + /* 20 MB/s */ + <20480 80000>, + <80000 80000>, + /* 25 MB/s */ + <25600 250000>, + <50000 133320>, + /* 50 MB/s */ + <51200 250000>, + <65000 133320>, + /* 100 MB/s */ + <102400 250000>, + <65000 133320>, + /* 200 MB/s */ + <204800 800000>, + <200000 300000>, + /* 400 MB/s */ + <204800 800000>, + <200000 300000>, + /* Max. bandwidth */ + <1338562 4096000>, + <1338562 4096000>; + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 + 100750000 200000000 400000000 4294967295>; + /* Add support for gcc hw reset */ resets = <&gcc GCC_SDCC1_BCR>; reset-names = "core_reset"; @@ -2558,6 +2602,42 @@ <&gcc GCC_SDCC2_APPS_CLK>; clock-names = "iface", "core"; + interconnects = <&system_noc MASTER_SDCC_2 &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_SDCC_2>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <0 0>, <0 0>, + /* 400 KB/s*/ + <1046 3200>, + <1600 1600>, + /* 20 MB/s */ + <52286 250000>, + <80000 133320>, + /* 25 MB/s */ + <65360 250000>, + <100000 133320>, + /* 50 MB/s */ + <130718 250000>, + <133320 133320>, + /* 100 MB/s */ + <261438 250000>, + <150000 133320>, + /* 200 MB/s */ + <261438 800000>, + <300000 300000>, + /* Max. bandwidth */ + <1338562 4096000>, + <1338562 4096000>; + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 + 100750000 200000000 4294967295>; + + qcom,devfreq,freq-table = <50000000 202000000>; + /* DLL HSR settings. Refer go/hsr - DLL settings */ qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; qcom,vbias-skip-wa; @@ -2705,7 +2785,6 @@ vote = <26>; perf; }; - qos1 { mask = <0xf0>; vote = <26>; @@ -3409,6 +3488,7 @@ ddr_dcvs_sp: sp { compatible = "qcom,dcvs-path"; qcom,dcvs-path-type = <0>; + interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI_CH0>; }; }; }; @@ -3531,6 +3611,27 @@ qcom,max_num_smmu_cb = <3>; clocks = <&rpmcc RPM_SMD_IPA_CLK>; clock-names = "core_clk"; + qcom,interconnect,num-cases = <5>; + qcom,interconnect,num-paths = <3>; + interconnects = <&system_noc MASTER_IPA &bimc SLAVE_EBI_CH0>, + <&system_noc MASTER_IPA &system_noc SLAVE_OCIMEM>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_IPA_CFG>; + interconnect-names = "ipa_to_ebi1", "ipa_to_imem", "appss_to_ipa"; + /* No vote */ + qcom,no-vote = + <0 0 0 0 0 0>; + /* SVS2 */ + qcom,svs2 = + <80000 465000 80000 68570 80000 30>; + /* SVS */ + qcom,svs = + <80000 2000000 80000 267461 80000 109890>; + /* NOMINAL */ + qcom,nominal = + <206000 4000000 206000 712961 206000 491520>; + /* TURBO */ + qcom,turbo = + <206000 5598900 206000 1436481 206000 491520>; qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", "TURBO"; diff --git a/qcom/msm-arm-smmu-bengal.dtsi b/qcom/msm-arm-smmu-bengal.dtsi index 48f6dce9..a423ad7c 100644 --- a/qcom/msm-arm-smmu-bengal.dtsi +++ b/qcom/msm-arm-smmu-bengal.dtsi @@ -131,6 +131,9 @@ , ; + interconnects = <&bimc MASTER_AMPSS_M0 + &system_noc SLAVE_TCU>; + qcom,active-only; qcom,actlr = @@ -145,6 +148,10 @@ <0xc782200 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x0 0x400>; + interconnects = <&bimc MASTER_AMPSS_M0 + &config_noc SLAVE_IMEM_CFG>, + <&bimc MASTER_AMPSS_M0 + &system_noc SLAVE_TCU>; qcom,active-only; qcom,iova-width = <36>; @@ -159,6 +166,10 @@ qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc>; + interconnects = <&mmrt_virt MASTER_MDP_PORT0 + &mmrt_virt SLAVE_SNOC_BIMC_RT>, + <&bimc MASTER_AMPSS_M0 + &system_noc SLAVE_TCU>; qcom,active-only; qcom,iova-width = <36>; @@ -173,6 +184,10 @@ qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc>; + interconnects = <&mmnrt_virt MASTER_CAMNOC_SF + &mmnrt_virt SLAVE_SNOC_BIMC_NRT>, + <&bimc MASTER_AMPSS_M0 + &system_noc SLAVE_TCU>; qcom,active-only; qcom,iova-width = <32>; @@ -187,6 +202,10 @@ qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_turing_mmu_tbu0_gdsc>; + interconnects = <&bimc MASTER_AMPSS_M0 + &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 + &system_noc SLAVE_TCU>; qcom,active-only; qcom,iova-width = <32>; }; From ba276030b6b240e005ece62931c6277a49bdd2d2 Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Tue, 20 Sep 2022 18:30:02 +0530 Subject: [PATCH 02/65] ARM: dts: msm: Add icc properties for i2c slave Add interconnect node for i2c slave core for cinder soc. Change-Id: Iad43bc34e482dea2eab3d8dde6184377865ecd51 --- qcom/cinder.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/cinder.dtsi b/qcom/cinder.dtsi index 9a1a845c..a9d45b75 100644 --- a/qcom/cinder.dtsi +++ b/qcom/cinder.dtsi @@ -1534,6 +1534,9 @@ interrupts = ; clock-names = "sm_bus_xo_clk", "sm_bus_ahb_clk"; clocks = <&gcc GCC_SM_BUS_XO_CLK>, <&gcc GCC_SM_BUS_AHB_CLK>; + interconnect-names = "i2c-slave-config"; + interconnects = + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_SMBUS_CFG>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_slave_sda_active>, <&i2c_slave_scl_active>; pinctrl-1 = <&i2c_slave_sleep>; From 43baf378cddd948aeca71f77fabd905c378d28b3 Mon Sep 17 00:00:00 2001 From: Ram Kumar Dwivedi Date: Thu, 22 Sep 2022 05:24:29 -0700 Subject: [PATCH 03/65] ARM: dts: msm: Disable lpm mode for UFS Added a property to ufshc_mem node to disable lpm in UFS Change-Id: I00711c5eb92882f4b766bc36d9fd61d53dd66ff6 --- qcom/sa8195p.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sa8195p.dtsi b/qcom/sa8195p.dtsi index 1ef2dcc4..b3ea9752 100644 --- a/qcom/sa8195p.dtsi +++ b/qcom/sa8195p.dtsi @@ -34,6 +34,7 @@ vcc-max-microamp = <750000>; vccq-max-microamp = <750000>; vccq2-max-microamp = <750000>; + qcom,disable-lpm; qcom,vddp-ref-clk-supply = <&pm8195_2_l5>; qcom,vddp-ref-clk-max-microamp = <100>; From 5ce74c596a067056875fa0923ebef4780d71d0c3 Mon Sep 17 00:00:00 2001 From: Priyansh Jain Date: Tue, 20 Sep 2022 09:15:52 +0530 Subject: [PATCH 04/65] ARM: dts: msm: Update tsens thermal zones for aminiAQ chipset Update tsens thermal zones for aminiAQ chipset as per latest recommendation. Change-Id: I72ec18a33aeaee4cf524c554f0ce47d1a4597b8a --- qcom/sa410m.dtsi | 36 +++++++++++++++++------------------- 1 file changed, 17 insertions(+), 19 deletions(-) diff --git a/qcom/sa410m.dtsi b/qcom/sa410m.dtsi index 88b474ad..4db47bd1 100644 --- a/qcom/sa410m.dtsi +++ b/qcom/sa410m.dtsi @@ -397,28 +397,12 @@ #include "scuba-thermal.dtsi" &thermal_zones { - gpu { - trips { - gpu-cxip-trip { - temperature = <105000>; - }; - - gpu-trip { - temperature = <105000>; - }; - - gpu-cx-mon { - temperature = <115000>; - }; - }; - - cooling-maps { - /delete-node/ gpu_cdev; - /delete-node/ gpu-cx-cdev0; - }; + wlan { + thermal-sensors = <&tsens0 1>; }; cpuss-0 { + thermal-sensors = <&tsens0 2>; trips { cpu-0-2-config { temperature = <115000>; @@ -427,6 +411,7 @@ }; cpuss-1 { + thermal-sensors = <&tsens0 3>; trips { cpu-1-3-configs { temperature = <115000>; @@ -435,6 +420,7 @@ }; mdm-0 { + thermal-sensors = <&tsens0 4>; trips { mdm0-cx-mon { temperature = <105000>; @@ -463,6 +449,7 @@ }; mdm-1 { + thermal-sensors = <&tsens0 5>; trips { mdm1-cx-mon { temperature = <105000>; @@ -489,6 +476,17 @@ }; }; }; + + video { + thermal-sensors = <&tsens0 6>; + }; + + hm-center { + thermal-sensors = <&tsens0 7>; + }; + + /delete-node/ gpu; + /delete-node/ camera; }; #include "msm-arm-smmu-sa410m.dtsi" From b0fa1ee325ddb56ab8f105a4df83d7c0c82367d4 Mon Sep 17 00:00:00 2001 From: congying Date: Mon, 26 Sep 2022 20:21:53 +0800 Subject: [PATCH 05/65] ARM: dts: msm: Update node name of tsens for kalama Tsens needs a different entry name when registering the minidump region, so update tsens node name as the tsens minidump entry name for kalama. Change-Id: Ia67ca59f38f8eab09fef69cc3a0f0b6166f85278 --- qcom/kalama-thermal.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/qcom/kalama-thermal.dtsi b/qcom/kalama-thermal.dtsi index 1b8cf821..249a8dc7 100644 --- a/qcom/kalama-thermal.dtsi +++ b/qcom/kalama-thermal.dtsi @@ -5,7 +5,7 @@ }; &soc { - tsens0: thermal-sensor@c271000 { + tsens0: tsens0@c271000 { compatible = "qcom,tsens-v2"; reg = <0x0c271000 0x1ff>, /* TM */ <0x0c222000 0x1ff>; /* SROT */ @@ -16,7 +16,7 @@ #thermal-sensor-cells = <1>; }; - tsens1: thermal-sensor@c272000 { + tsens1: tsens1@c272000 { compatible = "qcom,tsens-v2"; reg = <0x0c272000 0x1ff>, /* TM */ <0x0c223000 0x1ff>; /* SROT */ @@ -27,7 +27,7 @@ #thermal-sensor-cells = <1>; }; - tsens2: thermal-sensor@c273000 { + tsens2: tsens2@c273000 { compatible = "qcom,tsens-v2"; reg = <0x0c273000 0x1ff>, /* TM */ <0x0c224000 0x1ff>; /* SROT */ From 0e3d2043d0d1109f714cc338e3bc50789af0d526 Mon Sep 17 00:00:00 2001 From: Meenu Raja Sundaram Date: Tue, 2 Aug 2022 10:09:47 +0530 Subject: [PATCH 06/65] ARM: dts: msm: Add glink nodes for AminiAQ Add glink support to enable APPS communication with modem and ADSP on AminiAQ target. Change-Id: I0b28439f9a0285b7183b13ae2b623bd16f73a3b0 --- qcom/scuba_auto.dtsi | 99 ++++++++++++++++++++------------------------ 1 file changed, 44 insertions(+), 55 deletions(-) diff --git a/qcom/scuba_auto.dtsi b/qcom/scuba_auto.dtsi index 2c7d2fe0..def5beef 100644 --- a/qcom/scuba_auto.dtsi +++ b/qcom/scuba_auto.dtsi @@ -276,10 +276,6 @@ linux,cma-default; }; - smem_mem: smem@46000000 { - no-map; - reg = <0x0 0x46000000 0x0 0x200000>; - }; }; &soc { @@ -626,60 +622,10 @@ smem: qcom,smem { compatible = "qcom,smem"; - memory-region = <&smem_mem>; + memory-region = <&smem_region>; hwlocks = <&tcsr_mutex 3>; }; - qcom,glink { - compatible = "qcom,glink"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - glink_modem: modem { - qcom,remote-pid = <1>; - transport = "smem"; - mboxes = <&apcs_glb 12>; - mbox-names = "mpss_smem"; - interrupts = ; - - label = "modem"; - qcom,glink-label = "mpss"; - - qcom,modem_qrtr { - qcom,glink-channels = "IPCRTR"; - qcom,low-latency; - qcom,intents = <0x800 5 - 0x2000 3 - 0x4400 2>; - }; - }; - - glink_adsp: adsp { - qcom,remote-pid = <2>; - transport = "smem"; - mboxes = <&apcs_glb 8>; - mbox-names = "adsp_smem"; - interrupts = ; - - label = "adsp"; - qcom,glink-label = "lpass"; - - qcom,adsp_qrtr { - qcom,glink-channels = "IPCRTR"; - qcom,low-latency; - qcom,intents = <0x800 5 - 0x2000 3 - 0x4400 2>; - }; - - qcom,apr_tal_rpmsg { - qcom,glink-channels = "apr_audio_svc"; - qcom,intents = <0x200 20>; - }; - }; - }; - qcom,glinkpkt { compatible = "qcom,glinkpkt"; @@ -798,6 +744,25 @@ /* Outputs to mss */ qcom,smem-states = <&modem_smp2p_out 0>; qcom,smem-state-names = "stop"; + + glink_modem: glink-edge { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&apcs_glb 12>; + mbox-names = "mpss_smem"; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + }; }; @@ -834,6 +799,30 @@ /* Outputs to lpass */ qcom,smem-states = <&adsp_smp2p_out 0>; qcom,smem-state-names = "stop"; + + glink_adsp: glink-edge { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&apcs_glb 8>; + mbox-names = "adsp_smem"; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,apr_tal_rpmsg { + qcom,glink-channels = "apr_audio_svc"; + qcom,intents = <0x200 20>; + }; + }; }; qcom,ipa_fws { From 6abe5960bad61f191106f3d6510bc4c5d3650f91 Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Tue, 27 Sep 2022 15:52:19 +0530 Subject: [PATCH 07/65] ARM: dts: msm: Add interconnect devices for SDXPINN Add interconnect devices for clk_virt, mc_virt_noc, gem_noc, pcie_anoc, dc_noc and system_noc. This will allow consumers to get their path and set bandwidth constraints on them. Change-Id: I2ae256fdfb9a0705d50844a5dfdd46655d433e27 --- qcom/sdxpinn.dtsi | 53 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/qcom/sdxpinn.dtsi b/qcom/sdxpinn.dtsi index 05c605ee..23f50756 100644 --- a/qcom/sdxpinn.dtsi +++ b/qcom/sdxpinn.dtsi @@ -6,6 +6,8 @@ #include #include #include +#include +#include / { model = "Qualcomm Technologies, Inc. SDXPINN"; @@ -283,6 +285,10 @@ ; }; + apps_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + }; + rpmhcc: clock-controller { compatible = "qcom,sdxpinn-rpmh-clk"; #clock-cells = <1>; @@ -963,6 +969,53 @@ qcom,mem-buf-msgq { compatible = "qcom,mem-buf-msgq"; }; + + clk_virt: interconnect@0 { + compatible = "qcom,sdxpinn-clk_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect@1 { + compatible = "qcom,sdxpinn-mc_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + dc_noc: interconnect@190E0000 { + compatible = "qcom,sdxpinn-dc_noc"; + reg = <0x190E0000 0x8200>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect@19100000 { + compatible = "qcom,sdxpinn-gem_noc"; + reg = <0x19100000 0x34080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + pcie_anoc: interconnect@16C0000 { + compatible = "qcom,sdxpinn-pcie_anoc"; + reg = <0x16C0000 0x14200>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1640000 { + compatible = "qcom,sdxpinn-system_noc"; + reg = <0x1640000 0x4B400>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + }; #include "ipcc-test-sdxpinn.dtsi" From 233ab1af9d8937c8bc92c6e2ac2f7be9a0a3ab15 Mon Sep 17 00:00:00 2001 From: Nagireddy Annem Date: Tue, 27 Sep 2022 16:38:27 +0530 Subject: [PATCH 08/65] ARM: dts: msm: Add wdp and atp variants for monaco Add wdp and atp variants for monaco. Change-Id: Ifb38a578d23eb9558de6c6c2343376105758052f --- qcom/Makefile | 4 +++- qcom/monaco-atp-v1-overlay.dts | 9 +++++++++ qcom/monaco-atp-v1.dtsi | 1 + qcom/monaco-wdp-v1-overlay.dts | 9 +++++++++ qcom/monaco-wdp-v1.dtsi | 1 + 5 files changed, 23 insertions(+), 1 deletion(-) create mode 100644 qcom/monaco-atp-v1-overlay.dts create mode 100644 qcom/monaco-atp-v1.dtsi create mode 100644 qcom/monaco-wdp-v1-overlay.dts create mode 100644 qcom/monaco-wdp-v1.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 7883573d..670d802a 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -127,7 +127,9 @@ MONACO_BASE_DTB += monaco.dtb monacop.dtb MONACO_BOARDS += \ monaco-idp-v1-overlay.dtbo \ monaco-idp-v2-overlay.dtbo \ - monaco-idp-v3-overlay.dtbo + monaco-idp-v3-overlay.dtbo \ + monaco-wdp-v1-overlay.dtbo \ + monaco-atp-v1-overlay.dtbo monaco-dtb-$(CONFIG_ARCH_MONACO) += \ $(call add-overlays, $(MONACO_BOARDS) ,$(MONACO_BASE_DTB)) diff --git a/qcom/monaco-atp-v1-overlay.dts b/qcom/monaco-atp-v1-overlay.dts new file mode 100644 index 00000000..acea30f5 --- /dev/null +++ b/qcom/monaco-atp-v1-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "monaco-atp-v1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco ATP V1.0"; + qcom,board-id = <0x010021 0x0>; +}; diff --git a/qcom/monaco-atp-v1.dtsi b/qcom/monaco-atp-v1.dtsi new file mode 100644 index 00000000..6fea5bc4 --- /dev/null +++ b/qcom/monaco-atp-v1.dtsi @@ -0,0 +1 @@ +#include "monaco-idp-v1.dtsi" diff --git a/qcom/monaco-wdp-v1-overlay.dts b/qcom/monaco-wdp-v1-overlay.dts new file mode 100644 index 00000000..f146b0b7 --- /dev/null +++ b/qcom/monaco-wdp-v1-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "monaco-wdp-v1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco WDP V1.0"; + qcom,board-id = <0x010024 0x0>; +}; diff --git a/qcom/monaco-wdp-v1.dtsi b/qcom/monaco-wdp-v1.dtsi new file mode 100644 index 00000000..6fea5bc4 --- /dev/null +++ b/qcom/monaco-wdp-v1.dtsi @@ -0,0 +1 @@ +#include "monaco-idp-v1.dtsi" From b8212fe117bfdb96f3da9cff13139ed6b1f75270 Mon Sep 17 00:00:00 2001 From: Yadu MG Date: Wed, 28 Sep 2022 04:48:45 +0530 Subject: [PATCH 09/65] ARM: dts: msm: Add IPCC node for Lemans Add IPCC node with compatible of qcom,ipcc to enable IPCC driver on Lemans target. Change-Id: I667a29d4cc0fefcb66a2dd0faf3934eba7a23d83 --- qcom/lemans.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/lemans.dtsi b/qcom/lemans.dtsi index 1d366d21..4a557c0f 100644 --- a/qcom/lemans.dtsi +++ b/qcom/lemans.dtsi @@ -598,6 +598,15 @@ interrupts = ; }; + ipcc_mproc: qcom,ipcc@408000 { + compatible = "qcom,ipcc"; + reg = <0x408000 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + clocks { xo_board: xo_board { compatible = "fixed-clock"; From b7b8069b0745872738845facdbda2a515af172a3 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Mon, 4 Jul 2022 14:01:02 +0530 Subject: [PATCH 10/65] dt-bindings: soc: qcom: Add CRM device bindings Add CESTA Resoruce manager (CRM) device bindings. Change-Id: I12ab3e7f8d93b84133018252cbc9e6b0bcba18a0 --- bindings/soc/qcom/qcom,crm.yaml | 124 ++++++++++++++++++++++++++++++++ 1 file changed, 124 insertions(+) create mode 100644 bindings/soc/qcom/qcom,crm.yaml diff --git a/bindings/soc/qcom/qcom,crm.yaml b/bindings/soc/qcom/qcom,crm.yaml new file mode 100644 index 00000000..57faa0a7 --- /dev/null +++ b/bindings/soc/qcom/qcom,crm.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom-crm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. (QTI) CRM bindings + +maintainers: + - Maulik Shah + +description: + Support for communication with the hardened-CRM blocks. A set of HW and + SW client DRVs in CRM provides interface to vote desired power state of + resources local to a subsystem. + +properties: + label: + $ref: /schemas/types.yaml#/definitions/string-array + maxItems: 1 + oneOf: + - items: + - const: cam_crm + - const: pcie_crm + - description: Specifies the name of the CRM. + + compatible: + enum: + - qcom,cam-crm + - qcom,pcie-crm + + reg: + maxItems: 1 + items: + - description: Should specify the base address for the CRM device. + + reg-names: + maxItems: 1 + items: + - const: base + + interrupts: + maxItems: 1 + items: + - description: SW drv vote completion IRQ. + + interrupt-names: + maxItems: 1 + oneOf: + - items: + - const: cam_crm + - const: pcie_crm + + qcom,hw-drv-ids: + description: List of HW DRV IDs. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 3 + items: + minimum: 0 + maximum: 2 + + qcom,sw-drv-ids: + description: List of SW DRV IDs. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 2 + items: + minimum: 0 + maximum: 1 + + clocks: + maxItems: 1 + items: + - description: Bus Clock + +required: + - label + - compatible + - reg + - reg-names + - clocks + +oneOf: + - required: + - qcom,hw-drv-ids + - required: + - qcom,sw-drv-ids + +if: + required: + - qcom,sw-drv-ids +then: + required: + - interrupts + - interrupt-names + +additionalProperties: false + +examples: + # Example of Camera CRM device with HW DRVs + - | + #include + #include + cam_crm: crm@add7000 { + label = "cam_crm"; + compatible = "qcom,cam-crm"; + reg = <0xadd7000 0x2000>; + clocks = <&camcc CAM_CC_DRV_AHB_CLK>; + qcom,hw-drv-ids = <0 1 2>; + }; + # Example of PCIe CRM device with SW DRVs + - | + #include + pcie_crm: crm@1d01000 { + label = "pcie_crm"; + compatible = "qcom,pcie-crm"; + reg = <0x1d01000 0x3000>; + interrupts = ; + interrupt-names = "pcie_crm"; + clocks = <&pcie_0_pipe_clk>; + qcom,sw-drv-ids = <0>; + }; +... From 66cbcfda55b0c4f1ca993fe63ce88c3b3d87ec27 Mon Sep 17 00:00:00 2001 From: Sayan Dey Date: Mon, 4 Apr 2022 18:37:01 +0530 Subject: [PATCH 11/65] ARM: dts: msm: Add remoteproc node for sdxpinn modem Add remoteproc node for sdxpinn modem subsystem. Change-Id: I2102b1f7355b7bfccb886f0cd680717d546c6c50 --- qcom/sdxpinn.dtsi | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/qcom/sdxpinn.dtsi b/qcom/sdxpinn.dtsi index 6cade107..9530a7d3 100644 --- a/qcom/sdxpinn.dtsi +++ b/qcom/sdxpinn.dtsi @@ -884,6 +884,45 @@ status = "disabled"; }; + modem_pas: remoteproc-mss@04080000 { + compatible = "qcom,sdxpinn-modem-pas"; + reg = <0x4080000 0x10000>, + <0x4180000 0x10000>; + status = "disabled"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + cx-supply = <&VDD_CX_LEVEL>; + cx-uV-uA = ; + mx-supply = <&VDD_MODEM_LEVEL>; + mx-uV-uA = ; + reg-names = "cx", "mx"; + + qcom,signal-aop; + qcom,qmp = <&aoss_qmp>; + memory-region = <&mpssadsp_mem>; + + /* Inputs from mss */ + interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 3 0>, + <&modem_smp2p_in 7 0>; + + interrupt-names = "wdog", + "fatal", + "handover", + "ready", + "stop-ack", + "shutdown-ack"; + + /* Outputs to mss */ + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + }; + spmi_bus: qcom,spmi@c42d000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc42d000 0x4000>, From b493818518497eaa9518caf47ddd78814a0dfd94 Mon Sep 17 00:00:00 2001 From: Suraj Jaiswal Date: Fri, 23 Sep 2022 13:39:57 +0530 Subject: [PATCH 12/65] ARM: dts: msm: Enable gmac_4 Enable gmac_4 support from DTSI to fix Ethernet driver failure. Change-Id: I6687caa518198d616135cc20b724c1447f3c5108 --- qcom/sa8155.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi index 1e1f35af..5ce5c715 100644 --- a/qcom/sa8155.dtsi +++ b/qcom/sa8155.dtsi @@ -222,7 +222,7 @@ hsi2s: qcom,hsi2s { }; ethqos_hw: qcom,ethernet@00020000 { - compatible = "qcom,stmmac-ethqos"; + compatible = "qcom,stmmac-ethqos", "snps,dwmac-4.20a"; qcom,arm-smmu; reg = <0x20000 0x10000>, <0x36000 0x100>, From 13760a45c63680cb9de749fa1241a614f3be6d7b Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Tue, 27 Sep 2022 10:28:55 +0530 Subject: [PATCH 13/65] ARM: dts: msm: Add KGSL SMMU Device node for Lemans Add KGSL SMMU Device node for Lemans target. Change-Id: I5bb44d7f9820e9589b79cdef61ce9b33a3b3cdf8 --- qcom/msm-arm-smmu-lemans.dtsi | 108 ++++++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/qcom/msm-arm-smmu-lemans.dtsi b/qcom/msm-arm-smmu-lemans.dtsi index e3487485..baba59ab 100644 --- a/qcom/msm-arm-smmu-lemans.dtsi +++ b/qcom/msm-arm-smmu-lemans.dtsi @@ -281,6 +281,91 @@ }; }; + kgsl_smmu: kgsl-smmu@3da0000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x3da0000 0x20000>, + <0x3dca000 0x28>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,split-tables; + #global-interrupts = <2>; + #size-cells = <1>; + #address-cells = <1>; + #tcu-testbus-version = <1>; + ranges; + dma-coherent; + qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cc_cx_gdsc>; + + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>; + + clock-names = "gcc_gpu_memnoc_gfx", + "gcc_gpu_snoc_dvm_gfx", + "gpu_cc_ahb", + "gpu_cc_hlos1_vote_gpu_smmu_clk", + "gpu_cc_cx_gmu_clk", + "gpu_cc_hub_cx_int_clk", + "gpu_cc_hub_aon_clk"; + + + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + + gfx_0_tbu: gfx_0_tbu@3dd1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x3DD1000 0x1000>, + <0x3DCA200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + qcom,iova-width = <49>; + }; + + gfx_1_tbu: gfx_1_tbu@3dd3000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x3DD3000 0x1000>, + <0x3DCA208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + qcom,iova-width = <49>; + }; + + gfx_2_tbu: gfx_2_tbu@3dd9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x3DD9000 0x1000>, + <0x3DCB200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x800 0x400>; + qcom,iova-width = <49>; + }; + + gfx_3_tbu: gfx_3_tbu@3ddb000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x3DDB000 0x1000>, + <0x3DCB208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0xC00 0x400>; + qcom,iova-width = <49>; + }; + }; + iommu_test_device { compatible = "qcom,iommu-debug-test"; @@ -307,5 +392,28 @@ iommus = <&apps_smmu 0x581 0>; dma-coherent; }; + + usecase0_kgsl { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&kgsl_smmu 0x7 0xC00>; + }; + + usecase1_kgsl_fastmap { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&kgsl_smmu 0x7 0xC00>; + qcom,iommu-dma = "fastmap"; + }; + + usecase2_kgsl_atomic { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&kgsl_smmu 0x7 0xC00>; + qcom,iommu-dma = "atomic"; + }; + + usecase3_kgsl_dma { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&kgsl_smmu 0x407 0xC00>; + dma-coherent; + }; }; }; From 5c1d866664e7f8d8e0f67914876355a5b4143352 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Thu, 28 Jul 2022 11:11:00 +0530 Subject: [PATCH 14/65] ARM: dts: msm: Update GCC and GDSC nodes for sdxbaagha Update the global clock controller and GDSC nodes for sdxbaagha platform. Change-Id: I82e784fdcba23293501dcbf9b69cf0c8f4f95055 --- qcom/sdxbaagha-rumi.dtsi | 4 ++++ qcom/sdxbaagha.dtsi | 29 ++++++++++++++++++++++++----- 2 files changed, 28 insertions(+), 5 deletions(-) diff --git a/qcom/sdxbaagha-rumi.dtsi b/qcom/sdxbaagha-rumi.dtsi index 84c43d30..26af1922 100644 --- a/qcom/sdxbaagha-rumi.dtsi +++ b/qcom/sdxbaagha-rumi.dtsi @@ -23,3 +23,7 @@ &qupv3_se3_2uart { qcom,rumi_platform; }; + +&gcc { + clocks = <&bi_tcxo>, <&pcie_pipe_clk>, <&sleep_clk>; +}; diff --git a/qcom/sdxbaagha.dtsi b/qcom/sdxbaagha.dtsi index 2cffd768..96423ef7 100644 --- a/qcom/sdxbaagha.dtsi +++ b/qcom/sdxbaagha.dtsi @@ -383,28 +383,47 @@ }; gcc: clock-controller@80000 { - compatible = "qcom,dummycc"; - clock-output-names = "gcc_clocks"; + compatible = "qcom,sdxbaagha-gcc", "syscon"; + reg = <0x80000 0x1f4200>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mxa-supply = <&VDD_MXA_LEVEL>; + vdd_mxc-supply = <&VDD_MXC_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&pcie_pipe_clk>, + <&sleep_clk>; + clock-names = "bi_tcxo", + "pcie_pipe_clk", + "sleep_clk"; #clock-cells = <1>; #reset-cells = <1>; }; /* GCC GDSCs */ gcc_emac0_gdsc: qcom,gdsc@f1004 { - compatible = "qcom,stub-regulator"; + compatible = "qcom,gdsc"; + reg = <0xf1004 0x4>; regulator-name = "gcc_emac0_gdsc"; + parent-supply = <&VDD_MXC_LEVEL>; + qcom,retain-regs; qcom,support-hw-trigger; }; gcc_pcie_gdsc: qcom,gdsc@d3004 { - compatible = "qcom,stub-regulator"; + compatible = "qcom,gdsc"; + reg = <0xd3004 0x4>; regulator-name = "gcc_pcie_gdsc"; + parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; qcom,support-hw-trigger; }; gcc_usb20_gdsc: qcom,gdsc@a7004 { - compatible = "qcom,stub-regulator"; + compatible = "qcom,gdsc"; + reg = <0xa7004 0x4>; regulator-name = "gcc_usb20_gdsc"; + parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; }; ipcc_mproc: qcom,ipcc@408000 { From 02e698905ba415cfd0f969f4b2bd1a03cf3e130c Mon Sep 17 00:00:00 2001 From: Aniket Randive Date: Tue, 16 Aug 2022 15:30:13 +0530 Subject: [PATCH 15/65] ARM: dts: msm: Add QUPv3 node for Lemans target Add I2C/SPI/UART QUP node for Lemans target. Change-Id: I12edf543e87f61565d86ce798675a959353dbaa2 --- qcom/lemans-pinctrl.dtsi | 1471 ++++++++++++++++++++++++++++++++++++++ qcom/lemans-qupv3.dtsi | 997 ++++++++++++++++++++++++++ qcom/lemans.dtsi | 9 +- 3 files changed, 2476 insertions(+), 1 deletion(-) create mode 100644 qcom/lemans-qupv3.dtsi diff --git a/qcom/lemans-pinctrl.dtsi b/qcom/lemans-pinctrl.dtsi index 9f30c84a..9be9889c 100644 --- a/qcom/lemans-pinctrl.dtsi +++ b/qcom/lemans-pinctrl.dtsi @@ -1,2 +1,1473 @@ &tlmm { + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_active: qupv3_se0_i2c_active { + mux { + pins = "gpio20", "gpio21"; + function = "qup0_se0"; + }; + + config { + pins = "gpio20", "gpio21"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio20", "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio20", "gpio21"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se0_spi_pins: qupv3_se0_spi_pins { + qupv3_se0_spi_active: qupv3_se0_spi_active { + mux { + pins = "gpio20", "gpio21", + "gpio22", "gpio23"; + function = "qup0_se0"; + }; + + config { + pins = "gpio20", "gpio21", + "gpio22", "gpio23"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { + mux { + pins = "gpio20", "gpio21", + "gpio22", "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio20", "gpio21", + "gpio22", "gpio23"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { + qupv3_se1_i2c_active: qupv3_se1_i2c_active { + mux { + pins = "gpio24", "gpio25"; + function = "qup0_se1"; + }; + + config { + pins = "gpio24", "gpio25"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { + mux { + pins = "gpio24", "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio24", "gpio25"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se1_spi_pins: qupv3_se1_spi_pins { + qupv3_se1_spi_active: qupv3_se1_spi_active { + mux { + pins = "gpio24", "gpio25", + "gpio26", "gpio27"; + function = "qup0_se1"; + }; + + config { + pins = "gpio24", "gpio25", + "gpio26", "gpio27"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_sleep: qupv3_se1_spi_sleep { + mux { + pins = "gpio24", "gpio25", + "gpio26", "gpio27"; + function = "gpio"; + }; + + config { + pins = "gpio24", "gpio25", + "gpio26", "gpio27"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_active: qupv3_se2_i2c_active { + mux { + pins = "gpio36", "gpio37"; + function = "qup0_se2"; + }; + + config { + pins = "gpio36", "gpio37"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio36", "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio36", "gpio37"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_active: qupv3_se2_spi_active { + mux { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + function = "qup0_se2"; + }; + + config { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + function = "gpio"; + }; + + config { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { + qupv3_se3_i2c_active: qupv3_se3_i2c_active { + mux { + pins = "gpio28", "gpio29"; + function = "qup0_se3"; + }; + + config { + pins = "gpio28", "gpio29"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep { + mux { + pins = "gpio28", "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio29"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se3_spi_pins: qupv3_se3_spi_pins { + qupv3_se3_spi_active: qupv3_se3_spi_active { + mux { + pins = "gpio28", "gpio29", + "gpio30", "gpio31"; + function = "qup0_se3"; + }; + + config { + pins = "gpio28", "gpio29", + "gpio30", "gpio31"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se3_spi_sleep: qupv3_se3_spi_sleep { + mux { + pins = "gpio28", "gpio29", + "gpio30", "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio29", + "gpio30", "gpio31"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se4_i2c_pins: qupv3_se4_i2c_pins { + qupv3_se4_i2c_active: qupv3_se4_i2c_active { + mux { + pins = "gpio32", "gpio33"; + function = "qup0_se4"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep { + mux { + pins = "gpio32", "gpio33"; + function = "gpio"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se4_spi_pins: qupv3_se4_spi_pins { + qupv3_se4_spi_active: qupv3_se4_spi_active { + mux { + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + function = "qup0_se4"; + }; + + config { + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se4_spi_sleep: qupv3_se4_spi_sleep { + mux { + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { + qupv3_se5_i2c_active: qupv3_se5_i2c_active { + mux { + pins = "gpio36", "gpio37"; + function = "qup0_se5"; + }; + + config { + pins = "gpio36", "gpio37"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep { + mux { + pins = "gpio36", "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio36", "gpio37"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se5_spi_pins: qupv3_se5_spi_pins { + qupv3_se5_spi_active: qupv3_se5_spi_active { + mux { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + function = "qup0_se5"; + }; + + config { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_sleep: qupv3_se5_spi_sleep { + mux { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + function = "gpio"; + }; + + config { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se5_2uart_pins: qupv3_se5_2uart_pins { + qupv3_se5_2uart_active: qupv3_se5_2uart_active { + mux { + pins = "gpio38", "gpio39"; + function = "qup0_se5"; + }; + + config { + pins = "gpio38", "gpio39"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se5_2uart_sleep: qupv3_se5_2uart_sleep { + mux { + pins = "gpio38", "gpio39"; + function = "gpio"; + }; + + config { + pins = "gpio38", "gpio39"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se7_i2c_pins: qupv3_se7_i2c_pins { + qupv3_se7_i2c_active: qupv3_se7_i2c_active { + mux { + pins = "gpio40", "gpio41"; + function = "qup1_se0"; + }; + + config { + pins = "gpio40", "gpio41"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep { + mux { + pins = "gpio40", "gpio41"; + function = "gpio"; + }; + + config { + pins = "gpio40", "gpio41"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se7_spi_pins: qupv3_se7_spi_pins { + qupv3_se7_spi_active: qupv3_se7_spi_active { + mux { + pins = "gpio40", "gpio41", + "gpio42", "gpio43"; + function = "qup1_se0"; + }; + + config { + pins = "gpio40", "gpio41", + "gpio42", "gpio43"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se7_spi_sleep: qupv3_se7_spi_sleep { + mux { + pins = "gpio40", "gpio41", + "gpio42", "gpio43"; + function = "gpio"; + }; + + config { + pins = "gpio40", "gpio41", + "gpio42", "gpio43"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se8_i2c_pins: qupv3_se8_i2c_pins { + qupv3_se8_i2c_active: qupv3_se8_i2c_active { + mux { + pins = "gpio42", "gpio43"; + function = "qup1_se1"; + }; + + config { + pins = "gpio42", "gpio43"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep { + mux { + pins = "gpio42", "gpio43"; + function = "gpio"; + }; + + config { + pins = "gpio42", "gpio43"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se8_spi_pins: qupv3_se8_spi_pins { + qupv3_se8_spi_active: qupv3_se8_spi_active { + mux { + pins = "gpio42", "gpio43", + "gpio40", "gpio41"; + function = "qup1_se1"; + }; + + config { + pins = "gpio42", "gpio43", + "gpio40", "gpio41"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_sleep: qupv3_se8_spi_sleep { + mux { + pins = "gpio42", "gpio43", + "gpio40", "gpio41"; + function = "gpio"; + }; + + config { + pins = "gpio42", "gpio43", + "gpio40", "gpio41"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se9_i2c_pins: qupv3_se9_i2c_pins { + qupv3_se9_i2c_active: qupv3_se9_i2c_active { + mux { + pins = "gpio46", "gpio47"; + function = "qup1_se2"; + }; + + config { + pins = "gpio46", "gpio47"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep { + mux { + pins = "gpio46", "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio46", "gpio47"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se9_spi_pins: qupv3_se9_spi_pins { + qupv3_se9_spi_active: qupv3_se9_spi_active { + mux { + pins = "gpio46", "gpio47", + "gpio44", "gpio45"; + function = "qup1_se2"; + }; + + config { + pins = "gpio46", "gpio47", + "gpio44", "gpio45"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_sleep: qupv3_se9_spi_sleep { + mux { + pins = "gpio46", "gpio47", + "gpio44", "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio46", "gpio47", + "gpio44", "gpio45"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se9_2uart_pins: qupv3_se9_2uart_pins { + qupv3_se9_2uart_active: qupv3_se9_2uart_active { + mux { + pins = "gpio44", "gpio45"; + function = "qup1_se2"; + }; + + config { + pins = "gpio44", "gpio45"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se9_2uart_sleep: qupv3_se9_2uart_sleep { + mux { + pins = "gpio44", "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio44", "gpio45"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se10_i2c_pins: qupv3_se10_i2c_pins { + qupv3_se10_i2c_active: qupv3_se10_i2c_active { + mux { + pins = "gpio44", "gpio45"; + function = "qup1_se3"; + }; + + config { + pins = "gpio44", "gpio45"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep { + mux { + pins = "gpio44", "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio44", "gpio45"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se10_spi_pins: qupv3_se10_spi_pins { + qupv3_se10_spi_active: qupv3_se10_spi_active { + mux { + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + function = "qup1_se3"; + }; + + config { + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se10_spi_sleep: qupv3_se10_spi_sleep { + mux { + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se10_2uart_pins: qupv3_se10_2uart_pins { + qupv3_se10_2uart_active: qupv3_se10_2uart_active { + mux { + pins = "gpio46", "gpio47"; + function = "qup1_se3"; + }; + + config { + pins = "gpio46", "gpio47"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se10_2uart_sleep: qupv3_se10_2uart_sleep { + mux { + pins = "gpio46", "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio46", "gpio47"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se11_i2c_pins: qupv3_se11_i2c_pins { + qupv3_se11_i2c_active: qupv3_se11_i2c_active { + mux { + pins = "gpio48", "gpio49"; + function = "qup1_se4"; + }; + + config { + pins = "gpio48", "gpio49"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep { + mux { + pins = "gpio48", "gpio49"; + function = "gpio"; + }; + + config { + pins = "gpio48", "gpio49"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se11_spi_pins: qupv3_se11_spi_pins { + qupv3_se11_spi_active: qupv3_se11_spi_active { + mux { + pins = "gpio48", "gpio49", + "gpio50", "gpio51"; + function = "qup1_se4"; + }; + + config { + pins = "gpio48", "gpio49", + "gpio50", "gpio51"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se11_spi_sleep: qupv3_se11_spi_sleep { + mux { + pins = "gpio48", "gpio49", + "gpio50", "gpio51"; + function = "gpio"; + }; + + config { + pins = "gpio48", "gpio49", + "gpio50", "gpio51"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se12_i2c_pins: qupv3_se12_i2c_pins { + qupv3_se12_i2c_active: qupv3_se12_i2c_active { + mux { + pins = "gpio52", "gpio53"; + function = "qup1_se5"; + }; + + config { + pins = "gpio52", "gpio53"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep { + mux { + pins = "gpio52", "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio52", "gpio53"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se12_spi_pins: qupv3_se12_spi_pins { + qupv3_se12_spi_active: qupv3_se12_spi_active { + mux { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + function = "qup1_se5"; + }; + + config { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se12_spi_sleep: qupv3_se12_spi_sleep { + mux { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + function = "gpio"; + }; + + config { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se12_4uart_pins: qupv3_se12_4uart_pins { + qupv3_se12_default_cts: qupv3_se12_default_cts { + mux { + pins = "gpio52"; + function = "gpio"; + }; + + config { + pins = "gpio52"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se12_default_rtsrx: qupv3_se12_default_rtsrx { + mux { + pins = "gpio53", "gpio55"; + function = "gpio"; + }; + + config { + pins = "gpio53", "gpio55"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se12_default_tx: qupv3_se12_default_tx { + mux { + pins = "gpio54"; + function = "gpio"; + }; + + config { + pins = "gpio54"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se12_ctsrx: qupv3_se12_ctsrx { + mux { + pins = "gpio52", "gpio55"; + function = "qup1_se5"; + }; + + config { + pins = "gpio52", "gpio55"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se12_rts: qupv3_se12_rts { + mux { + pins = "gpio53"; + function = "qup1_se5"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se12_tx: qupv3_se12_tx { + mux { + pins = "gpio54"; + function = "qup1_se5"; + }; + + config { + pins = "gpio54"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se13_i2c_pins: qupv3_se13_i2c_pins { + qupv3_se13_i2c_active: qupv3_se13_i2c_active { + mux { + pins = "gpio56", "gpio57"; + function = "qup1_se6"; + }; + + config { + pins = "gpio56", "gpio57"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep { + mux { + pins = "gpio56", "gpio57"; + function = "gpio"; + }; + + config { + pins = "gpio56", "gpio57"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se14_i2c_pins: qupv3_se14_i2c_pins { + qupv3_se14_i2c_active: qupv3_se14_i2c_active { + mux { + pins = "gpio80", "gpio81"; + function = "qup2_se0"; + }; + + config { + pins = "gpio80", "gpio81"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se14_i2c_sleep: qupv3_se14_i2c_sleep { + mux { + pins = "gpio80", "gpio81"; + function = "gpio"; + }; + + config { + pins = "gpio80", "gpio81"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se14_spi_pins: qupv3_se14_spi_pins { + qupv3_se14_spi_active: qupv3_se14_spi_active { + mux { + pins = "gpio80", "gpio81", + "gpio82", "gpio83"; + function = "qup2_se0"; + }; + + config { + pins = "gpio80", "gpio81", + "gpio82", "gpio83"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se14_spi_sleep: qupv3_se14_spi_sleep { + mux { + pins = "gpio80", "gpio81", + "gpio82", "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio80", "gpio81", + "gpio82", "gpio83"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se15_i2c_pins: qupv3_se15_i2c_pins { + qupv3_se15_i2c_active: qupv3_se15_i2c_active { + mux { + pins = "gpio84", "gpio85"; + function = "qup2_se1"; + }; + + config { + pins = "gpio84", "gpio85"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep { + mux { + pins = "gpio84", "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio84", "gpio85"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se15_spi_pins: qupv3_se15_spi_pins { + qupv3_se15_spi_active: qupv3_se15_spi_active { + mux { + pins = "gpio84", "gpio85", + "gpio99", "gpio100"; + function = "qup2_se1"; + }; + + config { + pins = "gpio84", "gpio85", + "gpio99", "gpio100"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se15_spi_sleep: qupv3_se15_spi_sleep { + mux { + pins = "gpio84", "gpio85", + "gpio99", "gpio100"; + function = "gpio"; + }; + + config { + pins = "gpio84", "gpio85", + "gpio99", "gpio100"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se16_i2c_pins: qupv3_se16_i2c_pins { + qupv3_se16_i2c_active: qupv3_se16_i2c_active { + mux { + pins = "gpio86", "gpio87"; + function = "qup2_se2"; + }; + + config { + pins = "gpio86", "gpio87"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se16_i2c_sleep: qupv3_se16_i2c_sleep { + mux { + pins = "gpio86", "gpio87"; + function = "gpio"; + }; + + config { + pins = "gpio86", "gpio87"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se16_spi_pins: qupv3_se16_spi_pins { + qupv3_se16_spi_active: qupv3_se16_spi_active { + mux { + pins = "gpio86", "gpio87", + "gpio88", "gpio89"; + function = "qup2_se2"; + }; + + config { + pins = "gpio86", "gpio87", + "gpio88", "gpio89"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se16_spi_sleep: qupv3_se16_spi_sleep { + mux { + pins = "gpio86", "gpio87", + "gpio88", "gpio89"; + function = "gpio"; + }; + + config { + pins = "gpio86", "gpio87", + "gpio88", "gpio89"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se17_i2c_pins: qupv3_se17_i2c_pins { + qupv3_se17_i2c_active: qupv3_se17_i2c_active { + mux { + pins = "gpio91", "gpio92"; + function = "qup2_se3"; + }; + + config { + pins = "gpio91", "gpio92"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se17_i2c_sleep: qupv3_se17_i2c_sleep { + mux { + pins = "gpio91", "gpio92"; + function = "gpio"; + }; + + config { + pins = "gpio91", "gpio92"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se17_spi_pins: qupv3_se17_spi_pins { + qupv3_se17_spi_active: qupv3_se17_spi_active { + mux { + pins = "gpio91", "gpio92", + "gpio93", "gpio94"; + function = "qup2_se3"; + }; + + config { + pins = "gpio91", "gpio92", + "gpio93", "gpio94"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se17_spi_sleep: qupv3_se17_spi_sleep { + mux { + pins = "gpio91", "gpio92", + "gpio93", "gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio91", "gpio92", + "gpio93", "gpio94"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se17_4uart_pins: qupv3_se17_4uart_pins { + qupv3_se17_default_cts: qupv3_se17_default_cts { + mux { + pins = "gpio91"; + function = "gpio"; + }; + + config { + pins = "gpio91"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se17_default_rtsrx: qupv3_se17_default_rtsrx { + mux { + pins = "gpio92", "gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio92", "gpio94"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se17_default_tx: qupv3_se17_default_tx { + mux { + pins = "gpio93"; + function = "gpio"; + }; + + config { + pins = "gpio93"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se17_ctsrx: qupv3_se17_ctsrx { + mux { + pins = "gpio91", "gpio94"; + function = "qup2_se3"; + }; + + config { + pins = "gpio91", "gpio94"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se17_rts: qupv3_se17_rts { + mux { + pins = "gpio92"; + function = "qup2_se3"; + }; + + config { + pins = "gpio92"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se17_tx: qupv3_se17_tx { + mux { + pins = "gpio93"; + function = "qup2_se3"; + }; + + config { + pins = "gpio93"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se18_i2c_pins: qupv3_se18_i2c_pins { + qupv3_se18_i2c_active: qupv3_se18_i2c_active { + mux { + pins = "gpio95", "gpio96"; + function = "qup2_se4"; + }; + + config { + pins = "gpio95", "gpio96"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se18_i2c_sleep: qupv3_se18_i2c_sleep { + mux { + pins = "gpio95", "gpio96"; + function = "gpio"; + }; + + config { + pins = "gpio95", "gpio96"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se18_spi_pins: qupv3_se18_spi_pins { + qupv3_se18_spi_active: qupv3_se18_spi_active { + mux { + pins = "gpio95", "gpio96", + "gpio97", "gpio98"; + function = "qup2_se4"; + }; + + config { + pins = "gpio95", "gpio96", + "gpio97", "gpio98"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se18_spi_sleep: qupv3_se18_spi_sleep { + mux { + pins = "gpio95", "gpio96", + "gpio97", "gpio98"; + function = "gpio"; + }; + + config { + pins = "gpio95", "gpio96", + "gpio97", "gpio98"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se19_i2c_pins: qupv3_se19_i2c_pins { + qupv3_se19_i2c_active: qupv3_se19_i2c_active { + mux { + pins = "gpio99", "gpio100"; + function = "qup2_se5"; + }; + + config { + pins = "gpio99", "gpio100"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se19_i2c_sleep: qupv3_se19_i2c_sleep { + mux { + pins = "gpio99", "gpio100"; + function = "gpio"; + }; + + config { + pins = "gpio99", "gpio100"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se19_spi_pins: qupv3_se19_spi_pins { + qupv3_se19_spi_active: qupv3_se19_spi_active { + mux { + pins = "gpio99", "gpio100", + "gpio84", "gpio95"; + function = "qup2_se5"; + }; + + config { + pins = "gpio99", "gpio100", + "gpio84", "gpio95"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se19_spi_sleep: qupv3_se19_spi_sleep { + mux { + pins = "gpio99", "gpio100", + "gpio84", "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio99", "gpio100", + "gpio84", "gpio95"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se20_i2c_pins: qupv3_se20_i2c_pins { + qupv3_se20_i2c_active: qupv3_se20_i2c_active { + mux { + pins = "gpio97", "gpio98"; + function = "qup2_se6"; + }; + + config { + pins = "gpio97", "gpio98"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se20_i2c_sleep: qupv3_se20_i2c_sleep { + mux { + pins = "gpio97", "gpio98"; + function = "gpio"; + }; + + config { + pins = "gpio97", "gpio98"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se20_spi_pins: qupv3_se20_spi_pins { + qupv3_se20_spi_active: qupv3_se20_spi_active { + mux { + pins = "gpio97", "gpio98", + "gpio95", "gpio96"; + function = "qup2_se6"; + }; + + config { + pins = "gpio97", "gpio98", + "gpio95", "gpio96"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se20_spi_sleep: qupv3_se20_spi_sleep { + mux { + pins = "gpio97", "gpio98", + "gpio95", "gpio96"; + function = "gpio"; + }; + + config { + pins = "gpio97", "gpio98", + "gpio95", "gpio96"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se21_i2c_pins: qupv3_se21_i2c_pins { + qupv3_se21_i2c_active: qupv3_se21_i2c_active { + mux { + pins = "gpio13", "gpio14"; + function = "qup3_se0"; + }; + + config { + pins = "gpio13", "gpio14"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se21_i2c_sleep: qupv3_se21_i2c_sleep { + mux { + pins = "gpio13", "gpio14"; + function = "gpio"; + }; + + config { + pins = "gpio13", "gpio14"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se21_spi_pins: qupv3_se21_spi_pins { + qupv3_se21_spi_active: qupv3_se21_spi_active { + mux { + pins = "gpio13", "gpio14", + "gpio15", "gpio16"; + function = "qup3_se0"; + }; + + config { + pins = "gpio13", "gpio14", + "gpio15", "gpio16"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se21_spi_sleep: qupv3_se21_spi_sleep { + mux { + pins = "gpio13", "gpio14", + "gpio15", "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio13", "gpio14", + "gpio15", "gpio16"; + drive-strength = <2>; + bias-disable; + }; + }; + }; }; diff --git a/qcom/lemans-qupv3.dtsi b/qcom/lemans-qupv3.dtsi new file mode 100644 index 00000000..2dc039a9 --- /dev/null +++ b/qcom/lemans-qupv3.dtsi @@ -0,0 +1,997 @@ +&soc { + /* QUPv3_0 wrapper instance */ + qupv3_0: qcom,qupv3_0_geni_se@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x9c0000 0x6000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus = <&apps_smmu 0x403 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + status = "ok"; + + qupv3_se0_i2c: i2c@980000 { + compatible = "qcom,i2c-geni"; + reg = <0x980000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se0_spi: spi@980000 { + compatible = "qcom,spi-geni"; + reg = <0x980000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se1_i2c: i2c@984000 { + compatible = "qcom,i2c-geni"; + reg = <0x984000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se1_spi: spi@984000 { + compatible = "qcom,spi-geni"; + reg = <0x984000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_spi_active>; + pinctrl-1 = <&qupv3_se1_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@988000 { + compatible = "qcom,i2c-geni"; + reg = <0x988000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se2_spi: spi@988000 { + compatible = "qcom,spi-geni"; + reg = <0x988000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se3_i2c: i2c@98c000 { + compatible = "qcom,i2c-geni"; + reg = <0x98c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_i2c_active>; + pinctrl-1 = <&qupv3_se3_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se3_spi: spi@98c000 { + compatible = "qcom,spi-geni"; + reg = <0x98c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_spi_active>; + pinctrl-1 = <&qupv3_se3_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se4_i2c: i2c@990000 { + compatible = "qcom,i2c-geni"; + reg = <0x990000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_i2c_active>; + pinctrl-1 = <&qupv3_se4_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se4_spi: spi@990000 { + compatible = "qcom,spi-geni"; + reg = <0x990000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_spi_active>; + pinctrl-1 = <&qupv3_se4_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se5_i2c: i2c@994000 { + compatible = "qcom,i2c-geni"; + reg = <0x994000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_i2c_active>; + pinctrl-1 = <&qupv3_se5_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se5_spi: spi@994000 { + compatible = "qcom,spi-geni"; + reg = <0x994000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_spi_active>; + pinctrl-1 = <&qupv3_se5_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se5_2uart: qcom,qup_uart@994000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x994000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>, + <&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_2uart_active>; + pinctrl-1 = <&qupv3_se5_2uart_sleep>; + status = "disabled"; + }; + }; + + /* QUPv3_1 wrapper instance */ + qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0xac0000 0x6000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0x443 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + + qupv3_se7_i2c: i2c@a80000 { + compatible = "qcom,i2c-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_i2c_active>; + pinctrl-1 = <&qupv3_se7_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se7_spi: spi@a80000 { + compatible = "qcom,spi-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_spi_active>; + pinctrl-1 = <&qupv3_se7_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se8_i2c: i2c@a84000 { + compatible = "qcom,i2c-geni"; + reg = <0xa84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_i2c_active>; + pinctrl-1 = <&qupv3_se8_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se8_spi: spi@a84000 { + compatible = "qcom,spi-geni"; + reg = <0xa84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_spi_active>; + pinctrl-1 = <&qupv3_se8_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se9_i2c: i2c@a88000 { + compatible = "qcom,i2c-geni"; + reg = <0xa88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_i2c_active>; + pinctrl-1 = <&qupv3_se9_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se9_spi: spi@a88000 { + compatible = "qcom,spi-geni"; + reg = <0xa88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_spi_active>; + pinctrl-1 = <&qupv3_se9_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* Debug UART Instance for RUMI*/ + qupv3_se9_2uart: qcom,qup_uart@a88000 { + compatible = "qcom,geni-debug-uart"; + reg = <0xa88000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_2uart_active>; + pinctrl-1 = <&qupv3_se9_2uart_sleep>; + status = "disabled"; + }; + + qupv3_se10_i2c: i2c@a8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_i2c_active>; + pinctrl-1 = <&qupv3_se10_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se10_spi: spi@a8c000 { + compatible = "qcom,spi-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_spi_active>; + pinctrl-1 = <&qupv3_se10_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* Debug UART Instance */ + qupv3_se10_2uart: qcom,qup_uart@a8c000 { + compatible = "qcom,geni-debug-uart"; + reg = <0xa8c000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_2uart_active>; + pinctrl-1 = <&qupv3_se10_2uart_sleep>; + status = "disabled"; + }; + + qupv3_se11_i2c: i2c@a90000 { + compatible = "qcom,i2c-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_i2c_active>; + pinctrl-1 = <&qupv3_se11_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se11_spi: spi@a90000 { + compatible = "qcom,spi-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_spi_active>; + pinctrl-1 = <&qupv3_se11_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se12_i2c: i2c@a94000 { + compatible = "qcom,i2c-geni"; + reg = <0xa94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_i2c_active>; + pinctrl-1 = <&qupv3_se12_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se12_spi: spi@a94000 { + compatible = "qcom,spi-geni"; + reg = <0xa94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_spi_active>; + pinctrl-1 = <&qupv3_se12_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se12_4uart: qcom,qup_uart@a94000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0xa94000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "active", "sleep", "shutdown"; + pinctrl-0 = <&qupv3_se12_default_cts>, + <&qupv3_se12_default_rtsrx>, <&qupv3_se12_default_tx>; + pinctrl-1 = <&qupv3_se12_ctsrx>, <&qupv3_se12_rts>, + <&qupv3_se12_tx>; + pinctrl-2 = <&qupv3_se12_ctsrx>, <&qupv3_se12_rts>, + <&qupv3_se12_tx>; + pinctrl-3 = <&qupv3_se12_default_cts>, + <&qupv3_se12_default_rtsrx>, <&qupv3_se12_default_tx>; + status = "disabled"; + }; + + qupv3_se13_i2c: i2c@a98000 { + compatible = "qcom,i2c-geni"; + reg = <0xa98000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_i2c_active>; + pinctrl-1 = <&qupv3_se13_i2c_sleep>; + status = "disabled"; + }; + }; + + /* QUPv3_2 wrapper instance */ + qupv3_2: qcom,qupv3_2_geni_se@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x8c0000 0x6000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + iommus = <&apps_smmu 0x5a3 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + + qupv3_se14_i2c: i2c@880000 { + compatible = "qcom,i2c-geni"; + reg = <0x880000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se14_i2c_active>; + pinctrl-1 = <&qupv3_se14_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se14_spi: spi@880000 { + compatible = "qcom,spi-geni"; + reg = <0x880000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se14_spi_active>; + pinctrl-1 = <&qupv3_se14_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se15_i2c: i2c@884000 { + compatible = "qcom,i2c-geni"; + reg = <0x884000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_i2c_active>; + pinctrl-1 = <&qupv3_se15_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se15_spi: spi@884000 { + compatible = "qcom,spi-geni"; + reg = <0x884000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_spi_active>; + pinctrl-1 = <&qupv3_se15_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se16_i2c: i2c@888000 { + compatible = "qcom,i2c-geni"; + reg = <0x888000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se16_i2c_active>; + pinctrl-1 = <&qupv3_se16_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se16_spi: spi@888000 { + compatible = "qcom,spi-geni"; + reg = <0x888000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se16_spi_active>; + pinctrl-1 = <&qupv3_se16_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se17_i2c: i2c@88c000 { + compatible = "qcom,i2c-geni"; + reg = <0x88c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se17_i2c_active>; + pinctrl-1 = <&qupv3_se17_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se17_spi: spi@88c000 { + compatible = "qcom,spi-geni"; + reg = <0x88c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se17_spi_active>; + pinctrl-1 = <&qupv3_se17_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* BT UART Instance */ + qupv3_se17_4uart: qcom,qup_uart@88c000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x88c000 0x4000>; + reg-names = "se_phys"; + interrupts-extended = <&intc GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 94 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "active", "sleep", "shutdown"; + pinctrl-0 = <&qupv3_se17_default_cts>, + <&qupv3_se17_default_rtsrx>, <&qupv3_se17_default_tx>; + pinctrl-1 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>, + <&qupv3_se17_tx>; + pinctrl-2 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>, + <&qupv3_se17_tx>; + pinctrl-3 = <&qupv3_se17_default_cts>, + <&qupv3_se17_default_rtsrx>, <&qupv3_se17_default_tx>; + qcom,wakeup-byte = <0xFD>; + status = "disabled"; + }; + + qupv3_se18_i2c: i2c@890000 { + compatible = "qcom,i2c-geni"; + reg = <0x890000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se18_i2c_active>; + pinctrl-1 = <&qupv3_se18_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se18_spi: spi@890000 { + compatible = "qcom,spi-geni"; + reg = <0x890000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se18_spi_active>; + pinctrl-1 = <&qupv3_se18_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se19_i2c: i2c@894000 { + compatible = "qcom,i2c-geni"; + reg = <0x894000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se19_i2c_active>; + pinctrl-1 = <&qupv3_se19_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se19_spi: spi@894000 { + compatible = "qcom,spi-geni"; + reg = <0x894000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se19_spi_active>; + pinctrl-1 = <&qupv3_se19_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se20_i2c: i2c@898000 { + compatible = "qcom,i2c-geni"; + reg = <0x898000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se20_i2c_active>; + pinctrl-1 = <&qupv3_se20_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se20_spi: spi@898000 { + compatible = "qcom,spi-geni"; + reg = <0x898000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se20_spi_active>; + pinctrl-1 = <&qupv3_se20_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + }; + + /* QUPv3_3 wrapper instance */ + qupv3_3: qcom,qupv3_3_geni_se@bc0000 { + compatible = "qcom,geni-se-qup"; + reg = <0xbc0000 0x6000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; + iommus = <&apps_smmu 0x43 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + status = "ok"; + + qupv3_se21_i2c: i2c@b80000 { + compatible = "qcom,i2c-geni"; + reg = <0xb80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_3 &clk_virt SLAVE_QUP_CORE_3>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_3>, + <&aggre1_noc MASTER_QUP_3 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se21_i2c_active>; + pinctrl-1 = <&qupv3_se21_i2c_sleep>; + status = "disabled"; + }; + + qupv3_se21_spi: spi@b80000 { + compatible = "qcom,spi-geni"; + reg = <0xb80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_3 &clk_virt SLAVE_QUP_CORE_3>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_3>, + <&aggre1_noc MASTER_QUP_3 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se21_spi_active>; + pinctrl-1 = <&qupv3_se21_spi_sleep>; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + }; +}; diff --git a/qcom/lemans.dtsi b/qcom/lemans.dtsi index 1d366d21..2b0b079f 100644 --- a/qcom/lemans.dtsi +++ b/qcom/lemans.dtsi @@ -22,7 +22,9 @@ chosen: chosen { }; - aliases { }; + aliases { + serial0 = &qupv3_se10_2uart; + }; soc: soc { }; @@ -1118,3 +1120,8 @@ }; #include "lemans-debug.dtsi" +#include "lemans-qupv3.dtsi" + +&qupv3_se10_2uart { + status = "ok"; +}; From 97cd7572c8cb608d72370c50c70875cd7c2b4db5 Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Sun, 29 May 2022 22:20:45 +0530 Subject: [PATCH 16/65] dt-bindings: interconnect: add interconnect bindings for SDXBAAGHA Add interconnect device bindings. These devices can be used to describe any RPMH and NoC based interconnect devices. Change-Id: I8d10961c4043c0110fed0e6993df7b97d22f7a67 --- bindings/interconnect/qcom,sdxbaagha.txt | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 bindings/interconnect/qcom,sdxbaagha.txt diff --git a/bindings/interconnect/qcom,sdxbaagha.txt b/bindings/interconnect/qcom,sdxbaagha.txt new file mode 100644 index 00000000..2143431c --- /dev/null +++ b/bindings/interconnect/qcom,sdxbaagha.txt @@ -0,0 +1,26 @@ +Qualcomm Technologies, Inc. SDXBAAGHA Network-On-Chip interconnect driver binding +----------------------------------------------------------- + +SDXBAAGHA interconnect providers support system bandwidth requirements through +RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is +able to communicate with the BCM through the Resource State Coordinator (RSC) +associated with each execution environment. Provider nodes must point to at +least one RPMh device child node pertaining to their RSC and each provider +can map to multiple RPMh resources. + +Required properties : +- compatible : shall contain only one of the following: + "qcom,sdxbaagha-aggre_noc", + "qcom,sdxbaagha-cnoc_main", + "qcom,sdxbaagha-dc_noc_dch", + "qcom,sdxbaagha-mc_virt", + "qcom,sdxbaagha-mem_noc", + "qcom,sdxbaagha-snoc", +- #interconnect-cells : should contain 1 + +Examples: + +snoc: interconnect@15C0000 { + compatible = "qcom,sdxbaagha-snoc"; + #interconnect-cells = <1>; +}; From e06b72fb7c0ecd35f95c7ad888231dba59090b49 Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Sun, 29 May 2022 22:31:53 +0530 Subject: [PATCH 17/65] ARM: dts: msm: add stub interconnect devices for SDXBAAGHA Add stub interconnect providers for mc_virt_noc, aggre_noc, cnoc_main_noc, dc_noc_dch_noc, mem_noc, snoc_noc. This will allow consumers to get their path and set bandwidth constraints on them. Change-Id: I7a36988a0c515152ebc1bc8002fd2c258ce48e32 --- qcom/sdxbaagha.dtsi | 50 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/qcom/sdxbaagha.dtsi b/qcom/sdxbaagha.dtsi index 2cffd768..2500429d 100644 --- a/qcom/sdxbaagha.dtsi +++ b/qcom/sdxbaagha.dtsi @@ -2,6 +2,8 @@ #include #include #include +#include +#include / { #address-cells = <1>; @@ -415,6 +417,54 @@ #interrupt-cells = <3>; #mbox-cells = <2>; }; + + mc_virt: interconnect@0 { + compatible = "qcom,sdxbaagha-mc_virt"; + #interconnect-cells = <1>; + qcom,stub; + qcom,skip-qos; + }; + + aggre_noc: interconnect@1640000 { + reg = <0x1640000 0x33400>; + compatible = "qcom,sdxbaagha-aggre_noc"; + #interconnect-cells = <1>; + qcom,stub; + qcom,skip-qos; + }; + + cnoc_main: interconnect@1580000 { + reg = <0x01580000 0x19200>; + compatible = "qcom,sdxbaagha-cnoc_main"; + #interconnect-cells = <1>; + qcom,stub; + qcom,skip-qos; + }; + + dc_noc_dch: interconnect@190E0000 { + reg = <0x190E0000 0x5080>; + compatible = "qcom,sdxbaagha-dc_noc_dch"; + #interconnect-cells = <1>; + qcom,stub; + qcom,skip-qos; + }; + + mem_noc: interconnect@19100000 { + reg = <0x19100000 0x2D080>; + compatible = "qcom,sdxbaagha-mem_noc"; + #interconnect-cells = <1>; + qcom,stub; + qcom,skip-qos; + }; + + snoc: interconnect@15C0000 { + reg = <0x15C0000 0x14080>; + compatible = "qcom,sdxbaagha-snoc"; + #interconnect-cells = <1>; + qcom,stub; + qcom,skip-qos; + }; + }; #include "sdxbaagha-pinctrl.dtsi" From 5c8a2d04ac51c5f6ba445bb49af1356880e6a227 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Mon, 26 Sep 2022 14:22:47 +0530 Subject: [PATCH 18/65] ARM: dts: msm: Update GCC node for sdxpinn platform Add the support for emac clocks and update the GCC clock node for sdxpinn platform. Change-Id: I8d9f6504d92979516c416f0ae92d6acf8ec41f46 --- qcom/sdxpinn-rumi.dtsi | 7 ++-- qcom/sdxpinn.dtsi | 72 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+), 2 deletions(-) diff --git a/qcom/sdxpinn-rumi.dtsi b/qcom/sdxpinn-rumi.dtsi index 4d0e7198..17e29c75 100644 --- a/qcom/sdxpinn-rumi.dtsi +++ b/qcom/sdxpinn-rumi.dtsi @@ -221,8 +221,11 @@ }; &gcc { - clocks = <&bi_tcxo>, <&pcie20_phy_aux_clk>, <&pcie_1_pipe_clk>, <&pcie_2_pipe_clk>, - <&pcie_pipe_clk>, <&sleep_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + clocks = <&bi_tcxo>, <&emac0_sgmiiphy_mac_rclk>, <&emac0_sgmiiphy_mac_tclk>, + <&emac0_sgmiiphy_rclk>, <&emac0_sgmiiphy_tclk>, <&emac1_sgmiiphy_mac_rclk>, + <&emac1_sgmiiphy_mac_tclk>, <&emac1_sgmiiphy_rclk>, <&emac1_sgmiiphy_tclk>, + <&pcie20_phy_aux_clk>, <&pcie_1_pipe_clk>, <&pcie_2_pipe_clk>, <&pcie_pipe_clk>, + <&sleep_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; }; &gcc_emac0_gdsc { diff --git a/qcom/sdxpinn.dtsi b/qcom/sdxpinn.dtsi index 6cade107..e8709681 100644 --- a/qcom/sdxpinn.dtsi +++ b/qcom/sdxpinn.dtsi @@ -492,6 +492,62 @@ #clock-cells = <0>; }; + emac0_sgmiiphy_mac_rclk: emac0_sgmiiphy_mac_rclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac0_sgmiiphy_mac_rclk"; + #clock-cells = <0>; + }; + + emac0_sgmiiphy_mac_tclk: emac0_sgmiiphy_mac_tclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac0_sgmiiphy_mac_tclk"; + #clock-cells = <0>; + }; + + emac0_sgmiiphy_rclk: emac0_sgmiiphy_rclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac0_sgmiiphy_rclk"; + #clock-cells = <0>; + }; + + emac0_sgmiiphy_tclk: emac0_sgmiiphy_tclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac0_sgmiiphy_tclk"; + #clock-cells = <0>; + }; + + emac1_sgmiiphy_mac_rclk: emac1_sgmiiphy_mac_rclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac1_sgmiiphy_mac_rclk"; + #clock-cells = <0>; + }; + + emac1_sgmiiphy_mac_tclk: emac1_sgmiiphy_mac_tclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac1_sgmiiphy_mac_tclk"; + #clock-cells = <0>; + }; + + emac1_sgmiiphy_rclk: emac1_sgmiiphy_rclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac1_sgmiiphy_rclk"; + #clock-cells = <0>; + }; + + emac1_sgmiiphy_tclk: emac1_sgmiiphy_tclk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "emac1_sgmiiphy_tclk"; + #clock-cells = <0>; + }; + pcie20_phy_aux_clk: pcie20_phy_aux_clk { compatible = "fixed-clock"; clock-frequency = <1000>; @@ -535,6 +591,14 @@ vdd_cx-supply = <&VDD_CX_LEVEL>; vdd_mx-supply = <&VDD_MXA_LEVEL>; clocks = <&rpmhcc RPMH_CXO_CLK>, + <&emac0_sgmiiphy_mac_rclk>, + <&emac0_sgmiiphy_mac_tclk>, + <&emac0_sgmiiphy_rclk>, + <&emac0_sgmiiphy_tclk>, + <&emac1_sgmiiphy_mac_rclk>, + <&emac1_sgmiiphy_mac_tclk>, + <&emac1_sgmiiphy_rclk>, + <&emac1_sgmiiphy_tclk>, <&pcie20_phy_aux_clk>, <&pcie_1_pipe_clk>, <&pcie_2_pipe_clk>, @@ -542,6 +606,14 @@ <&sleep_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; clock-names = "bi_tcxo", + "emac0_sgmiiphy_mac_rclk", + "emac0_sgmiiphy_mac_tclk", + "emac0_sgmiiphy_rclk", + "emac0_sgmiiphy_tclk", + "emac1_sgmiiphy_mac_rclk", + "emac1_sgmiiphy_mac_tclk", + "emac1_sgmiiphy_rclk", + "emac1_sgmiiphy_tclk", "pcie20_phy_aux_clk", "pcie_1_pipe_clk", "pcie_2_pipe_clk", From a3e7dd1a976e22ad72093c2ea9c725f77abbc309 Mon Sep 17 00:00:00 2001 From: Nishant Pandey Date: Wed, 28 Sep 2022 10:29:40 -0700 Subject: [PATCH 19/65] ARM: dts: msm: Enable DT overlay support for scuba auto Enable DT overlay support for scuba auto. Change-Id: I8897f48101d8ced825bf399ccd12b701385a9a83 --- qcom/Makefile | 8 ++++++-- ...scuba_auto-idp.dts => scuba_auto-idp-overlay.dts} | 2 +- ...scuba_auto-qrd.dts => scuba_auto-qrd-overlay.dts} | 2 +- qcom/scuba_auto.dts | 10 ++++++++++ qcom/scuba_auto.dtsi | 12 +++++++++++- 5 files changed, 29 insertions(+), 5 deletions(-) rename qcom/{scuba_auto-idp.dts => scuba_auto-idp-overlay.dts} (89%) rename qcom/{scuba_auto-qrd.dts => scuba_auto-qrd-overlay.dts} (88%) create mode 100644 qcom/scuba_auto.dts diff --git a/qcom/Makefile b/qcom/Makefile index 7883573d..49acfb12 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -234,9 +234,13 @@ autogvm-overlays-dtb-$(CONFIG_QTI_QUIN_GVM) += $(SA8155_LA_GVM_BOARDS) $(SA8155_ dtb-y += $(autogvm-dtb-y) +SCUBA_AUTO_BASE_DTB += scuba_auto.dtb +SCUBA_AUTO_BOARDS += \ + scuba_auto-idp-overlay.dtbo \ + scuba_auto-qrd-overlay.dtbo scuba_auto-dtb-$(CONFIG_ARCH_SCUBA_AUTO) += \ - scuba_auto-idp.dtb \ - scuba_auto-qrd.dtb + $(call add-overlays, $(SCUBA_AUTO_BOARDS) ,$(SCUBA_AUTO_BASE_DTB)) +scuba_auto-overlays-dtb-$(CONFIG_ARCH_SCUBA_AUTO) += $(SCUBA_AUTO_BOARDS) $(SCUBA_AUTO_BASE_DTB) dtb-y += $(scuba_auto-dtb-y) endif diff --git a/qcom/scuba_auto-idp.dts b/qcom/scuba_auto-idp-overlay.dts similarity index 89% rename from qcom/scuba_auto-idp.dts rename to qcom/scuba_auto-idp-overlay.dts index b2085f9c..14b319c6 100644 --- a/qcom/scuba_auto-idp.dts +++ b/qcom/scuba_auto-idp-overlay.dts @@ -1,6 +1,6 @@ /dts-v1/; +/plugin/; -#include "scuba_auto.dtsi" #include "scuba_auto-idp.dtsi" / { diff --git a/qcom/scuba_auto-qrd.dts b/qcom/scuba_auto-qrd-overlay.dts similarity index 88% rename from qcom/scuba_auto-qrd.dts rename to qcom/scuba_auto-qrd-overlay.dts index 195a2fad..e38a0032 100644 --- a/qcom/scuba_auto-qrd.dts +++ b/qcom/scuba_auto-qrd-overlay.dts @@ -1,7 +1,7 @@ /dts-v1/; +/plugin/; #include "scuba_auto.dtsi" -#include "scuba_auto-qrd.dtsi" / { model = "Qualcomm Technologies, Inc. SCUBA AUTO QRD"; diff --git a/qcom/scuba_auto.dts b/qcom/scuba_auto.dts new file mode 100644 index 00000000..574e96eb --- /dev/null +++ b/qcom/scuba_auto.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "scuba_auto.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SCUBA AUTO"; + compatible = "qcom,sa410m"; + qcom,msm-id = <441 0x10000>, <471 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/qcom/scuba_auto.dtsi b/qcom/scuba_auto.dtsi index 794d734b..997d4f72 100644 --- a/qcom/scuba_auto.dtsi +++ b/qcom/scuba_auto.dtsi @@ -20,7 +20,9 @@ reserved_memory: reserved-memory { }; - chosen: chosen { }; + chosen: chosen { + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + }; mem-offline { compatible = "qcom,mem-offline"; @@ -317,6 +319,14 @@ clock-frequency = <19200000>; }; + qcom_tzlog: tz-log@c125720 { + compatible = "qcom,tz-log"; + reg = <0xc125720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + }; + memtimer: timer@f120000 { #address-cells = <1>; #size-cells = <1>; From 38b6db15852a9e4017e3e80b0f84de8d7721484a Mon Sep 17 00:00:00 2001 From: Sudarshan Rajagopalan Date: Wed, 3 Aug 2022 14:32:26 -0700 Subject: [PATCH 20/65] ARM: dts: msm: reduce offlineable region for 12GB device for Kalama Reduce the offlinable region by 1GB for 12GB DDR devices for Kalama. Cherry picked from commit 9f858c07838e9965c92e4a455665b51091e182b3. Change-Id: If3a82dced7b2dcd1b266d9bec0927f19ba85f90f --- qcom/kalama.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/kalama.dtsi b/qcom/kalama.dtsi index 38f5bc06..3bb8cc57 100644 --- a/qcom/kalama.dtsi +++ b/qcom/kalama.dtsi @@ -35,7 +35,7 @@ mem-offline { compatible = "qcom,mem-offline"; - offline-sizes = <0x2 0xc0000000 0x1 0x40000000>; + offline-sizes = <0x2 0xc0000000 0x1 0x00000000>; granule = <512>; mboxes = <&qmp_aop 0>; }; From 50316aac14c234bdb2ad827398cc83cf913c5962 Mon Sep 17 00:00:00 2001 From: Vinay Sudra Date: Tue, 6 Sep 2022 17:06:41 +0530 Subject: [PATCH 21/65] ARM: dts: msm: Add ddr-regions node for optimise Optimise for boot up time since it will search for special node ddr-regions in apps boot loader. If put the node in the beginning of the device tree can make it search faster. Change-Id: Ibc1483a6a0d5a65bd119372a9e6a6b3a4dd44145 --- qcom/sm8150.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 24c58512..f8f273a3 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -25,6 +25,7 @@ #address-cells = <2>; #size-cells = <2>; memory { device_type = "memory"; reg = <0 0 0 0>; }; + ddr-regions { }; aliases { mmc1 = &sdhc_2; /* SDC2 SD card slot */ From 1bb52110108e7aad94ad499473a55e89d6605321 Mon Sep 17 00:00:00 2001 From: Vinay Sudra Date: Fri, 30 Sep 2022 11:00:41 +0530 Subject: [PATCH 22/65] ARM: dts: msm: Add ddr-regions node to sdmshrike for optimise Optimise for boot up time since it will search for special node ddr-regions in apps boot loader. If put the node in the beginning of the device tree can make it search faster. Change-Id: Icd77aa23adf153503150237bd28554b3997a2906 --- qcom/sdmshrike.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index f3f17c9e..64f1eca2 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -24,6 +24,7 @@ #address-cells = <2>; #size-cells = <2>; memory { device_type = "memory"; reg = <0 0 0 0>; }; + ddr-regions { }; aliases { ufshc1 = &ufshc_mem; /* Embedded UFS slot */ From bd182ac7c31c16387bf5ffbe4472cd597d9afa6f Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Thu, 29 Sep 2022 15:38:50 +0800 Subject: [PATCH 23/65] ARM: dts: msm: revise cmb elememt size on sdxpinn Revise cmb element size and disable some tpdms on sdxpinn. Change-Id: I8c8bf740cdc65b37191f844411cb194054c677fe --- qcom/sdxpinn-coresight.dtsi | 45 +++++++++++++++++-------------------- 1 file changed, 21 insertions(+), 24 deletions(-) diff --git a/qcom/sdxpinn-coresight.dtsi b/qcom/sdxpinn-coresight.dtsi index 266bb98a..542344b9 100644 --- a/qcom/sdxpinn-coresight.dtsi +++ b/qcom/sdxpinn-coresight.dtsi @@ -217,6 +217,7 @@ atid = <78>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + status = "disabled"; out-ports { port { @@ -473,6 +474,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,cmb-msr-skip; + status = "disabled"; out-ports { port { @@ -495,6 +497,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,cmb-msr-skip; + status = "disabled"; out-ports { port { @@ -516,6 +519,7 @@ atid = <78>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + status = "disabled"; out-ports { port { @@ -599,10 +603,11 @@ reg-names = "tpdm-base"; coresight-name = "coresight-tpdm-pcie-rscc"; - atid = <78>; + atid = <88>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,cmb-msr-skip; + status = "disabled"; out-ports { port { @@ -666,7 +671,7 @@ reg-names = "tpdm-base"; status = "disabled"; - atid = <67>; + atid = <87>; coresight-name = "coresight-tpdm-modem-rscc"; clocks = <&aoss_qmp>; @@ -742,6 +747,7 @@ coresight-name = "coresight-funnel-mvm"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + status = "disabled"; in-ports { @@ -1012,7 +1018,7 @@ qcom,tpda-atid = <67>; qcom,dsb-elem-size = <0 32>; - qcom,cmb-elem-size = <0 64>; + qcom,cmb-elem-size = <1 64>; coresight-name = "coresight-tpda-modem"; @@ -1058,9 +1064,8 @@ reg = <0x2480e000 0x1000>; reg-names = "tpda-base"; - qcom,tpda-atid = <67>; + qcom,tpda-atid = <87>; - qcom,dsb-elem-size = <0 32>; qcom,cmb-elem-size = <0 64>; coresight-name = "coresight-tpda-modem-rscc"; @@ -1099,10 +1104,9 @@ reg = <0x24c09000 0x1000>; reg-names = "tpda-base"; - qcom,tpda-atid = <67>; + qcom,tpda-atid = <88>; - qcom,dsb-elem-size = <0 32>; - qcom,cmb-elem-size = <0 64>; + qcom,cmb-elem-size = <0 8>; coresight-name = "coresight-tpda-pcie-rscc"; @@ -1247,7 +1251,7 @@ qcom,dsb-elem-size = <4 32>; qcom,cmb-elem-size = <0 32>, - <2 64>; + <3 64>; in-ports { @@ -1508,25 +1512,18 @@ qcom,tpda-atid = <78>; - qcom,dsb-elem-size = <0 32>, - <4 32>, - <5 32>, - <7 32>, + qcom,dsb-elem-size = <9 32>, + <11 32>, <15 32>, - <17 32>, <20 32>, <21 32>, - <25 32>, + <23 32>, <26 32>; - qcom,cmb-elem-size = <0 32>, - <7 32>, - <8 64>, - <13 64>, - <14 64>, - <16 32>, + qcom,cmb-elem-size = <5 32>, <19 32>, - <22 32>, - <25 64>, + <20 32>, + <23 64>, + <24 32>, <27 64>; in-ports { @@ -1905,7 +1902,7 @@ qcom,tpda-atid = <71>; - qcom,dsb-elem-size = <2 32>; + qcom,dsb-elem-size = <4 32>; qcom,cmb-elem-size = <0 64>, <1 64>, <2 64>, From dd66ccb76e87a32641a68eb0c4a0ae95ac6557dc Mon Sep 17 00:00:00 2001 From: Shaikh Andlib Date: Tue, 27 Sep 2022 13:01:03 +0530 Subject: [PATCH 24/65] ARM: dts: msm: Enable ICE(Inline Crypto Engine) driver Add dts entries for ICE(Inline Crypto Engine) driver for FBEv2 in autogen3 8195 target. Test: Pin/Pattern/Password test, File Name encryption test, vts_kernel_encryption_test test suite, Build compilation passed. Change-Id: I765fd6452ec3f60a196487e4af2bbe11a1347815 --- qcom/sdmshrike.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index f3f17c9e..14aeab2d 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -1593,7 +1593,7 @@ compatible = "qcom,ufshc"; reg = <0x1d84000 0x3000>, <0x1d90000 0x8000>; - reg-names = "ufs_mem", "ice"; + reg-names = "ufs_mem", "ufs_ice"; interrupts = ; phys = <&ufsphy_mem>; phy-names = "ufsphy"; From 1e7e765f5d01cc7bf3e2149fb13157562ff0dd68 Mon Sep 17 00:00:00 2001 From: Surya Teja Kudiri Date: Fri, 16 Sep 2022 16:28:40 +0530 Subject: [PATCH 25/65] ARM: dts: msm: Create Node entry for parade touch Add parade device tree entry and configuration for touch. Change-Id: Ia3fc1134da6c7031b1528d85657db3d3224e2b43 --- bindings/input/touchscreen/parade_pt.txt | 34 +++++++ qcom/monaco.dtsi | 122 +++++++++++++++++++++++ 2 files changed, 156 insertions(+) create mode 100644 bindings/input/touchscreen/parade_pt.txt diff --git a/bindings/input/touchscreen/parade_pt.txt b/bindings/input/touchscreen/parade_pt.txt new file mode 100644 index 00000000..3a357980 --- /dev/null +++ b/bindings/input/touchscreen/parade_pt.txt @@ -0,0 +1,34 @@ +* Parade pt touch controller + +Please add this description here: The Parade Touch controller is connected to the +host processor via I2C. The controller generates interrupts when the user touches +the panel. The host controller is expected to read the touch coordinates over I2C and +pass the coordinates to the rest of the system. + +Required properties: + - compatible : should be "parade,pt_i2c_adapter" + - reg : i2c slave address of the device. + - vdd-supply : digital voltage power supply needed to power device. + - avdd-supply : analog voltage power supply needed to power device. + - novatek,reset-gpio : reset gpio. + - novatek,irq-gpio : irq gpio. + +Example: + &i2c_1 { + status = "ok"; + + /* Parade device tree node */ + tsc@24 { + compatible = "parade,pt_i2c_adapter"; + reg = <0x24>; + status = "ok"; + + vdd-supply = <&L29A>; + vcc_i2c-supply = <&L21A>; + + parade,core { + parade,rst_gpio = <&tlmm 71 0x00>; + parade,irq_gpio = <&tlmm 80 0x2008>; + }; + }; + }; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 4f5518a3..31660e08 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1878,6 +1878,128 @@ io-channel-names = "chg_type"; }; +&qupv3_se1_i2c { + status = "ok"; + + tsc@24 { + compatible = "parade,pt_i2c_adapter"; + reg = <0x24>; + status = "ok"; + interrupt-parent = <&tlmm>; + interrupts = <80 0x2008>; + parade,adapter_id = "pt_i2c_adapter"; + vcc_i2c-supply = <&L21A>; + vdd-supply = <&L29A>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + + parade,core { + parade,name = "pt_core"; + + parade,irq_gpio = <&tlmm 13 0x2008>; + parade,rst_gpio = <&tlmm 12 0x00>; + parade,hid_desc_register = <1>; + /* + * PT_CORE_FLAG_NONE = 0x00 + * PT_CORE_FLAG_POWEROFF_ON_SLEEP = 0x02 + * PT_CORE_FLAG_RESTORE_PARAMETERS = 0x04 + * PT_CORE_FLAG_DEEP_STANDBY = 0x08 + * PT_CORE_FLAG_SKIP_SYS_SLEEP = 0x10 + * PT_CORE_FLAG_SKIP_RUNTIME = 0x20 + * PT_CORE_FLAG_SKIP_RESUME = 0x40 + */ + parade,flags = <4>; + /* PT_CORE_EWG_NONE */ + parade,easy_wakeup_gesture = <1>; + /* 0:AUTO 1:PIP1_ONLY 2:PIP2_CAPABLE*/ + parade,config_dut_generation = <1>; + /* 0:False 1:True*/ + parade,watchdog_force_stop = <0>; + /* + * PT_PANEL_ID_DISABLE = 0x00 + * PT_PANEL_ID_BY_BL = 0x01 + * PT_PANEL_ID_BY_SYS_INFO = 0x02 + * PT_PANEL_ID_BY_MFG_DATA = 0x04 + */ + parade,panel_id_support = <0>; + parade,btn_keys = <172 /* KEY_HOMEPAGE */ + /* previously was KEY_HOME, new Android versions use KEY_HOMEPAGE */ + 139 /* KEY_MENU */ + 158 /* KEY_BACK */ + 217 /* KEY_SEARCH */ + 114 /* KEY_VOLUMEDOWN */ + 115 /* KEY_VOLUMEUP */ + 212 /* KEY_CAMERA */ + 116>; /* KEY_POWER */ + parade,btn_keys-tag = <0>; + + parade,mt { + parade,name = "pt_mt"; + parade,inp_dev_name = "pt_mt"; + /* + * PT_MT_FLAG_NONE = 0x00 + * PT_MT_FLAG_FLIP = 0x08 + * PT_MT_FLAG_INV_X = 0x10 + * PT_MT_FLAG_INV_Y = 0x20 + * PT_MT_FLAG_VKEYS = 0x40 + */ + parade,flags = <0x08>; + parade,abs = + /* ABS_MT_POSITION_X, CY_ABS_MIN_X, CY_ABS_MAX_X, 0, 0 */ + <0x35 0 880 0 0 + /* ABS_MT_POSITION_Y, CY_ABS_MIN_Y, CY_ABS_MAX_Y, 0, 0 */ + 0x36 0 1280 0 0 + /* ABS_MT_PRESSURE, CY_ABS_MIN_P, CY_ABS_MAX_P, 0, 0 */ + 0x3a 0 255 0 0 + /* CY_IGNORE_VALUE, CY_ABS_MIN_W, CY_ABS_MAX_W, 0, 0 */ + 0xffff 0 255 0 0 + /* ABS_MT_TRACKING_ID, CY_ABS_MIN_T, CY_ABS_MAX_T, 0, 0 */ + 0x39 0 15 0 0 + /* ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0 */ + 0x30 0 255 0 0 + /* ABS_MT_TOUCH_MINOR, 0, 255, 0, 0 */ + 0x31 0 255 0 0 + /* ABS_MT_ORIENTATION, -127, 127, 0, 0 */ + 0x34 0xffffff81 127 0 0 + /* ABS_MT_TOOL_TYPE, 0, MT_TOOL_MAX, 0, 0 */ + 0x37 0 1 0 0 + /* ABS_DISTANCE, 0, 255, 0, 0 */ + 0x19 0 255 0 0>; + + parade,vkeys_x = <720>; + parade,vkeys_y = <1280>; + + parade,virtual_keys = /* KeyCode CenterX CenterY Width Height */ + /* KEY_BACK */ + <158 90 1360 160 180 + /* KEY_MENU */ + 139 270 1360 160 180 + /* KEY_HOMEPAGE */ + 172 450 1360 160 180 + /* KEY SEARCH */ + 217 630 1360 160 180>; + }; + + parade,btn { + parade,name = "pt_btn"; + + parade,inp_dev_name = "pt_btn"; + }; + + parade,proximity { + parade,name = "pt_proximity"; + + parade,inp_dev_name = "pt_proximity"; + parade,abs = + <0x19 0 1 0 0>; + }; + }; + }; +}; + &qupv3_se6_2uart { status = "ok"; }; From b75dcf7cb8244865ed39642b2345a90eb60dd794 Mon Sep 17 00:00:00 2001 From: lixiang Date: Fri, 30 Sep 2022 17:29:26 +0800 Subject: [PATCH 26/65] ARM: dts: msm: Add HAB support for the Auto GVMs Add HAB device node for Auto GVMs for clients. Change-Id: I340189d635bbb1ec0165c3c09d1a70cdc486294b --- qcom/quin-vm-common.dtsi | 89 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/qcom/quin-vm-common.dtsi b/qcom/quin-vm-common.dtsi index 55b31f2d..6c76233d 100644 --- a/qcom/quin-vm-common.dtsi +++ b/qcom/quin-vm-common.dtsi @@ -83,6 +83,95 @@ }; }; + hab: qcom,hab { + compatible = "qcom,hab"; + vmid = <2>; + + mmidgrp100: mmidgrp100 { + grp-start-id = <100>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp200: mmidgrp200 { + grp-start-id = <200>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp300: mmidgrp300 { + grp-start-id = <300>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp400: mmidgrp400 { + grp-start-id = <400>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp500: mmidgrp500 { + grp-start-id = <500>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp600: mmidgrp600 { + grp-start-id = <600>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp700: mmidgrp700 { + grp-start-id = <700>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp800: mmidgrp800 { + grp-start-id = <800>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp900: mmidgrp900 { + grp-start-id = <900>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp1000: mmidgrp1000 { + grp-start-id = <1000>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp1100: mmidgrp1100 { + grp-start-id = <1100>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp1200: mmidgrp1200 { + grp-start-id = <1200>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp1400: mmidgrp1400 { + grp-start-id = <1400>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp1500: mmidgrp1500 { + grp-start-id = <1500>; + role = "fe"; + remote-vmids = <0>; + }; + }; + qcom,msm-imem@14680000 { compatible = "qcom,msm-imem"; reg = <0x14680000 0x1000>; From afc104fcdfa01dd6f1ee9a325c0e019c4b9a74b9 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Thu, 29 Sep 2022 17:00:07 +0530 Subject: [PATCH 27/65] ARM: dts: msm: Update RPMHCC node for sdxpinn Update RPMHCC node for sdxpinn platform. Change-Id: I8ddf57c2789bea02220ae8cb6146b6b37b66bed4 --- qcom/sdxpinn-rumi.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxpinn-rumi.dtsi b/qcom/sdxpinn-rumi.dtsi index 17e29c75..25d8a6f4 100644 --- a/qcom/sdxpinn-rumi.dtsi +++ b/qcom/sdxpinn-rumi.dtsi @@ -211,7 +211,7 @@ }; &rpmhcc { - compatible = "fixed-clock"; + compatible = "qcom,dummycc"; clock-output-names = "rpmh_clocks"; }; From f69d1a4881279ca02feffad83ceeb2f7527107e3 Mon Sep 17 00:00:00 2001 From: Jeyaprabu J Date: Wed, 28 Sep 2022 16:35:49 +0530 Subject: [PATCH 28/65] ARM: dts: msm: Add compatible string for kgsl_smmu Add qcom,adreno-smmu compatible string for kgsl_smmu node. msm kgsl driver checks for this compatible string to enable per-process pagetables. Change-Id: I3a6ae9413c8eeb1102b1bf3c1fe4eb276da23abb --- qcom/msm-arm-smmu-sm8150-v2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/msm-arm-smmu-sm8150-v2.dtsi b/qcom/msm-arm-smmu-sm8150-v2.dtsi index f1bc17f9..0a438d2d 100644 --- a/qcom/msm-arm-smmu-sm8150-v2.dtsi +++ b/qcom/msm-arm-smmu-sm8150-v2.dtsi @@ -2,7 +2,7 @@ &soc { kgsl_smmu: kgsl-smmu@2ca0000 { - compatible = "qcom,qsmmu-v500"; + compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu"; reg = <0x2ca0000 0x10000>, <0x2cc2000 0x20>; reg-names = "base", "tcu-base"; From be2971c2b46f73a956b77a5fe468c5b3f5b5c08b Mon Sep 17 00:00:00 2001 From: Visweswara Tanuku Date: Mon, 5 Sep 2022 20:26:07 -0700 Subject: [PATCH 29/65] ARM: dts: msm: Add QUPV3 SE dtsi entries for sdxpinn Added dt node entries of UART, I2C, SPI, GSI for sdxpinn. Change-Id: I6437d039283ec025d7137d8d077dd7aa7dcb2e96 --- qcom/sdxpinn-pinctrl.dtsi | 783 +++++++++++++++++++++++++++++++++++++- qcom/sdxpinn-qupv3.dtsi | 374 +++++++++++++++++- qcom/sdxpinn.dtsi | 1 + 3 files changed, 1155 insertions(+), 3 deletions(-) diff --git a/qcom/sdxpinn-pinctrl.dtsi b/qcom/sdxpinn-pinctrl.dtsi index d56e0874..184fd03f 100644 --- a/qcom/sdxpinn-pinctrl.dtsi +++ b/qcom/sdxpinn-pinctrl.dtsi @@ -3,7 +3,7 @@ qupv3_se1_2uart_tx_active: qupv3_se1_2uart_tx_active { mux { pins = "gpio12"; - function = "qup_se1_l2"; + function = "qup_se1_l2_mira"; }; config { @@ -16,7 +16,7 @@ qupv3_se1_2uart_rx_active: qupv3_se1_2uart_rx_active { mux { pins = "gpio13"; - function = "qup_se1_l3"; + function = "qup_se1_l3_mira"; }; config { @@ -40,6 +40,785 @@ }; }; + qupv3_se3_4uart_pins: qupv3_se3_4uart_pins { + qupv3_se3_default_cts: qupv3_se3_default_cts { + mux { + pins = "gpio52"; + function = "gpio"; + }; + + config { + pins = "gpio52"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se3_default_rts: qupv3_se3_default_rts { + mux { + pins = "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se3_default_tx: qupv3_se3_default_tx { + mux { + pins = "gpio54"; + function = "gpio"; + }; + + config { + pins = "gpio54"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_default_rx: qupv3_se3_default_rx { + mux { + pins = "gpio55"; + function = "gpio"; + }; + + config { + pins = "gpio55"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se3_cts: qupv3_se3_cts { + mux { + pins = "gpio52"; + function = "qup_se3_l0"; + }; + + config { + pins = "gpio52"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se3_rts: qupv3_se3_rts { + mux { + pins = "gpio53"; + function = "qup_se3_l1"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se3_tx: qupv3_se3_tx { + mux { + pins = "gpio54"; + function = "qup_se3_l2"; + }; + + config { + pins = "gpio54"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_rx: qupv3_se3_rx { + mux { + pins = "gpio55"; + function = "qup_se3_l3"; + }; + + config { + pins = "gpio55"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_sda_active: qupv3_se0_i2c_sda_active { + mux { + pins = "gpio8"; + function = "qup_se0_l0"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_i2c_scl_active: qupv3_se0_i2c_scl_active { + mux { + pins = "gpio9"; + function = "qup_se0_l1"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio8", "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se0_spi_pins: qupv3_se0_spi_pins { + qupv3_se0_spi_miso_active: qupv3_se0_spi_miso_active { + mux { + pins = "gpio8"; + function = "qup_se0_l0"; + }; + + config { + pins = "gpio8"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se0_spi_mosi_active: qupv3_se0_spi_mosi_active { + mux { + pins = "gpio9"; + function = "qup_se0_l1"; + }; + + config { + pins = "gpio9"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se0_spi_clk_active: qupv3_se0_spi_clk_active { + mux { + pins = "gpio10"; + function = "qup_se0_l2"; + }; + + config { + pins = "gpio10"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se0_spi_cs_active: qupv3_se0_spi_cs_active { + mux { + pins = "gpio11"; + function = "qup_se0_l3"; + }; + + config { + pins = "gpio11"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_sda_active: qupv3_se2_i2c_sda_active { + mux { + pins = "gpio14"; + function = "qup_se2_l0"; + }; + + config { + pins = "gpio14"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se2_i2c_scl_active: qupv3_se2_i2c_scl_active { + mux { + pins = "gpio15"; + function = "qup_se2_l1"; + }; + + config { + pins = "gpio15"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio14", "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_miso_active: qupv3_se2_spi_miso_active { + mux { + pins = "gpio14"; + function = "qup_se2_l0"; + }; + + config { + pins = "gpio14"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se2_spi_mosi_active: qupv3_se2_spi_mosi_active { + mux { + pins = "gpio15"; + function = "qup_se2_l1"; + }; + + config { + pins = "gpio15"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se2_spi_clk_active: qupv3_se2_spi_clk_active { + mux { + pins = "gpio16"; + function = "qup_se2_l2"; + }; + + config { + pins = "gpio16"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se2_spi_cs_active: qupv3_se2_spi_cs_active { + mux { + pins = "gpio17"; + function = "qup_se2_l3"; + }; + + config { + pins = "gpio17"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio14", "gpio15", + "gpio16", "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio14", "gpio15", + "gpio16", "gpio17"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { + qupv3_se3_i2c_sda_active: qupv3_se3_i2c_sda_active { + mux { + pins = "gpio52"; + function = "qup_se3_l0"; + }; + + config { + pins = "gpio52"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_i2c_scl_active: qupv3_se3_i2c_scl_active { + mux { + pins = "gpio53"; + function = "qup_se3_l1"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep { + mux { + pins = "gpio52", "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio52", "gpio53"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se3_spi_pins: qupv3_se3_spi_pins { + qupv3_se3_spi_miso_active: qupv3_se3_spi_miso_active { + mux { + pins = "gpio52"; + function = "qup_se3_l0"; + }; + + config { + pins = "gpio52"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se3_spi_mosi_active: qupv3_se3_spi_mosi_active { + mux { + pins = "gpio53"; + function = "qup_se3_l1"; + }; + + config { + pins = "gpio53"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se3_spi_clk_active: qupv3_se3_spi_clk_active { + mux { + pins = "gpio54"; + function = "qup_se3_l2"; + }; + + config { + pins = "gpio54"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se3_spi_cs_active: qupv3_se3_spi_cs_active { + mux { + pins = "gpio55"; + function = "qup_se3_l3"; + }; + + config { + pins = "gpio55"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se3_spi_sleep: qupv3_se3_spi_sleep { + mux { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + function = "gpio"; + }; + + config { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se4_2uart_pins: qupv3_se4_2uart_pins { + qupv3_se4_2uart_tx_active: qupv3_se4_2uart_tx_active { + mux { + pins = "gpio64"; + function = "qup_se4_l2"; + }; + + config { + pins = "gpio64"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se4_2uart_rx_active: qupv3_se4_2uart_rx_active { + mux { + pins = "gpio65"; + function = "qup_se4_l3"; + }; + + config { + pins = "gpio65"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se4_2uart_sleep: qupv3_se4_2uart_sleep { + mux { + pins = "gpio64", "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio64", "gpio65"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { + qupv3_se5_i2c_sda_active: qupv3_se5_i2c_sda_active { + mux { + pins = "gpio110"; + function = "qup_se5_l0"; + }; + + config { + pins = "gpio110"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se5_i2c_scl_active: qupv3_se5_i2c_scl_active { + mux { + pins = "gpio111"; + function = "qup_se5_l1"; + }; + + config { + pins = "gpio111"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep { + mux { + pins = "gpio110", "gpio111"; + function = "gpio"; + }; + + config { + pins = "gpio110", "gpio111"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { + qupv3_se6_i2c_sda_active: qupv3_se6_i2c_sda_active { + mux { + pins = "gpio112"; + function = "qup_se6_l0"; + }; + + config { + pins = "gpio112"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se6_i2c_scl_active: qupv3_se6_i2c_scl_active { + mux { + pins = "gpio113"; + function = "qup_se6_l1"; + }; + + config { + pins = "gpio113"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { + mux { + pins = "gpio112", "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio112", "gpio113"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se6_spi_pins: qupv3_se6_spi_pins { + qupv3_se6_spi_miso_active: qupv3_se6_spi_miso_active { + mux { + pins = "gpio112"; + function = "qup_se6_l0"; + }; + + config { + pins = "gpio112"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se6_spi_mosi_active: qupv3_se6_spi_mosi_active { + mux { + pins = "gpio113"; + function = "qup_se6_l1"; + }; + + config { + pins = "gpio113"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se6_spi_clk_active: qupv3_se6_spi_clk_active { + mux { + pins = "gpio114"; + function = "qup_se6_l2"; + }; + + config { + pins = "gpio114"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se6_spi_cs_active: qupv3_se6_spi_cs_active { + mux { + pins = "gpio115"; + function = "qup_se6_l3"; + }; + + config { + pins = "gpio115"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { + mux { + pins = "gpio112", "gpio113", + "gpio114", "gpio115"; + function = "gpio"; + }; + + config { + pins = "gpio112", "gpio113", + "gpio114", "gpio115"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se7_i2c_pins: qupv3_se7_i2c_pins { + qupv3_se7_i2c_sda_active: qupv3_se7_i2c_sda_active { + mux { + pins = "gpio116"; + function = "qup_se7_l0"; + }; + + config { + pins = "gpio116"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se7_i2c_scl_active: qupv3_se7_i2c_scl_active { + mux { + pins = "gpio117"; + function = "qup_se7_l1"; + }; + + config { + pins = "gpio117"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep { + mux { + pins = "gpio116", "gpio117"; + function = "gpio"; + }; + + config { + pins = "gpio116", "gpio117"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se7_spi_pins: qupv3_se7_spi_pins { + qupv3_se7_spi_miso_active: qupv3_se7_spi_miso_active { + mux { + pins = "gpio116"; + function = "qup_se7_l0"; + }; + + config { + pins = "gpio116"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se7_spi_mosi_active: qupv3_se7_spi_mosi_active { + mux { + pins = "gpio117"; + function = "qup_se7_l1"; + }; + + config { + pins = "gpio117"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se7_spi_clk_active: qupv3_se7_spi_clk_active { + mux { + pins = "gpio118"; + function = "qup_se7_l2"; + }; + + config { + pins = "gpio118"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se7_spi_cs_active: qupv3_se7_spi_cs_active { + mux { + pins = "gpio119"; + function = "qup_se7_l3"; + }; + + config { + pins = "gpio119"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se7_spi_sleep: qupv3_se7_spi_sleep { + mux { + pins = "gpio116", "gpio117", + "gpio118", "gpio119"; + function = "gpio"; + }; + + config { + pins = "gpio116", "gpio117", + "gpio118", "gpio119"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se8_2uart_pins: qupv3_se8_2uart_pins { + qupv3_se8_2uart_tx_active: qupv3_se8_2uart_tx_active { + mux { + pins = "gpio124"; + function = "qup_se8_l2"; + }; + + config { + pins = "gpio124"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se8_2uart_rx_active: qupv3_se8_2uart_rx_active { + mux { + pins = "gpio125"; + function = "qup_se8_l3"; + }; + + config { + pins = "gpio125"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se8_2uart_sleep: qupv3_se8_2uart_sleep { + mux { + pins = "gpio124", "gpio125"; + function = "gpio"; + }; + + config { + pins = "gpio124", "gpio125"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + sdc1_on: sdc1_on { clk { pins = "sdc1_clk"; diff --git a/qcom/sdxpinn-qupv3.dtsi b/qcom/sdxpinn-qupv3.dtsi index 808caa83..6b5d3a59 100644 --- a/qcom/sdxpinn-qupv3.dtsi +++ b/qcom/sdxpinn-qupv3.dtsi @@ -1,4 +1,44 @@ &soc { + /* QUPv3 SE Instances + * Qup0 0: SE 0 + * Qup0 1: SE 1 + * Qup0 2: SE 2 + * Qup0 3: SE 3 + * Qup0 4: SE 4 + * Qup0 5: SE 5 + * Qup0 6: SE 6 + * Qup0 7: SE 7 + * Qup0 8: SE 8 + */ + + /* GPI Instance */ + gpi_dma0: qcom,gpi-dma@900000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0x900000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0xf6 0x0>; + qcom,max-num-gpii = <12>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,gpii-mask = <0xfff>; + qcom,ev-factor = <2>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + qcom,gpi-ee-offset = <0x10000>; + dma-coherent; + status = "ok"; + }; + /* QUPv3_0 wrapper instance */ qupv3_0: qcom,qupv3_0_geni_se@9c0000 { compatible = "qcom,geni-se-qup"; @@ -8,10 +48,15 @@ clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus = <&apps_smmu 0xe3 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + dma-coherent; ranges; status = "ok"; - /*PORed Debug UART Instance */ + /* PORed Debug UART Instance */ qupv3_se1_2uart: qcom,qup_uart@984000 { compatible = "qcom,geni-debug-uart"; reg = <0x984000 0x4000>; @@ -19,10 +64,337 @@ interrupts = ; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se1_2uart_tx_active>, <&qupv3_se1_2uart_rx_active>; pinctrl-1 = <&qupv3_se1_2uart_sleep>; status = "disabled"; }; + + /* HS UART Instance */ + qupv3_se3_4uart: qcom,qup_uart@98c000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x98c000 0x4000>; + reg-names = "se_phys"; + interrupts-extended = <&intc GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 55 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "active", "sleep", "shutdown"; + pinctrl-0 = <&qupv3_se3_default_cts>, <&qupv3_se3_default_rts>, + <&qupv3_se3_default_tx>, <&qupv3_se3_default_rx>; + pinctrl-1 = <&qupv3_se3_cts>, <&qupv3_se3_rts>, + <&qupv3_se3_tx>, <&qupv3_se3_rx>; + pinctrl-2 = <&qupv3_se3_cts>, <&qupv3_se3_rts>, + <&qupv3_se3_tx>, <&qupv3_se3_default_rx>; + pinctrl-3 = <&qupv3_se3_default_cts>, <&qupv3_se3_default_rts>, + <&qupv3_se3_default_tx>, <&qupv3_se3_default_rx>; + qcom,wakeup-byte = <0xFD>; + status = "disabled"; + }; + + qupv3_se0_i2c: i2c@980000 { + compatible = "qcom,i2c-geni"; + reg = <0x980000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + dmas = <&gpi_dma0 0 0 3 64 0>, + <&gpi_dma0 1 0 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se0_spi: spi@980000 { + compatible = "qcom,spi-geni"; + reg = <0x980000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_mosi_active>, <&qupv3_se0_spi_miso_active>, + <&qupv3_se0_spi_clk_active>, <&qupv3_se0_spi_cs_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + dmas = <&gpi_dma0 0 0 1 64 0>, + <&gpi_dma0 1 0 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@988000 { + compatible = "qcom,i2c-geni"; + reg = <0x988000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_sda_active>, <&qupv3_se2_i2c_scl_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + dmas = <&gpi_dma0 0 2 3 64 0>, + <&gpi_dma0 1 2 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se2_spi: spi@988000 { + compatible = "qcom,spi-geni"; + reg = <0x988000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_mosi_active>, <&qupv3_se2_spi_miso_active>, + <&qupv3_se2_spi_clk_active>, <&qupv3_se2_spi_cs_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + dmas = <&gpi_dma0 0 2 1 64 0>, + <&gpi_dma0 1 2 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se3_i2c: i2c@98c000 { + compatible = "qcom,i2c-geni"; + reg = <0x98c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_i2c_sda_active>, <&qupv3_se3_i2c_scl_active>; + pinctrl-1 = <&qupv3_se3_i2c_sleep>; + dmas = <&gpi_dma0 0 3 3 64 0>, + <&gpi_dma0 1 3 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se3_spi: spi@98c000 { + compatible = "qcom,spi-geni"; + reg = <0x98c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_spi_mosi_active>, <&qupv3_se3_spi_miso_active>, + <&qupv3_se3_spi_clk_active>, <&qupv3_se3_spi_cs_active>; + pinctrl-1 = <&qupv3_se3_spi_sleep>; + dmas = <&gpi_dma0 0 3 1 64 0>, + <&gpi_dma0 1 3 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* CV2X UART1 Instance */ + qupv3_se4_2uart: qcom,qup_uart@990000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x990000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_2uart_tx_active>, <&qupv3_se4_2uart_rx_active>; + pinctrl-1 = <&qupv3_se4_2uart_sleep>; + status = "disabled"; + }; + + qupv3_se5_i2c: i2c@994000 { + compatible = "qcom,i2c-geni"; + reg = <0x994000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_i2c_sda_active>, <&qupv3_se5_i2c_scl_active>; + pinctrl-1 = <&qupv3_se5_i2c_sleep>; + dmas = <&gpi_dma0 0 5 3 64 0>, + <&gpi_dma0 1 5 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se6_i2c: i2c@998000 { + compatible = "qcom,i2c-geni"; + reg = <0x998000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_i2c_sda_active>, <&qupv3_se6_i2c_scl_active>; + pinctrl-1 = <&qupv3_se6_i2c_sleep>; + dmas = <&gpi_dma0 0 6 3 64 0>, + <&gpi_dma0 1 6 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se6_spi: spi@998000 { + compatible = "qcom,spi-geni"; + reg = <0x998000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_spi_mosi_active>, <&qupv3_se6_spi_miso_active>, + <&qupv3_se6_spi_clk_active>, <&qupv3_se6_spi_cs_active>; + pinctrl-1 = <&qupv3_se6_spi_sleep>; + dmas = <&gpi_dma0 0 6 1 64 0>, + <&gpi_dma0 1 6 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se7_i2c: i2c@99c000 { + compatible = "qcom,i2c-geni"; + reg = <0x99c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_i2c_sda_active>, <&qupv3_se7_i2c_scl_active>; + pinctrl-1 = <&qupv3_se7_i2c_sleep>; + dmas = <&gpi_dma0 0 7 3 64 0>, + <&gpi_dma0 1 7 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se7_spi: spi@99c000 { + compatible = "qcom,spi-geni"; + reg = <0x99c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_spi_mosi_active>, <&qupv3_se7_spi_miso_active>, + <&qupv3_se7_spi_clk_active>, <&qupv3_se7_spi_cs_active>; + pinctrl-1 = <&qupv3_se7_spi_sleep>; + dmas = <&gpi_dma0 0 7 1 64 0>, + <&gpi_dma0 1 7 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* CV2X UART2 Instance */ + qupv3_se8_2uart: qcom,qup_uart@9a0000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x9a0000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_QUP_0>, + <&system_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_2uart_tx_active>, <&qupv3_se8_2uart_rx_active>; + pinctrl-1 = <&qupv3_se8_2uart_sleep>; + status = "disabled"; + }; }; }; diff --git a/qcom/sdxpinn.dtsi b/qcom/sdxpinn.dtsi index 82631d0d..050d9cc1 100644 --- a/qcom/sdxpinn.dtsi +++ b/qcom/sdxpinn.dtsi @@ -27,6 +27,7 @@ aliases { serial0 = &qupv3_se1_2uart; + hsuart0 = &qupv3_se3_4uart; mmc0 = &sdhc_1; /*SDC1 eMMC slot*/ mmc1 = &sdhc_2; /* SDC2 SD card slot */ }; From b6bcb4082beedbe0864dd945e9034a7b36cd6b34 Mon Sep 17 00:00:00 2001 From: Can Guo Date: Sun, 2 Oct 2022 06:21:57 -0700 Subject: [PATCH 30/65] ARM: dts: msm: Correct PCIe EP's mhi-soc-reset-offset on sdxpinn Correct PCIe EP's mhi-soc-reset-offset on sdxpinn. Change-Id: Ic5c26c96a703b7871a2ddbce2e3cea83b4475d4d --- qcom/sdxpinn.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxpinn.dtsi b/qcom/sdxpinn.dtsi index 82631d0d..d8acd822 100644 --- a/qcom/sdxpinn.dtsi +++ b/qcom/sdxpinn.dtsi @@ -1079,7 +1079,7 @@ qcom,pcie-aggregated-irq; qcom,pcie-mhi-a7-irq; qcom,phy-status-reg2 = <0x1214>; - qcom,mhi-soc-reset-offset = <0xb01b8>; + qcom,mhi-soc-reset-offset = <0xb001b8>; qcom,aoss-rst-clr; qcom,aux-clk = <0x13>; From 8d62d95b6eca5894b6fe0bceac931b3819e2fec2 Mon Sep 17 00:00:00 2001 From: Aniket Randive Date: Fri, 30 Sep 2022 10:50:45 +0530 Subject: [PATCH 31/65] ARM: dts: msm: Add pinctrl node for UART Add pinctrl node for UART which is missed for SA410M target. Change-Id: Ie5466ce2e9ae493733106f6ca17d093cd7601034 --- qcom/sa410m-pinctrl.dtsi | 106 +++++++++++++++++++++++++++++++++++++++ qcom/sa410m-qupv3.dtsi | 40 +++++++-------- 2 files changed, 126 insertions(+), 20 deletions(-) diff --git a/qcom/sa410m-pinctrl.dtsi b/qcom/sa410m-pinctrl.dtsi index db93d342..ce0b7470 100644 --- a/qcom/sa410m-pinctrl.dtsi +++ b/qcom/sa410m-pinctrl.dtsi @@ -109,6 +109,112 @@ }; }; + qupv3_se0_4uart_pins: qupv3_se0_4uart_pins { + qupv3_se0_default_cts: qupv3_se0_default_cts { + mux { + pins = "gpio0"; + function = "gpio"; + }; + + config { + pins = "gpio0"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se0_default_rts: qupv3_se0_default_rts { + mux { + pins = "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio1"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se0_default_tx: qupv3_se0_default_tx { + mux { + pins = "gpio2"; + function = "gpio"; + }; + + config { + pins = "gpio2"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_default_rx: qupv3_se0_default_rx { + mux { + pins = "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio3"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se0_cts: qupv3_se0_cts { + mux { + pins = "gpio0"; + function = "qup0_se0_l0"; + }; + + config { + pins = "gpio0"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se0_rts: qupv3_se0_rts { + mux { + pins = "gpio1"; + function = "qup0_se0_l1"; + }; + + config { + pins = "gpio1"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se0_tx: qupv3_se0_tx { + mux { + pins = "gpio2"; + function = "qup0_se0_l2"; + }; + + config { + pins = "gpio2"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_rx: qupv3_se0_rx { + mux { + pins = "gpio3"; + function = "qup0_se0_l3"; + }; + + config { + pins = "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { qupv3_se1_i2c_sda_active: qupv3_se1_i2c_sda_active { mux { diff --git a/qcom/sa410m-qupv3.dtsi b/qcom/sa410m-qupv3.dtsi index d96903a1..cf6bfdad 100644 --- a/qcom/sa410m-qupv3.dtsi +++ b/qcom/sa410m-qupv3.dtsi @@ -71,8 +71,8 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, - <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + <&bimc_noc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&sys_noc MASTER_QUP_0 &bimc_noc SLAVE_EBI_CH0>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>; pinctrl-1 = <&qupv3_se0_i2c_sleep>; @@ -94,8 +94,8 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, - <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + <&bimc_noc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&sys_noc MASTER_QUP_0 &bimc_noc SLAVE_EBI_CH0>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se0_spi_mosi_active>, <&qupv3_se0_spi_miso_active>, <&qupv3_se0_spi_clk_active>, <&qupv3_se0_spi_cs_active>; @@ -117,8 +117,8 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, - <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + <&bimc_noc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&sys_noc MASTER_QUP_0 &bimc_noc SLAVE_EBI_CH0>; pinctrl-names = "default", "active", "sleep", "shutdown"; pinctrl-0 = <&qupv3_se0_default_cts>, <&qupv3_se0_default_rts>, <&qupv3_se0_default_tx>, <&qupv3_se0_default_rx>; @@ -142,8 +142,8 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, - <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + <&bimc_noc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&sys_noc MASTER_QUP_0 &bimc_noc SLAVE_EBI_CH0>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se1_i2c_sda_active>, <&qupv3_se1_i2c_scl_active>; pinctrl-1 = <&qupv3_se1_i2c_sleep>; @@ -165,8 +165,8 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, - <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + <&bimc_noc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&sys_noc MASTER_QUP_0 &bimc_noc SLAVE_EBI_CH0>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se1_spi_mosi_active>, <&qupv3_se1_spi_miso_active>, <&qupv3_se1_spi_clk_active>, <&qupv3_se1_spi_cs_active>; @@ -189,8 +189,8 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, - <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + <&bimc_noc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&sys_noc MASTER_QUP_0 &bimc_noc SLAVE_EBI_CH0>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se2_i2c_sda_active>, <&qupv3_se2_i2c_scl_active>; pinctrl-1 = <&qupv3_se2_i2c_sleep>; @@ -212,8 +212,8 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, - <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + <&bimc_noc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&sys_noc MASTER_QUP_0 &bimc_noc SLAVE_EBI_CH0>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se2_spi_mosi_active>, <&qupv3_se2_spi_miso_active>, <&qupv3_se2_spi_clk_active>, <&qupv3_se2_spi_cs_active>; @@ -236,8 +236,8 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, - <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + <&bimc_noc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&sys_noc MASTER_QUP_0 &bimc_noc SLAVE_EBI_CH0>; pinctrl-names = "default", "active", "sleep", "shutdown"; pinctrl-0 = <&qupv3_se3_default_cts>, <&qupv3_se3_default_rts>, <&qupv3_se3_default_tx>, <&qupv3_se3_default_rx>; @@ -262,8 +262,8 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, - <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + <&bimc_noc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&sys_noc MASTER_QUP_0 &bimc_noc SLAVE_EBI_CH0>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se5_i2c_sda_active>, <&qupv3_se5_i2c_scl_active>; pinctrl-1 = <&qupv3_se5_i2c_sleep>; @@ -285,8 +285,8 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, - <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, - <&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>; + <&bimc_noc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>, + <&sys_noc MASTER_QUP_0 &bimc_noc SLAVE_EBI_CH0>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se5_spi_mosi_active>, <&qupv3_se5_spi_miso_active>, <&qupv3_se5_spi_clk_active>, <&qupv3_se5_spi_cs_active>; From 37da23bcc4632e61d11b52561a7da76ea0720fab Mon Sep 17 00:00:00 2001 From: Aniket Randive Date: Thu, 29 Sep 2022 12:38:52 +0530 Subject: [PATCH 32/65] ARM: dts: msm: Add SPS node for SA410M target Add SPS module to device tree. SPS (Smart Peripheral System) enables the support of all BAMs in the system which provide DMA functionality to various peripherals for SA410M target. Change-Id: I99893b664a5a9d8fe7dbae09db15428442b9a33b --- qcom/sa410m.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/sa410m.dtsi b/qcom/sa410m.dtsi index cdbe4f95..007927a1 100644 --- a/qcom/sa410m.dtsi +++ b/qcom/sa410m.dtsi @@ -453,6 +453,11 @@ }; thermal_zones: thermal-zones { }; + + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; }; #include "sa410m-stub-regulators.dtsi" From 1540b327841149d0fbc2bd9e6fa71c377c392f96 Mon Sep 17 00:00:00 2001 From: Surya Teja Kudiri Date: Fri, 16 Sep 2022 16:41:18 +0530 Subject: [PATCH 33/65] ARM: dts: msm: Correct node entry for parade flag Enabling the parade flag to power mode off on sleep. Change-Id: Ib48fbec26955a5629d27057e4165cd9b159f9ba0 --- qcom/monaco.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 31660e08..be5225ce 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1911,7 +1911,7 @@ * PT_CORE_FLAG_SKIP_RUNTIME = 0x20 * PT_CORE_FLAG_SKIP_RESUME = 0x40 */ - parade,flags = <4>; + parade,flags = <6>; /* PT_CORE_EWG_NONE */ parade,easy_wakeup_gesture = <1>; /* 0:AUTO 1:PIP1_ONLY 2:PIP2_CAPABLE*/ From 783c33347191b3db9e5d41c65989ce3dcb486d72 Mon Sep 17 00:00:00 2001 From: Praveen koya Date: Mon, 3 Oct 2022 11:53:08 +0530 Subject: [PATCH 34/65] ARM: dts: qcom: Add spi node for AON interface Add spi node for AON interface. Change-Id: Ifcb614e548f925c5c021cdb6f09e60e3f27d88d4 --- qcom/slate.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 qcom/slate.dtsi diff --git a/qcom/slate.dtsi b/qcom/slate.dtsi new file mode 100644 index 00000000..b6cfc1e9 --- /dev/null +++ b/qcom/slate.dtsi @@ -0,0 +1,13 @@ +&soc { + qupv3_se4_spi: spi@4a90000 { /* BLSP4 QUP3*/ + status = "ok"; + qcom,shared_ee; + qcom,slate-spi { + compatible = "qcom,slate-spi"; + reg = <0>; + spi-max-frequency = <737000>; + interrupt-parent = <&tlmm>; + qcom,irq-gpio = <&tlmm 95 1>; + }; + }; +}; From 38fc6b015bf8421d3b5797cd90fc14dcfa9af192 Mon Sep 17 00:00:00 2001 From: Dipa Mantre Date: Tue, 27 Sep 2022 08:55:00 -0700 Subject: [PATCH 35/65] ARM: dts: msm: Update support for GCC for SA410M Add the clocks handles for clients to be able to request on them for SA410M. Change-Id: Ibd7f8bab4ff204a729a2a566d56a49d26ffa8ee4 --- qcom/sa410m.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/qcom/sa410m.dtsi b/qcom/sa410m.dtsi index cdbe4f95..878d897b 100644 --- a/qcom/sa410m.dtsi +++ b/qcom/sa410m.dtsi @@ -386,6 +386,20 @@ clock-output-names = "chip_sleep_clk"; #clock-cells = <0>; }; + + pcie_0_pipe_clk: pcie_0_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; + }; + + usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + #clock-cells = <0>; + }; }; rpmcc: clock-controller { From dfa0d5f1d59b3891ea954468de11a8dab8c0effb Mon Sep 17 00:00:00 2001 From: Jyothi Kumar Seerapu Date: Tue, 6 Sep 2022 19:46:33 +0530 Subject: [PATCH 36/65] ARM: dts: msm: Add PCIe PHY settings for sdxpinn PCIe PHY settings of PCIe0, PCIe1 and PCIe2 are added for sdxpinn. Limit PCIe0 to Gen3 speed. Disable port bus driver. Add interconnects and SMMU nodes for PCIe for sdxpinn. Change-Id: I25557629e77f2f34cc3f71191ea86987fb78306f --- qcom/sdxpinn-pcie.dtsi | 405 +++++++++++++++++++++++++++++++++++++++-- qcom/sdxpinn.dtsi | 2 +- 2 files changed, 391 insertions(+), 16 deletions(-) diff --git a/qcom/sdxpinn-pcie.dtsi b/qcom/sdxpinn-pcie.dtsi index a2b9f59e..e1d95457 100644 --- a/qcom/sdxpinn-pcie.dtsi +++ b/qcom/sdxpinn-pcie.dtsi @@ -76,8 +76,8 @@ RPMH_REGULATOR_LEVEL_NOM 100000000>; - //interconnect-names = "icc_path"; - //interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; + interconnect-names = "icc_path"; + interconnects = <&pcie_anoc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; clocks = <&gcc GCC_PCIE_PIPE_CLK>, <&rpmhcc RPMH_CXO_CLK>, @@ -108,9 +108,9 @@ reset-names = "pcie_core_reset", "pcie_phy_reset"; - //qcom,smmu-sid-base = <0x0800>; - //iommu-map = <0x0 &apps_smmu 0x0800 0x1>, - // <0x100 &apps_smmu 0x0801 0x1>; + qcom,smmu-sid-base = <0x0800>; + iommu-map = <0x0 &apps_smmu 0x0800 0x1>, + <0x100 &apps_smmu 0x0801 0x1>; qcom,aux-clk-freq = <20>; /* 19.2 MHz */ qcom,tpwr-on-scale = <1>; @@ -119,6 +119,177 @@ qcom,slv-addr-space-size = <0x4000000>; qcom,ep-latency = <10>; qcom,num-parf-testbus-sel = <0xb9>; + qcom,target-link-speed = <3>; + + qcom,pcie-phy-ver = <100>; + qcom,phy-status-offset = <0x1214>; + qcom,phy-status-bit = <7>; + qcom,phy-power-down-offset = <0x1240>; + qcom,phy-sequence = <0x1240 0x03 0x0 + 0x0030 0x1d 0x0 + 0x0034 0x03 0x0 + 0x0078 0x01 0x0 + 0x007c 0x00 0x0 + 0x0080 0x51 0x0 + 0x00ac 0x34 0x0 + 0x0208 0x0c 0x0 + 0x020c 0x0a 0x0 + 0x0218 0x04 0x0 + 0x0220 0x16 0x0 + 0x0234 0x00 0x0 + 0x029c 0x80 0x0 + 0x02a0 0x7c 0x0 + 0x02b4 0x05 0x0 + 0x02e8 0x0a 0x0 + 0x030c 0x0d 0x0 + 0x0320 0x0b 0x0 + 0x0348 0x1c 0x0 + 0x0388 0x20 0x0 + 0x0394 0x30 0x0 + 0x03dc 0x09 0x0 + 0x03f4 0x14 0x0 + 0x03f8 0xb3 0x0 + 0x03fc 0x58 0x0 + 0x0400 0x9a 0x0 + 0x0404 0x26 0x0 + 0x0408 0xb6 0x0 + 0x040c 0xee 0x0 + 0x0410 0xdb 0x0 + 0x0414 0xdb 0x0 + 0x0418 0xa0 0x0 + 0x041c 0xdf 0x0 + 0x0420 0x78 0x0 + 0x0424 0x76 0x0 + 0x0428 0xff 0x0 + 0x0830 0x1d 0x0 + 0x0834 0x03 0x0 + 0x0878 0x01 0x0 + 0x087c 0x00 0x0 + 0x0880 0x51 0x0 + 0x08ac 0x34 0x0 + 0x0a08 0x0c 0x0 + 0x0a0c 0x0a 0x0 + 0x0a18 0x04 0x0 + 0x0a20 0x16 0x0 + 0x0a34 0x00 0x0 + 0x0a9c 0x80 0x0 + 0x0aa0 0x7c 0x0 + 0x0ab4 0x05 0x0 + 0x0ae8 0x0a 0x0 + 0x0b0c 0x0d 0x0 + 0x0b20 0x0b 0x0 + 0x0b48 0x1c 0x0 + 0x0b88 0x20 0x0 + 0x0b94 0x30 0x0 + 0x0bdc 0x09 0x0 + 0x0bf4 0x14 0x0 + 0x0bf8 0xb3 0x0 + 0x0bfc 0x58 0x0 + 0x0c00 0x9a 0x0 + 0x0c04 0x26 0x0 + 0x0c08 0xb6 0x0 + 0x0c0c 0xee 0x0 + 0x0c10 0xdb 0x0 + 0x0c14 0xdb 0x0 + 0x0c18 0xa0 0x0 + 0x0c1c 0xdf 0x0 + 0x0c20 0x78 0x0 + 0x0c24 0x76 0x0 + 0x0c28 0xff 0x0 + 0x0ea0 0x01 0x0 + 0x0eb4 0x00 0x0 + 0x0ec4 0x00 0x0 + 0x0ec8 0x1f 0x0 + 0x0ed4 0x12 0x0 + 0x0ed8 0x12 0x0 + 0x0edc 0xdb 0x0 + 0x0ee0 0x9a 0x0 + 0x0ee4 0x38 0x0 + 0x0ee8 0xb6 0x0 + 0x0eec 0x64 0x0 + 0x0ef0 0x1f 0x0 + 0x0ef4 0x1f 0x0 + 0x0ef8 0x1f 0x0 + 0x0efc 0x1f 0x0 + 0x0f00 0x1f 0x0 + 0x0f04 0x1f 0x0 + 0x0f0c 0x1f 0x0 + 0x0f14 0x1f 0x0 + 0x0f1c 0x1f 0x0 + 0x0f28 0x5b 0x0 + 0x1000 0x97 0x0 + 0x1004 0x0c 0x0 + 0x1010 0x06 0x0 + 0x1014 0x16 0x0 + 0x1018 0x36 0x0 + 0x101c 0x04 0x0 + 0x1020 0x14 0x0 + 0x1024 0x34 0x0 + 0x1028 0xd0 0x0 + 0x1030 0x55 0x0 + 0x1034 0x55 0x0 + 0x1038 0x05 0x0 + 0x103c 0x12 0x0 + 0x1060 0xde 0x0 + 0x1064 0x07 0x0 + 0x1070 0x06 0x0 + 0x1074 0x16 0x0 + 0x1078 0x36 0x0 + 0x107c 0x0a 0x0 + 0x1080 0x0a 0x0 + 0x1084 0x1a 0x0 + 0x1088 0x82 0x0 + 0x1090 0x55 0x0 + 0x1094 0x55 0x0 + 0x1098 0x03 0x0 + 0x109c 0x00 0x0 + 0x10bc 0x0e 0x0 + 0x10c0 0x01 0x0 + 0x10cc 0x31 0x0 + 0x10d0 0x01 0x0 + 0x10d8 0x40 0x0 + 0x10dc 0x14 0x0 + 0x10e0 0x90 0x0 + 0x10e4 0x82 0x0 + 0x10f4 0x0f 0x0 + 0x1110 0x08 0x0 + 0x1120 0x46 0x0 + 0x1124 0x04 0x0 + 0x1140 0x14 0x0 + 0x1164 0x34 0x0 + 0x1170 0xa0 0x0 + 0x1174 0x06 0x0 + 0x1184 0x88 0x0 + 0x1188 0x14 0x0 + 0x1198 0x0f 0x0 + 0x1378 0x2e 0x0 + 0x1390 0xcc 0x0 + 0x13f8 0x00 0x0 + 0x13fc 0x22 0x0 + 0x141c 0xc1 0x0 + 0x129c 0x83 0x0 + 0x12a0 0x09 0x0 + 0x12a4 0xa2 0x0 + 0x1450 0x03 0x0 + 0x1490 0x00 0x0 + 0x14a0 0x16 0x0 + 0x1508 0x02 0x0 + 0x155c 0x2e 0x0 + 0x157c 0x03 0x0 + 0x1584 0x28 0x0 + 0x13dc 0x04 0x0 + 0x13e0 0x02 0x0 + 0x1418 0xc0 0x0 + 0x140c 0x1d 0x0 + 0x158c 0x0f 0x0 + 0x15ac 0xf2 0x0 + 0x15c0 0xf2 0x0 + 0x1828 0x00 0x0 + 0x1c28 0x00 0x0 + 0x1e24 0x00 0x0 + 0x1e28 0x00 0x0 + 0x1200 0x00 0x0 + 0x1244 0x03 0x0>; pcie0_rp: pcie0_rp { reg = <0 0 0 0 0>; @@ -212,8 +383,8 @@ RPMH_REGULATOR_LEVEL_LOW_SVS 100000000>; - //interconnect-names = "icc_path"; - //interconnects = <&system_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>; + interconnect-names = "icc_path"; + interconnects = <&pcie_anoc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>; clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&rpmhcc RPMH_CXO_CLK>, @@ -244,9 +415,9 @@ reset-names = "pcie_1_core_reset", "pcie_1_phy_reset"; - //qcom,smmu-sid-base = <0x0880>; - //iommu-map = <0x0 &apps_smmu 0x0880 0x1>, - // <0x100 &apps_smmu 0x0881 0x1>; + qcom,smmu-sid-base = <0x0880>; + iommu-map = <0x0 &apps_smmu 0x0880 0x1>, + <0x100 &apps_smmu 0x0881 0x1>; qcom,aux-clk-freq = <20>; /* 19.2 MHz */ qcom,tpwr-on-scale = <1>; @@ -256,6 +427,124 @@ qcom,ep-latency = <10>; qcom,num-parf-testbus-sel = <0xb9>; + qcom,pcie-phy-ver = <101>; + qcom,phy-status-offset = <0x214>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x240>; + qcom,phy-sequence = <0x0240 0x03 0x0 + 0x00c0 0x01 0x0 + 0x00cc 0x31 0x0 + 0x00d0 0x01 0x0 + 0x0060 0xff 0x0 + 0x0064 0x06 0x0 + 0x0000 0x4c 0x0 + 0x0004 0x06 0x0 + 0x00e0 0x90 0x0 + 0x00e4 0x82 0x0 + 0x00f4 0x07 0x0 + 0x0070 0x02 0x0 + 0x0010 0x02 0x0 + 0x0074 0x16 0x0 + 0x0014 0x16 0x0 + 0x0078 0x36 0x0 + 0x0018 0x36 0x0 + 0x0110 0x08 0x0 + 0x00bc 0x0e 0x0 + 0x0120 0x42 0x0 + 0x0080 0x0a 0x0 + 0x0084 0x1a 0x0 + 0x0020 0x14 0x0 + 0x0024 0x34 0x0 + 0x0088 0x82 0x0 + 0x0028 0x68 0x0 + 0x0090 0xab 0x0 + 0x0094 0xea 0x0 + 0x0098 0x02 0x0 + 0x0030 0xab 0x0 + 0x0034 0xaa 0x0 + 0x0038 0x02 0x0 + 0x0140 0x14 0x0 + 0x0164 0x34 0x0 + 0x003c 0x01 0x0 + 0x001c 0x04 0x0 + 0x0174 0x16 0x0 + 0x01bc 0x0f 0x0 + 0x0170 0xa0 0x0 + 0x11a4 0x38 0x0 + 0x10dc 0x11 0x0 + 0x1160 0xbf 0x0 + 0x1164 0xbf 0x0 + 0x1168 0xb7 0x0 + 0x116c 0xea 0x0 + 0x115c 0x3f 0x0 + 0x1174 0x5c 0x0 + 0x1178 0x9c 0x0 + 0x117c 0x1a 0x0 + 0x1180 0x89 0x0 + 0x1170 0xdc 0x0 + 0x1188 0x94 0x0 + 0x118c 0x5b 0x0 + 0x1190 0x1a 0x0 + 0x1194 0x89 0x0 + 0x10cc 0x00 0x0 + 0x1008 0x09 0x0 + 0x1014 0x05 0x0 + 0x104c 0x08 0x0 + 0x1050 0x08 0x0 + 0x10d8 0x0f 0x0 + 0x1118 0x1c 0x0 + 0x10f8 0x07 0x0 + 0x11f8 0x08 0x0 + 0x0e84 0x15 0x0 + 0x0e90 0x3f 0x0 + 0x0ee4 0x02 0x0 + 0x0e40 0x06 0x0 + 0x0e3c 0x18 0x0 + 0x19a4 0x38 0x0 + 0x18dc 0x11 0x0 + 0x1960 0xbf 0x0 + 0x1964 0xbf 0x0 + 0x1968 0xb7 0x0 + 0x196c 0xea 0x0 + 0x195c 0x3f 0x0 + 0x1974 0x5c 0x0 + 0x1978 0x9c 0x0 + 0x197c 0x1a 0x0 + 0x1980 0x89 0x0 + 0x1970 0xdc 0x0 + 0x1988 0x94 0x0 + 0x198c 0x5b 0x0 + 0x1990 0x1a 0x0 + 0x1994 0x89 0x0 + 0x18cc 0x00 0x0 + 0x1808 0x09 0x0 + 0x1814 0x05 0x0 + 0x184c 0x08 0x0 + 0x1850 0x08 0x0 + 0x18d8 0x0f 0x0 + 0x1918 0x1c 0x0 + 0x18f8 0x07 0x0 + 0x19f8 0x08 0x0 + 0x1684 0x15 0x0 + 0x1690 0x3f 0x0 + 0x16e4 0x02 0x0 + 0x1640 0x06 0x0 + 0x163c 0x18 0x0 + 0x02dc 0x05 0x0 + 0x0388 0x77 0x0 + 0x0398 0x0b 0x0 + 0x06a4 0x1e 0x0 + 0x03e0 0x0f 0x0 + 0x060c 0x1d 0x0 + 0x0614 0x07 0x0 + 0x0620 0xc1 0x0 + 0x0694 0x00 0x0 + 0x03d0 0x8c 0x0 + 0x1424 0x00 0x0 + 0x1428 0x00 0x0 + 0x0200 0x00 0x0 + 0x0244 0x03 0x0>; + pcie1_rp: pcie1_rp { reg = <0 0 0 0 0>; @@ -349,8 +638,8 @@ RPMH_REGULATOR_LEVEL_LOW_SVS 100000000>; - //interconnect-names = "icc_path"; - //interconnects = <&system_noc MASTER_PCIE_2 &mc_virt SLAVE_EBI1>; + interconnect-names = "icc_path"; + interconnects = <&pcie_anoc MASTER_PCIE_2 &mc_virt SLAVE_EBI1>; clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, <&rpmhcc RPMH_CXO_CLK>, @@ -381,9 +670,9 @@ reset-names = "pcie_2_core_reset", "pcie_2_phy_reset"; - //qcom,smmu-sid-base = <0x0900>; - //iommu-map = <0x0 &apps_smmu 0x0900 0x1>, - // <0x100 &apps_smmu 0x0901 0x1>; + qcom,smmu-sid-base = <0x0900>; + iommu-map = <0x0 &apps_smmu 0x0900 0x1>, + <0x100 &apps_smmu 0x0901 0x1>; qcom,aux-clk-freq = <20>; /* 19.2 MHz */ qcom,tpwr-on-scale = <1>; @@ -393,6 +682,92 @@ qcom,ep-latency = <10>; qcom,num-parf-testbus-sel = <0xb9>; + qcom,pcie-phy-ver = <001>; + qcom,phy-status-offset = <0x214>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x240>; + qcom,phy-sequence = <0x0240 0x03 0x0 + 0x0000 0x4c 0x0 + 0x0004 0x06 0x0 + 0x0010 0x02 0x0 + 0x0014 0x16 0x0 + 0x0018 0x36 0x0 + 0x001c 0x04 0x0 + 0x0020 0x14 0x0 + 0x0024 0x34 0x0 + 0x0028 0x68 0x0 + 0x0030 0xab 0x0 + 0x0034 0xaa 0x0 + 0x0038 0x02 0x0 + 0x003c 0x01 0x0 + 0x0060 0xde 0x0 + 0x0064 0x07 0x0 + 0x0070 0x02 0x0 + 0x0074 0x16 0x0 + 0x0078 0x36 0x0 + 0x0080 0x0a 0x0 + 0x0084 0x1a 0x0 + 0x0088 0x82 0x0 + 0x0090 0x55 0x0 + 0x0094 0x55 0x0 + 0x0098 0x03 0x0 + 0x00bc 0x0e 0x0 + 0x00c0 0x00 0x0 + 0x00cc 0x31 0x0 + 0x00d0 0x01 0x0 + 0x00e0 0x90 0x0 + 0x00e4 0x82 0x0 + 0x00f4 0x07 0x0 + 0x0110 0x04 0x0 + 0x0120 0x42 0x0 + 0x0140 0x14 0x0 + 0x0164 0x34 0x0 + 0x0170 0xa0 0x0 + 0x0174 0x16 0x0 + 0x01bc 0x0f 0x0 + 0x02dc 0x05 0x0 + 0x0388 0x77 0x0 + 0x0398 0x0b 0x0 + 0x03e0 0x0f 0x0 + 0x060c 0x1d 0x0 + 0x061c 0x8c 0x0 + 0x0620 0xc1 0x0 + 0x0654 0x00 0x0 + 0x0694 0x00 0x0 + 0x0e3c 0x17 0x0 + 0x0e40 0x06 0x0 + 0x0e84 0x15 0x0 + 0x0e90 0x3f 0x0 + 0x0ee4 0x02 0x0 + 0x1008 0x09 0x0 + 0x1014 0x05 0x0 + 0x104c 0x08 0x0 + 0x1050 0x08 0x0 + 0x10cc 0xf0 0x0 + 0x10d8 0x0f 0x0 + 0x10dc 0x11 0x0 + 0x10f8 0x07 0x0 + 0x1118 0x0c 0x0 + 0x115c 0x3f 0x0 + 0x1160 0xbf 0x0 + 0x1164 0xbf 0x0 + 0x1168 0xb7 0x0 + 0x116c 0xea 0x0 + 0x1170 0xdc 0x0 + 0x1174 0x5c 0x0 + 0x1178 0x9c 0x0 + 0x117c 0x1a 0x0 + 0x1180 0x89 0x0 + 0x1188 0x94 0x0 + 0x118c 0x5b 0x0 + 0x1190 0x1a 0x0 + 0x1194 0x89 0x0 + 0x11a4 0x38 0x0 + 0x11f8 0x08 0x0 + 0x0200 0x00 0x0 + 0x0244 0x03 0x0>; + + pcie2_rp: pcie2_rp { reg = <0 0 0 0 0>; }; diff --git a/qcom/sdxpinn.dtsi b/qcom/sdxpinn.dtsi index a8b71a38..83ff5bf4 100644 --- a/qcom/sdxpinn.dtsi +++ b/qcom/sdxpinn.dtsi @@ -22,7 +22,7 @@ reserved_memory: reserved-memory { }; chosen: chosen { - bootargs = "disable_dma32=on swiotlb=noforce kpti=off cpufreq.default_governor=performance"; + bootargs = "disable_dma32=on swiotlb=noforce kpti=off cpufreq.default_governor=performance pcie_ports=compat"; }; aliases { From 87574217783026dc026264bc27d2b1b9ee72621f Mon Sep 17 00:00:00 2001 From: Archana Sriram Date: Mon, 3 Oct 2022 21:28:24 +0530 Subject: [PATCH 37/65] ARM: dts: msm: Modify adc_tm nodes for Khaje to suit spmi adc tm5 driver Modify adc_tm nodes in Khaje and variants to suit qcom-spmi-adc-tm5 driver in msm-5.15. Change-Id: Iabe3133fe95ee0166d9b7b3fb92e7bda9217393c --- qcom/bengal-thermal.dtsi | 6 +++--- qcom/khaje-atp.dtsi | 12 +++++------- qcom/khaje-idp.dtsi | 12 +++++------- qcom/khaje-pm7250b.dtsi | 17 +++++++++-------- qcom/khaje-qrd.dtsi | 4 ++-- qcom/khaje.dtsi | 18 +++++++++--------- qcom/pm6125.dtsi | 10 ++-------- qcom/pm7250b.dtsi | 4 ++-- 8 files changed, 37 insertions(+), 46 deletions(-) diff --git a/qcom/bengal-thermal.dtsi b/qcom/bengal-thermal.dtsi index a3eda4d8..a077b521 100644 --- a/qcom/bengal-thermal.dtsi +++ b/qcom/bengal-thermal.dtsi @@ -823,7 +823,7 @@ xo-therm { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&pm6125_adc_tm ADC5_XO_THERM_100K_PU>; + thermal-sensors = <&pm6125_adc_tm 2>; trips { active-config0 { temperature = <125000>; @@ -842,7 +842,7 @@ pa-therm0 { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&pm6125_adc_tm ADC5_AMUX_THM1_100K_PU>; + thermal-sensors = <&pm6125_adc_tm 0>; trips { active-config0 { temperature = <125000>; @@ -855,7 +855,7 @@ quiet-therm { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&pm6125_adc_tm ADC5_AMUX_THM2_100K_PU>; + thermal-sensors = <&pm6125_adc_tm 1>; status = "disabled"; trips { active-config0 { diff --git a/qcom/khaje-atp.dtsi b/qcom/khaje-atp.dtsi index af91e0dd..8f0eb87b 100644 --- a/qcom/khaje-atp.dtsi +++ b/qcom/khaje-atp.dtsi @@ -115,15 +115,13 @@ }; &pm6125_adc_tm { - io-channels = <&pm6125_vadc ADC5_AMUX_THM1_100K_PU>, - <&pm6125_vadc ADC5_AMUX_THM2_100K_PU>, - <&pm6125_vadc ADC5_XO_THERM_100K_PU>, - <&pm6125_vadc ADC5_GPIO4_100K_PU>; + status = "ok"; rf_pa1_therm { - reg = ; + reg = <3>; + io-channels = <&pm6125_vadc ADC5_GPIO4_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; }; @@ -132,7 +130,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; - thermal-sensors = <&pm6125_adc_tm ADC5_GPIO4_100K_PU>; + thermal-sensors = <&pm6125_adc_tm 3>; wake-capable-sensor; trips { active-config0 { diff --git a/qcom/khaje-idp.dtsi b/qcom/khaje-idp.dtsi index d4d75671..213382a9 100644 --- a/qcom/khaje-idp.dtsi +++ b/qcom/khaje-idp.dtsi @@ -20,15 +20,13 @@ }; &pm6125_adc_tm { - io-channels = <&pm6125_vadc ADC5_AMUX_THM1_100K_PU>, - <&pm6125_vadc ADC5_AMUX_THM2_100K_PU>, - <&pm6125_vadc ADC5_XO_THERM_100K_PU>, - <&pm6125_vadc ADC5_GPIO4_100K_PU>; + status = "ok"; rf_pa1_therm { - reg = ; + reg = <3>; + io-channels = <&pm6125_vadc ADC5_GPIO4_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; }; @@ -37,7 +35,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; - thermal-sensors = <&pm6125_adc_tm ADC5_GPIO4_100K_PU>; + thermal-sensors = <&pm6125_adc_tm 3>; wake-capable-sensor; trips { active-config0 { diff --git a/qcom/khaje-pm7250b.dtsi b/qcom/khaje-pm7250b.dtsi index 4330593d..4802d26e 100644 --- a/qcom/khaje-pm7250b.dtsi +++ b/qcom/khaje-pm7250b.dtsi @@ -25,20 +25,21 @@ }; &pm7250b_adc_tm { - io-channels = <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>, - <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>; + status = "ok"; /* Channel nodes */ charger_skin_therm@4d { - reg = ; + reg = <0>; + io-channels = <&pm7250b_vadc ADC5_AMUX_THM1_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; conn_therm@4f { - reg = ; + reg = <1>; + io-channels = <&pm7250b_vadc ADC5_AMUX_THM3_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; }; @@ -47,7 +48,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; - thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM1_100K_PU>; + thermal-sensors = <&pm7250b_adc_tm 0>; wake-capable-sensor; trips { active-config0 { @@ -62,7 +63,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; - thermal-sensors = <&pm7250b_adc_tm ADC5_AMUX_THM3_100K_PU>; + thermal-sensors = <&pm7250b_adc_tm 1>; wake-capable-sensor; trips { active-config0 { diff --git a/qcom/khaje-qrd.dtsi b/qcom/khaje-qrd.dtsi index 4461431a..485d0e1d 100644 --- a/qcom/khaje-qrd.dtsi +++ b/qcom/khaje-qrd.dtsi @@ -210,7 +210,7 @@ quiet-therm { polling-delay-passive = <2000>; polling-delay = <0>; - thermal-sensors = <&pm6125_adc_tm ADC5_AMUX_THM2_100K_PU>; + thermal-sensors = <&pm6125_adc_tm 1>; trips { quiet_batt_trip0: batt-trip0 { @@ -318,7 +318,7 @@ pa-therm0 { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&pm6125_adc_tm ADC5_AMUX_THM1_100K_PU>; + thermal-sensors = <&pm6125_adc_tm 0>; trips { pa_therm0_trip0: pa-therm0-trip0 { diff --git a/qcom/khaje.dtsi b/qcom/khaje.dtsi index b79d978e..75d3365e 100644 --- a/qcom/khaje.dtsi +++ b/qcom/khaje.dtsi @@ -4177,27 +4177,27 @@ tpdm_turing_llm: tpdm@8861000 { &pm6125_adc_tm { #address-cells = <1>; #size-cells = <0>; - io-channels = <&pm6125_vadc ADC5_AMUX_THM1_100K_PU>, - <&pm6125_vadc ADC5_AMUX_THM2_100K_PU>, - <&pm6125_vadc ADC5_XO_THERM_100K_PU>; /* Channel nodes */ pa_therm0 { - reg = ; + reg = <0>; + io-channels = <&pm6125_vadc ADC5_AMUX_THM1_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; quiet_therm { - reg = ; + reg = <1>; + io-channels = <&pm6125_vadc ADC5_AMUX_THM2_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; xo_therm { - reg = ; + reg = <2>; + io-channels = <&pm6125_vadc ADC5_XO_THERM_100K_PU>; qcom,ratiometric; - qcom,hw-settle-time = <200>; + qcom,hw-settle-time-us = <200>; }; }; diff --git a/qcom/pm6125.dtsi b/qcom/pm6125.dtsi index c1306da4..ed49b316 100644 --- a/qcom/pm6125.dtsi +++ b/qcom/pm6125.dtsi @@ -69,12 +69,6 @@ qcom,pre-scaling = <1 3>; }; - vcoin { - reg = ; - label = "vcoin"; - qcom,pre-scaling = <1 3>; - }; - xo_therm { reg = ; label = "xo_therm"; @@ -85,10 +79,10 @@ }; pm6125_adc_tm: adc_tm@3500 { - compatible = "qcom,adc-tm5"; + compatible = "qcom,spmi-adc-tm5"; reg = <0x3500>; interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "thr-int-en"; + interrupt-names = "pm-adc-tm5"; #address-cells = <1>; #size-cells = <0>; #thermal-sensor-cells = <1>; diff --git a/qcom/pm7250b.dtsi b/qcom/pm7250b.dtsi index 4ed03d3b..e8a39c45 100644 --- a/qcom/pm7250b.dtsi +++ b/qcom/pm7250b.dtsi @@ -382,10 +382,10 @@ }; pm7250b_adc_tm: adc_tm@3500 { - compatible = "qcom,adc-tm5"; + compatible = "qcom,spmi-adc-tm5"; reg = <0x3500>; interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "thr-int-en"; + interrupt-names = "pm-adc-tm5"; #address-cells = <1>; #size-cells = <0>; #thermal-sensor-cells = <1>; From 8de7322c630bf24a00dca2e8d8b91e086ca70f8e Mon Sep 17 00:00:00 2001 From: Swetha Chikkaboraiah Date: Thu, 29 Sep 2022 16:02:05 +0530 Subject: [PATCH 38/65] ARM: dts: msm: set ddr bus-width to 8 Set DDR bus-width to 8 for khaje. Change-Id: If407376ada9f69e26ece314621fdbdad74e01c32 --- qcom/khaje.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/khaje.dtsi b/qcom/khaje.dtsi index b79d978e..a3dac1fb 100644 --- a/qcom/khaje.dtsi +++ b/qcom/khaje.dtsi @@ -3502,7 +3502,7 @@ qcom_ddr_dcvs_hw: ddr { compatible = "qcom,dcvs-hw"; qcom,dcvs-hw-type = <0>; - qcom,bus-width = <4>; + qcom,bus-width = <8>; qcom,freq-tbl = <&ddr_freq_table>; ddr_dcvs_sp: sp { From d2c135d647c9cf5495892272467700eb798cf32a Mon Sep 17 00:00:00 2001 From: Sandeep Singh Date: Fri, 23 Sep 2022 18:28:01 +0530 Subject: [PATCH 39/65] ARM: dts: msm: Disable ipa for wlan side for khaje Disable ipa for wlan side for khaje. Change-Id: I93f7a302796a88acf497d9cd0bbd1f62332c2908 --- qcom/khajeg.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/khajeg.dtsi b/qcom/khajeg.dtsi index ed1fe0a9..bbaad82c 100644 --- a/qcom/khajeg.dtsi +++ b/qcom/khajeg.dtsi @@ -23,4 +23,8 @@ ipa_hw: qcom,ipa@0x5800000 { status = "disabled"; }; + + icnss: qcom,icnss@C800000 { + wlan-ipa-disabled; + }; }; From 16ff79e5d1d4d91d75c93d6998af3721f529a25a Mon Sep 17 00:00:00 2001 From: Anusha Bableshwar Date: Tue, 27 Sep 2022 16:50:41 -0700 Subject: [PATCH 40/65] ARM: dts: msm: Add PHY init sequence for sdxpinn EP PCIe Added PHY init sequence for EP PCIe and updated version to 8 for 4nm QMP PHY. Value retrieved from PHY HSR V1.00. Change-Id: I4c64f625008f115ea37c4c2a99876b7fdb9d3f28 --- qcom/sdxpinn.dtsi | 154 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 153 insertions(+), 1 deletion(-) diff --git a/qcom/sdxpinn.dtsi b/qcom/sdxpinn.dtsi index 82260833..e6ddb44b 100644 --- a/qcom/sdxpinn.dtsi +++ b/qcom/sdxpinn.dtsi @@ -892,7 +892,7 @@ qcom,pcie-vendor-id = /bits/ 16 <0x17cb>; qcom,pcie-device-id = /bits/ 16 <0x0309>; qcom,pcie-link-speed = <4>; - qcom,pcie-phy-ver = <7>; + qcom,pcie-phy-ver = <8>; qcom,pcie-active-config; qcom,pcie-aggregated-irq; qcom,pcie-mhi-a7-irq; @@ -900,6 +900,158 @@ qcom,mhi-soc-reset-offset = <0xb01b8>; qcom,aoss-rst-clr; qcom,aux-clk = <0x13>; + qcom,phy-init = <0x1240 0x01 0x0 + 0x0030 0x1d 0x0 + 0x0034 0x03 0x0 + 0x0078 0x01 0x0 + 0x007c 0x00 0x0 + 0x0080 0x51 0x0 + 0x00ac 0x34 0x0 + 0x0208 0x0c 0x0 + 0x020c 0x0a 0x0 + 0x0218 0x04 0x0 + 0x0220 0x16 0x0 + 0x0234 0x00 0x0 + 0x029c 0x80 0x0 + 0x02a0 0x7c 0x0 + 0x02b4 0x05 0x0 + 0x02e8 0x0a 0x0 + 0x030c 0x0d 0x0 + 0x0320 0x0b 0x0 + 0x0348 0x1c 0x0 + 0x0388 0x20 0x0 + 0x0394 0x30 0x0 + 0x03dc 0x09 0x0 + 0x03f4 0x14 0x0 + 0x03f8 0xb3 0x0 + 0x03fc 0x58 0x0 + 0x0400 0x9a 0x0 + 0x0404 0x26 0x0 + 0x0408 0xb6 0x0 + 0x040c 0xee 0x0 + 0x0410 0xdb 0x0 + 0x0414 0xdb 0x0 + 0x0418 0xa0 0x0 + 0x041c 0xdf 0x0 + 0x0420 0x78 0x0 + 0x0424 0x76 0x0 + 0x0428 0xff 0x0 + 0x0830 0x1d 0x0 + 0x0834 0x03 0x0 + 0x0878 0x01 0x0 + 0x087c 0x00 0x0 + 0x0880 0x51 0x0 + 0x08ac 0x34 0x0 + 0x0a08 0x0c 0x0 + 0x0a0c 0x0a 0x0 + 0x0a18 0x04 0x0 + 0x0a20 0x16 0x0 + 0x0a34 0x00 0x0 + 0x0a9c 0x80 0x0 + 0x0aa0 0x7c 0x0 + 0x0ab4 0x05 0x0 + 0x0ae8 0x0a 0x0 + 0x0b0c 0x0d 0x0 + 0x0b20 0x0b 0x0 + 0x0b48 0x1c 0x0 + 0x0b88 0x20 0x0 + 0x0b94 0x30 0x0 + 0x0bdc 0x09 0x0 + 0x0bf4 0x14 0x0 + 0x0bf8 0xb3 0x0 + 0x0bfc 0x58 0x0 + 0x0c00 0x9a 0x0 + 0x0c04 0x26 0x0 + 0x0c08 0xb6 0x0 + 0x0c0c 0xee 0x0 + 0x0c10 0xdb 0x0 + 0x0c14 0xdb 0x0 + 0x0c18 0xa0 0x0 + 0x0c1c 0xdf 0x0 + 0x0c20 0x78 0x0 + 0x0c24 0x76 0x0 + 0x0c28 0xff 0x0 + 0x0ea0 0x01 0x0 + 0x0eb4 0x00 0x0 + 0x0ec4 0x00 0x0 + 0x0ec8 0x1f 0x0 + 0x0ed4 0x12 0x0 + 0x0ed8 0x12 0x0 + 0x0edc 0xdb 0x0 + 0x0ee0 0x9a 0x0 + 0x0ee4 0x38 0x0 + 0x0ee8 0xb6 0x0 + 0x0eec 0x64 0x0 + 0x0ef0 0x1f 0x0 + 0x0ef4 0x1f 0x0 + 0x0ef8 0x1f 0x0 + 0x0efc 0x1f 0x0 + 0x0f00 0x1f 0x0 + 0x0f04 0x1f 0x0 + 0x0f0c 0x1f 0x0 + 0x0f14 0x1f 0x0 + 0x0f1c 0x1f 0x0 + 0x0f28 0x5b 0x0 + 0x1010 0x28 0x0 + 0x1014 0x10 0x0 + 0x1018 0x00 0x0 + 0x101c 0x04 0x0 + 0x1020 0xff 0x0 + 0x1024 0x09 0x0 + 0x1028 0x28 0x0 + 0x103c 0x12 0x0 + 0x1040 0xfb 0x0 + 0x1044 0x01 0x0 + 0x1070 0x28 0x0 + 0x1074 0x0d 0x0 + 0x1078 0x00 0x0 + 0x107c 0x0a 0x0 + 0x1080 0xff 0x0 + 0x1084 0x04 0x0 + 0x1088 0x19 0x0 + 0x109c 0x00 0x0 + 0x10a0 0xfb 0x0 + 0x10a4 0x01 0x0 + 0x10bc 0x06 0x0 + 0x10d8 0x40 0x0 + 0x10dc 0x14 0x0 + 0x10e4 0x07 0x0 + 0x10f4 0x0f 0x0 + 0x1110 0x00 0x0 + 0x1120 0x46 0x0 + 0x1124 0x04 0x0 + 0x1140 0x14 0x0 + 0x1170 0xa0 0x0 + 0x1174 0x06 0x0 + 0x1184 0x88 0x0 + 0x1188 0x14 0x0 + 0x1198 0x0f 0x0 + 0x1378 0x2e 0x0 + 0x1390 0xcc 0x0 + 0x13f8 0x00 0x0 + 0x13fc 0x22 0x0 + 0x129c 0x83 0x0 + 0x12a0 0x09 0x0 + 0x12a4 0xa2 0x0 + 0x1450 0x02 0x0 + 0x1478 0x10 0x0 + 0x14a0 0x16 0x0 + 0x1508 0x02 0x0 + 0x155c 0x2e 0x0 + 0x157c 0x03 0x0 + 0x1584 0x28 0x0 + 0x13dc 0x04 0x0 + 0x13e0 0x02 0x0 + 0x1418 0xc0 0x0 + 0x158c 0x0f 0x0 + 0x15ac 0xf2 0x0 + 0x15c0 0xf2 0x0 + 0x1828 0x00 0x0 + 0x1c28 0x00 0x0 + 0x1e24 0x00 0x0 + 0x1e28 0x00 0x0 + 0x1200 0x00 0x0 + 0x1244 0x03 0x0>; status = "disabled"; }; From 5f0db9d7f0efb28bd1b9b16e42f63685186cb0ba Mon Sep 17 00:00:00 2001 From: Sanjay Date: Tue, 27 Sep 2022 10:53:29 +0530 Subject: [PATCH 41/65] ARM: dts: qcom: Update Memory Map for scuba_auto Update Memory Map for scuba_auto and keep it in sync with sa410m. Change-Id: I5c702b2910061e4b3c91688aea4aed4911a85a53 --- qcom/scuba_auto.dtsi | 49 +++++++++++--------------------------------- 1 file changed, 12 insertions(+), 37 deletions(-) diff --git a/qcom/scuba_auto.dtsi b/qcom/scuba_auto.dtsi index 123a77de..26278591 100644 --- a/qcom/scuba_auto.dtsi +++ b/qcom/scuba_auto.dtsi @@ -146,9 +146,9 @@ reg = <0x0 0x45600000 0x0 0x700000>; }; - xbl_aop_mem: xbl_aop_mem@45e00000 { + xbl_aop_mem: xbl_aop_mem@45d00000 { no-map; - reg = <0x0 0x45e00000 0x0 0x100000>; + reg = <0x0 0x45d00000 0x0 0x200000>; }; sec_apps_mem: sec_apps_region@45fff000 { @@ -186,9 +186,14 @@ reg = <0x0 0x52910000 0x0 0x5000>; }; - removed_region: removed_region@60000000 { + tz_stat: tz_stat@53200000 { no-map; - reg = <0x0 0x60000000 0x0 0x3900000>; + reg = <0x0 0x53200000 0x0 0x100000>; + }; + + pimem_vault: pimem_vault@53300000 { + no-map; + reg = <0x0 0x53300000 0x0 0x1500000>; }; adsp_mem: adsp_region { @@ -206,29 +211,6 @@ size = <0 0x800000>; }; - secure_display_memory: secure_display_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0 0x00000000 0 0xffffffff>; - reusable; - alignment = <0 0x400000>; - size = <0 0x5c00000>; - }; - - cont_splash_memory: cont_splash_region@5c000000 { - reg = <0x0 0x5c000000 0x0 0x00f00000>; - label = "cont_splash_region"; - }; - - dfps_data_memory: dfps_data_region@5cf00000 { - reg = <0x0 0x5cf00000 0x0 0x0100000>; - label = "dfps_data_region"; - }; - - disp_rdump_memory: disp_rdump_region@5c000000 { - reg = <0x0 0x5c000000 0x0 0x00f00000>; - label = "disp_rdump_region"; - }; - user_contig_mem: user_contig_region { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; @@ -242,7 +224,7 @@ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; reusable; alignment = <0x0 0x400000>; - size = <0x0 0x1400000>; + size = <0x0 0x700000>; }; qseecom_ta_mem: qseecom_ta_region { @@ -250,7 +232,7 @@ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; reusable; alignment = <0x0 0x400000>; - size = <0x0 0x1000000>; + size = <0x0 0x400000>; }; memshare_mem: memshare_region { @@ -261,15 +243,8 @@ size = <0x0 0x800000>; }; - dump_mem: mem_dump_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - size = <0 0x800000>; - }; - /* global autoconfigured region for contiguous allocations */ - system_cma: linux,cma { + system_cma:linux,cma { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; reusable; From 26df25a458eefe7274862ec05d5bac9d36fe7f71 Mon Sep 17 00:00:00 2001 From: Puneet Yatnal Date: Mon, 27 Jun 2022 23:24:23 +0530 Subject: [PATCH 42/65] ARM: dts: msm: Enable asm330 sensor for SA8155 target Enable asm330 sensor for SA8155 target Change-Id: I174191b33017dc940ba4406caa52f9723e541090 --- qcom/sa8155-adp-common.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/qcom/sa8155-adp-common.dtsi b/qcom/sa8155-adp-common.dtsi index ce71d404..e5923968 100644 --- a/qcom/sa8155-adp-common.dtsi +++ b/qcom/sa8155-adp-common.dtsi @@ -80,3 +80,21 @@ status = "ok"; }; + +&qupv3_se10_i2c { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + asm330@6a { + compatible = "st,asm330lhh"; + reg = <0x6a>; + vio-supply = <&pm8150_2_l7>; + vdd-supply = <&pm8150_2_l16>; + interrupt-parent = <&tlmm>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sensor_int1_default + &sensor_int2_default>; + }; +}; From 6231f873e3601d148002e08e0fb87b798c71e8f6 Mon Sep 17 00:00:00 2001 From: Archana Sriram Date: Fri, 7 Oct 2022 08:23:55 +0530 Subject: [PATCH 43/65] dt-bindings: thermal: Update dt-binding for spmi-adc-tm5 Update compatible string to support ADC channels that are registered to thermal framework, without registering interrupts. Change-Id: Ic423571989dba9e2cb69f4e76d3667872809de36 --- bindings/thermal/qcom-spmi-adc-tm5.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/bindings/thermal/qcom-spmi-adc-tm5.yaml b/bindings/thermal/qcom-spmi-adc-tm5.yaml index 3ea8c0c1..dbcdf7ae 100644 --- a/bindings/thermal/qcom-spmi-adc-tm5.yaml +++ b/bindings/thermal/qcom-spmi-adc-tm5.yaml @@ -10,7 +10,9 @@ maintainers: properties: compatible: - const: qcom,spmi-adc-tm5 + enum: + - qcom,spmi-adc-tm5 + - qcom,spmi-adc-tm5-iio reg: maxItems: 1 From f3ef486e315db4f8cb91b9ee7984fe92fc088ef1 Mon Sep 17 00:00:00 2001 From: Archana Sriram Date: Fri, 7 Oct 2022 00:29:36 +0530 Subject: [PATCH 44/65] ARM: dts: msm: Modify adc_tm_iio nodes for Khaje to suit spmi adc tm5 driver Modify adc_tm_iio nodes in Khaje to suit the qcom-spmi-adc-tm5 driver in msm-5.15. Change-Id: I7b6968107aeabf6327de50f3bb5ee8198c2f71bd --- qcom/bengal-thermal.dtsi | 4 ++-- qcom/khaje.dtsi | 16 ++++++---------- 2 files changed, 8 insertions(+), 12 deletions(-) diff --git a/qcom/bengal-thermal.dtsi b/qcom/bengal-thermal.dtsi index a077b521..023d19e1 100644 --- a/qcom/bengal-thermal.dtsi +++ b/qcom/bengal-thermal.dtsi @@ -988,7 +988,7 @@ camera-therm { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&pm6125_adc_tm_iio ADC5_GPIO1_100K_PU>; + thermal-sensors = <&pm6125_adc_tm_iio 0>; trips { active-config0 { temperature = <125000>; @@ -1001,7 +1001,7 @@ emmc-ufs-therm { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&pm6125_adc_tm_iio ADC5_GPIO2_100K_PU>; + thermal-sensors = <&pm6125_adc_tm_iio 1>; trips { active-config0 { temperature = <125000>; diff --git a/qcom/khaje.dtsi b/qcom/khaje.dtsi index 75d3365e..7194fd82 100644 --- a/qcom/khaje.dtsi +++ b/qcom/khaje.dtsi @@ -4151,24 +4151,20 @@ tpdm_turing_llm: tpdm@8861000 { &spmi_bus { qcom,pm6125@0 { pm6125_adc_tm_iio: adc_tm@3400 { - compatible = "qcom,adc-tm5-iio"; - reg = <0x3400 0x100>; + compatible = "qcom,spmi-adc-tm5-iio"; + reg = <0x3400>; #thermal-sensor-cells = <1>; #address-cells = <1>; #size-cells = <0>; - io-channels = <&pm6125_vadc ADC5_GPIO1_100K_PU>, - <&pm6125_vadc ADC5_GPIO2_100K_PU>; camera_flash_therm { - reg = ; - qcom,ratiometric; - qcom,hw-settle-time = <200>; + reg = <0>; + io-channels = <&pm6125_vadc ADC5_GPIO1_100K_PU>; }; emmc_ufs_therm { - reg = ; - qcom,ratiometric; - qcom,hw-settle-time = <200>; + reg = <1>; + io-channels = <&pm6125_vadc ADC5_GPIO2_100K_PU>; }; }; }; From 944d313325563322066e1ddb723ec783e17b3c92 Mon Sep 17 00:00:00 2001 From: Anurag Chouhan Date: Fri, 7 Oct 2022 14:31:50 +0530 Subject: [PATCH 45/65] ARM: dts: msm: Remove AHB clock for monaco Remove AHB clock as it is always on for monaco. Change-Id: I61ea87e3306fb286979e53d9e03dedd19aa5579f --- qcom/msm-arm-smmu-monaco.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/qcom/msm-arm-smmu-monaco.dtsi b/qcom/msm-arm-smmu-monaco.dtsi index 8f7d889c..5ae347c6 100644 --- a/qcom/msm-arm-smmu-monaco.dtsi +++ b/qcom/msm-arm-smmu-monaco.dtsi @@ -16,11 +16,9 @@ vdd-supply = <&gpu_cx_gdsc>; clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, - <&gpucc GPU_CC_AHB_CLK>, <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; clock-names = "gcc_gpu_memnoc_gfx", "gcc_gpu_snoc_dvm_gfx", - "gpu_cc_ahb", "gpu_cc_hlos1_vote_gpu_smmu_clk"; #size-cells = <1>; #address-cells = <1>; From f976cab7acaeb96ea4edbae1717e80cb3202349b Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Wed, 27 Apr 2022 07:51:10 +0530 Subject: [PATCH 46/65] ARM: dts: msm: add SPMI PMIC arbiter and PMIC devices for lemans Add an SPMI PMIC arbiter device so that it is possible to communicate with PMICs attached to the SPMI bus and also add top level slave devices and their peripherals. Change-Id: I15afa13ed9edfd455c1594ada1a80748d844c149 --- qcom/lemans-adp-common.dtsi | 2 + qcom/lemans-pmic-overlay.dtsi | 211 ++++++++++++++++++++++++++++++ qcom/lemans.dtsi | 22 ++++ qcom/pm8775.dtsi | 233 ++++++++++++++++++++++++++++++++++ 4 files changed, 468 insertions(+) create mode 100644 qcom/lemans-pmic-overlay.dtsi create mode 100644 qcom/pm8775.dtsi diff --git a/qcom/lemans-adp-common.dtsi b/qcom/lemans-adp-common.dtsi index f82eb484..3316447c 100644 --- a/qcom/lemans-adp-common.dtsi +++ b/qcom/lemans-adp-common.dtsi @@ -1,3 +1,5 @@ +#include "lemans-pmic-overlay.dtsi" + / { model = "Qualcomm Technologies, Inc. Lemans ADP"; compatible = "qcom,lemans", "qcom,adp"; diff --git a/qcom/lemans-pmic-overlay.dtsi b/qcom/lemans-pmic-overlay.dtsi new file mode 100644 index 00000000..18ffd3dd --- /dev/null +++ b/qcom/lemans-pmic-overlay.dtsi @@ -0,0 +1,211 @@ +#include "pm8775.dtsi" + +&pm8775_1 { + /delete-node/ pon_pbs@800; + /delete-node/ pon_hlos@1200; + + pon_hlos@1200 { + compatible = "qcom,pm8998-pon"; + reg = <0x1200>, <0x800>; + reg-names = "pon_hlos", "pon_pbs"; + + pwrkey { + compatible = "qcom,pmk8350-pwrkey"; + interrupts = <0x0 0x12 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + }; + + resin { + compatible = "qcom,pmk8350-resin"; + interrupts = <0x0 0x12 0x6 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + }; + }; +}; + +&pm8775_2 { + /delete-node/ pon_pbs@800; + /delete-node/ pon_hlos@1200; + + pon_hlos@1200 { + compatible = "qcom,pm8998-pon"; + reg = <0x1200>, <0x800>; + reg-names = "pon_hlos", "pon_pbs"; + + pwrkey { + compatible = "qcom,pmk8350-pwrkey"; + interrupts = <0x2 0x12 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + }; + + resin { + compatible = "qcom,pmk8350-resin"; + interrupts = <0x2 0x12 0x6 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + }; + }; +}; + +&pm8775_3 { + /delete-node/ pon_pbs@800; + /delete-node/ pon_hlos@1200; + + pon_hlos@1200 { + compatible = "qcom,pm8998-pon"; + reg = <0x1200>, <0x800>; + reg-names = "pon_hlos", "pon_pbs"; + + pwrkey { + compatible = "qcom,pmk8350-pwrkey"; + interrupts = <0x4 0x12 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + }; + + resin { + compatible = "qcom,pmk8350-resin"; + interrupts = <0x4 0x12 0x6 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + }; + }; +}; + +&pm8775_4 { + /delete-node/ pon_pbs@800; + /delete-node/ pon_hlos@1200; + + pon_hlos@1200 { + compatible = "qcom,pm8998-pon"; + reg = <0x1200>, <0x800>; + reg-names = "pon_hlos", "pon_pbs"; + + pwrkey { + compatible = "qcom,pmk8350-pwrkey"; + interrupts = <0x6 0x12 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + }; + + resin { + compatible = "qcom,pmk8350-resin"; + interrupts = <0x6 0x12 0x6 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + }; + }; +}; + +&soc { + pmic-pon-log { + compatible = "qcom,pmic-pon-log"; + nvmem = <&pm8775_1_sdam_5>; + nvmem-names = "pon_log"; + }; +}; + +&thermal_zones { + pm8775_1_temp_alarm: pm8775_1_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8775_1_tz>; + + trips { + pm8775_1_trip0: trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8775_1_trip1: trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8775_1_trip2: trip2 { + temperature = <155000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pm8775_2_temp_alarm: pm8775_2_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8775_2_tz>; + + trips { + pm8775_2_trip0: trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8775_2_trip1: trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8775_2_trip2: trip2 { + temperature = <155000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pm8775_3_temp_alarm: pm8775_3_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8775_3_tz>; + + trips { + pm8775_3_trip0: trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8775_3_trip1: trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8775_3_trip2: trip2 { + temperature = <155000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pm8775_4_temp_alarm: pm8775_4_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8775_4_tz>; + + trips { + pm8775_4_trip0: trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8775_4_trip1: trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8775_4_trip2: trip2 { + temperature = <155000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; +}; diff --git a/qcom/lemans.dtsi b/qcom/lemans.dtsi index 2b0b079f..03ba45cc 100644 --- a/qcom/lemans.dtsi +++ b/qcom/lemans.dtsi @@ -957,6 +957,28 @@ vendor_hooks: qcom,cpu-vendor-hooks { compatible = "qcom,cpu-vendor-hooks"; }; + + spmi_bus: qcom,spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc440000 0x1100>, + <0xc600000 0x2000000>, + <0xe600000 0x100000>, + <0xe700000 0xa0000>, + <0xc40a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + cell-index = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + }; + + thermal_zones: thermal-zones { + }; }; #include "lemans-4pmic-regulators.dtsi" diff --git a/qcom/pm8775.dtsi b/qcom/pm8775.dtsi new file mode 100644 index 00000000..8f6caf84 --- /dev/null +++ b/qcom/pm8775.dtsi @@ -0,0 +1,233 @@ +#include +#include +#include +#include +#include + + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + pm8775_1: qcom,pm8775@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8775_1_tz: qcom,temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x0 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pon_pbs@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + qcom,system-reset; + qcom,store-hard-reset-reason; + }; + + pon_hlos@1200 { + compatible = "qcom,qpnp-power-on"; + reg = <0x1200>, <0x800>; + reg-names = "pon_hlos", "pon_pbs"; + interrupts = <0x0 0x12 0x7 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x6 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "kpdpwr", "resin"; + qcom,kpdpwr-sw-debounce; + + qcom,pon_1 { + qcom,pon-type = ; + linux,code = ; + }; + + qcom,pon_2 { + qcom,pon-type = ; + linux,code = ; + }; + }; + + pm8775_1_clkdiv: clock-controller@5700 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5700>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm8775_1_div_clk1", + "pm8775_1_div_clk2"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm8775_1_rtc: qcom,pm8775_1_rtc { + compatible = "qcom,pmk8350-rtc"; + reg = <0x6100>, <0x6200>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x62 0x1 IRQ_TYPE_NONE>; + }; + + pm8775_1_gpios: pinctrl@8800 { + compatible = "qcom,pm8775-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm8775_1_sdam_2: sdam@7100 { + compatible = "qcom,spmi-sdam"; + reg = <0x7100>; + #address-cells = <1>; + #size-cells = <1>; + }; + + pm8775_1_sdam_5: sdam@7400 { + compatible = "qcom,spmi-sdam"; + reg = <0x7400>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; + + /* below definitions are for the second instance of pm8775 */ + pm8775_2: qcom,pm8775@2 { + compatible = "qcom,spmi-pmic"; + reg = <2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8775_2_tz: qcom,temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pon_pbs@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + }; + + pon_hlos@1200 { + compatible = "qcom,qpnp-power-on"; + reg = <0x1200>, <0x800>; + reg-names = "pon_hlos", "pon_pbs"; + }; + + pm8775_2_clkdiv: clock-controller@5700 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5700>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm8775_2_div_clk1", + "pm8775_2_div_clk2"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm8775_2_gpios: pinctrl@8800 { + compatible = "qcom,pm8775-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + /* below definitions are for the third instance of pm8775 */ + pm8775_3: qcom,pm8775@4 { + compatible = "qcom,spmi-pmic"; + reg = <4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8775_3_tz: qcom,temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pon_pbs@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + }; + + pon_hlos@1200 { + compatible = "qcom,qpnp-power-on"; + reg = <0x1200>, <0x800>; + reg-names = "pon_hlos", "pon_pbs"; + }; + + pm8775_3_clkdiv: clock-controller@5700 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5700>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm8775_3_div_clk1", + "pm8775_3_div_clk2"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm8775_3_gpios: pinctrl@8800 { + compatible = "qcom,pm8775-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + /* below definitions are for the fourth instance of pm8775 */ + pm8775_4: qcom,pm8775@6 { + compatible = "qcom,spmi-pmic"; + reg = <6 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8775_4_tz: qcom,temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pon_pbs@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + }; + + pon_hlos@1200 { + compatible = "qcom,qpnp-power-on"; + reg = <0x1200>, <0x800>; + reg-names = "pon_hlos", "pon_pbs"; + }; + + pm8775_4_clkdiv: clock-controller@5700 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5700>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm8775_4_div_clk1", + "pm8775_4_div_clk2"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm8775_4_gpios: pinctrl@8800 { + compatible = "qcom,pm8775-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; From 3d585b804c656157df270d73b5f611604a70634d Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Thu, 28 Jul 2022 19:14:02 +0530 Subject: [PATCH 47/65] ARM: dts: msm: Add usb device nodes for sdxbaagha Add USB device node to support USB peripheral mode on RUMI platform for sdxbaagha. Change-Id: I64e6a91cb37b2cf7dfe69f7bdd6f632f8e79222b --- qcom/sdxbaagha-rumi.dtsi | 28 ++++++++++++++++++++++++ qcom/sdxbaagha-usb.dtsi | 46 ++++++++++++++++++++++++++++++++++++++++ qcom/sdxbaagha.dtsi | 1 + 3 files changed, 75 insertions(+) create mode 100644 qcom/sdxbaagha-usb.dtsi diff --git a/qcom/sdxbaagha-rumi.dtsi b/qcom/sdxbaagha-rumi.dtsi index 26af1922..e2f47e70 100644 --- a/qcom/sdxbaagha-rumi.dtsi +++ b/qcom/sdxbaagha-rumi.dtsi @@ -18,6 +18,27 @@ qcom,no-l0s-supported; qcom,no-aux-clk-sync; }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + usb_emuphy: phy@a71c000 { + compatible = "qcom,usb-emu-phy"; + reg = <0xA71C000 0x9500>; + + qcom,emu-init-seq = <0xfff0 0x4 + 0xfff3 0x4 + 0xfff0 0x4 + 0x100000 0x20 + 0x0 0x20 + 0x1e0 0x20 + 0x100000 0x3c + 0x0 0x3c + 0x4 0x3c + 0x0 0x4 + 0x9 0x14>; + }; }; &qupv3_se3_2uart { @@ -27,3 +48,10 @@ &gcc { clocks = <&bi_tcxo>, <&pcie_pipe_clk>, <&sleep_clk>; }; + +&usb0 { + dwc3@a600000 { + usb-phy = <&usb_emuphy>, <&usb_nop_phy>; + dr_mode = "peripheral"; + }; +}; diff --git a/qcom/sdxbaagha-usb.dtsi b/qcom/sdxbaagha-usb.dtsi new file mode 100644 index 00000000..14d8e38b --- /dev/null +++ b/qcom/sdxbaagha-usb.dtsi @@ -0,0 +1,46 @@ +#include + +&soc { + usb0: hsusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa600000 0x100000>; + reg-names = "core_base"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + USB3_GDSC-supply = <&gcc_usb20_gdsc>; + + clocks = <&gcc GCC_USB20_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB_SF_AXI_CLK>, + <&gcc GCC_USB20_SLEEP_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>; + + clock-names = "core_clk", "iface_clk", "sleep_clk", "utmi_clk"; + + resets = <&gcc GCC_USB20_BCR>; + reset-names = "core_reset"; + + interrupts = ; + interrupt-names = "pwr_event_irq"; + + qcom,core-clk-rate = <60000000>; + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0xa600000 0xd93c>; + + interrupts = ; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + maximum-speed = "high-speed"; + dr_mode = "otg"; + usb-role-switch; + }; + }; +}; diff --git a/qcom/sdxbaagha.dtsi b/qcom/sdxbaagha.dtsi index 2e17a39d..e347f5a7 100644 --- a/qcom/sdxbaagha.dtsi +++ b/qcom/sdxbaagha.dtsi @@ -491,6 +491,7 @@ #include "msm-arm-smmu-sdxbaagha.dtsi" #include "sdxbaagha-pcie.dtsi" #include "sdxbaagha-qupv3.dtsi" +#include "sdxbaagha-usb.dtsi" &qupv3_se3_2uart { status = "ok"; From 6d1f481adc3672d7810a6c1dbb1ba697327bd8ee Mon Sep 17 00:00:00 2001 From: Ronak Vijay Raheja Date: Sat, 8 Oct 2022 09:00:42 -0700 Subject: [PATCH 48/65] ARM: dts: msm: Use the 5nm QMP USB UNI PHY header for cinder Instead of qcom,usb3-4nm-qmp-uni.h, use qcom,usb3-5nm-qmp-uni.h for cinder-usb.dtsi. Change-Id: Ia1e0d6795f8a38a30397b00a31f40d2cc1d07105 --- qcom/cinder-usb.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/cinder-usb.dtsi b/qcom/cinder-usb.dtsi index 2a445056..6a05c105 100644 --- a/qcom/cinder-usb.dtsi +++ b/qcom/cinder-usb.dtsi @@ -1,5 +1,5 @@ #include -#include +#include &soc { usb0: ssusb@a600000 { From 5f1e2d0a6b2ad994adda84495980e34edcc32f98 Mon Sep 17 00:00:00 2001 From: Lijuan Gao Date: Mon, 10 Oct 2022 11:23:02 +0800 Subject: [PATCH 49/65] ARM: dts: msm: Update the subtype with ddr info Subtype bits 10:8 contains ddr information and ddr info is absolutely matched, so update the subtype with ddr info for sdxbaagha rumi. Change-Id: Id5ef4873d027651ec9753621f6bde812f8010ee4 --- qcom/sdxbaagha-rumi.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxbaagha-rumi.dts b/qcom/sdxbaagha-rumi.dts index 475e673a..695024cd 100644 --- a/qcom/sdxbaagha-rumi.dts +++ b/qcom/sdxbaagha-rumi.dts @@ -7,5 +7,5 @@ model = "Qualcomm Technologies, Inc. SDXBAAGHA RUMI"; compatible = "qcom,sdxbaagha-rumi", "qcom,sdxbaagha", "qcom,rumi"; - qcom,board-id = <0x0F 0>; + qcom,board-id = <0x0F 0x400>; }; From 223de31fb47f788f88a9cd242497ef75efb01140 Mon Sep 17 00:00:00 2001 From: Nishant Pandey Date: Thu, 6 Oct 2022 22:48:28 -0700 Subject: [PATCH 50/65] ARM: dts: msm: Add the dma-buf heaps device node for sa410m Add the dma-buf heaps device node for the dma-buf heaps driver on sa410m. Change-Id: If2730989080b9b79391215163d8a169fc6df8edf --- qcom/sa410m-dma-heap.dtsi | 26 ++++++++++++++++++++++++++ qcom/sa410m.dtsi | 1 + 2 files changed, 27 insertions(+) create mode 100644 qcom/sa410m-dma-heap.dtsi diff --git a/qcom/sa410m-dma-heap.dtsi b/qcom/sa410m-dma-heap.dtsi new file mode 100644 index 00000000..527e869e --- /dev/null +++ b/qcom/sa410m-dma-heap.dtsi @@ -0,0 +1,26 @@ + +#include + +&soc { + qcom,dma-heaps { + compatible = "qcom,dma-heaps"; + + qcom,qseecom { + qcom,dma-heap-name = "qcom,qseecom"; + qcom,dma-heap-type = ; + memory-region = <&qseecom_mem>; + }; + + qcom,qseecom_ta { + qcom,dma-heap-name = "qcom,qseecom-ta"; + qcom,dma-heap-type = ; + memory-region = <&qseecom_ta_mem>; + }; + + qcom,user_contig { + qcom,dma-heap-name = "qcom,user-contig"; + qcom,dma-heap-type = ; + memory-region = <&user_contig_mem>; + }; + }; +}; diff --git a/qcom/sa410m.dtsi b/qcom/sa410m.dtsi index 8362ac06..28354d71 100644 --- a/qcom/sa410m.dtsi +++ b/qcom/sa410m.dtsi @@ -575,6 +575,7 @@ #include "sa410m-pinctrl.dtsi" #include "monaco-gdsc.dtsi" #include "sa410m-qupv3.dtsi" +#include "sa410m-dma-heap.dtsi" &gcc_emac0_gdsc { status = "ok"; From a82ebd53fc0d3fd421ad9082eca6aae0cb0b477e Mon Sep 17 00:00:00 2001 From: Nishant Pandey Date: Sun, 9 Oct 2022 23:40:07 -0700 Subject: [PATCH 51/65] ARM: dts: msm: Add the dma-buf heaps device node for scuba_auto Add the dma-buf heaps device node for the dma-buf heaps driver on scuba_auto. Change-Id: I24ab890c9d5cccee4ece1b934bdd0a93cb96da80 --- qcom/scuba_auto-dma-heap.dtsi | 26 ++++++++++++++++++++++++++ qcom/scuba_auto.dtsi | 1 + 2 files changed, 27 insertions(+) create mode 100644 qcom/scuba_auto-dma-heap.dtsi diff --git a/qcom/scuba_auto-dma-heap.dtsi b/qcom/scuba_auto-dma-heap.dtsi new file mode 100644 index 00000000..527e869e --- /dev/null +++ b/qcom/scuba_auto-dma-heap.dtsi @@ -0,0 +1,26 @@ + +#include + +&soc { + qcom,dma-heaps { + compatible = "qcom,dma-heaps"; + + qcom,qseecom { + qcom,dma-heap-name = "qcom,qseecom"; + qcom,dma-heap-type = ; + memory-region = <&qseecom_mem>; + }; + + qcom,qseecom_ta { + qcom,dma-heap-name = "qcom,qseecom-ta"; + qcom,dma-heap-type = ; + memory-region = <&qseecom_ta_mem>; + }; + + qcom,user_contig { + qcom,dma-heap-name = "qcom,user-contig"; + qcom,dma-heap-type = ; + memory-region = <&user_contig_mem>; + }; + }; +}; diff --git a/qcom/scuba_auto.dtsi b/qcom/scuba_auto.dtsi index 26278591..6ff28f5a 100644 --- a/qcom/scuba_auto.dtsi +++ b/qcom/scuba_auto.dtsi @@ -1132,6 +1132,7 @@ #include "msm-arm-smmu-scuba_auto.dtsi" #include "scuba_auto-qupv3.dtsi" +#include "scuba_auto-dma-heap.dtsi" &sdhc_1 { vdd-supply = <&L20A>; From a945736d9df90a064a25837f71bac1d19f2bb689 Mon Sep 17 00:00:00 2001 From: Yogesh Lal Date: Mon, 10 Oct 2022 18:04:45 +0530 Subject: [PATCH 52/65] ARM: dts: qcom: Update the ddr size for 4GB cinder ru Update the ddr size in the board for cinder 4GB ru. Change-Id: I96c8600668eb5fa1793f7771000c07afc8f65467 --- qcom/cinder-ru-idp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/cinder-ru-idp.dts b/qcom/cinder-ru-idp.dts index 6afc61c3..a7cefc73 100644 --- a/qcom/cinder-ru-idp.dts +++ b/qcom/cinder-ru-idp.dts @@ -6,5 +6,5 @@ / { model = "Qualcomm Technologies, Inc. Cinder RU IDP"; compatible = "qcom,cinder-idp", "qcom,cinder", "qcom,idp"; - qcom,board-id = <0x22 0x0>; + qcom,board-id = <0x22 0x600>; }; From 399ac2dcde623b20a250b22c92499def9d13177d Mon Sep 17 00:00:00 2001 From: Yadu MG Date: Fri, 12 Aug 2022 02:25:40 +0530 Subject: [PATCH 53/65] ARM: dts: msm: Add the PCIe SMMUv2 instance for Lemans Enable the PCIe SMMUv2 instance for the Lemans target. Change-Id: If03411ab5d7467d6ea0b39bce08e35aae51ed454 --- qcom/msm-arm-smmu-lemans.dtsi | 124 ++++++++++++++++++++++++++++++++++ 1 file changed, 124 insertions(+) diff --git a/qcom/msm-arm-smmu-lemans.dtsi b/qcom/msm-arm-smmu-lemans.dtsi index baba59ab..488884d9 100644 --- a/qcom/msm-arm-smmu-lemans.dtsi +++ b/qcom/msm-arm-smmu-lemans.dtsi @@ -281,6 +281,107 @@ }; }; + pcie_smmu: pcie-smmu@0x15200000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15200000 0x80000>, + <0x152F2000 0x28>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,split-tables; + #global-interrupts = <2>; + #size-cells = <1>; + #address-cells = <1>; + #tcu-testbus-version = <1>; + ranges; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + pcie_0_tbu: pcie_0_tbu@152f9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x152F9000 0x1000>, + <0x152F2200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + qcom,iova-width = <36>; + }; + + pcie_1_tbu: pcie_1_tbu@152fb000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x152FB000 0x1000>, + <0x152F3200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + qcom,iova-width = <36>; + }; + }; + kgsl_smmu: kgsl-smmu@3da0000 { compatible = "qcom,qsmmu-v500"; reg = <0x3da0000 0x20000>, @@ -393,6 +494,29 @@ dma-coherent; }; + usecase0_pcie { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&pcie_smmu 0x440 0x0>; + }; + + usecase1_pcie_fastmap { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&pcie_smmu 0x440 0x0>; + qcom,iommu-dma = "fastmap"; + }; + + usecase2_pcie_atomic { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&pcie_smmu 0x440 0x0>; + qcom,iommu-dma = "atomic"; + }; + + usecase3_pcie_dma { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&pcie_smmu 0x440 0x0>; + dma-coherent; + }; + usecase0_kgsl { compatible = "qcom,iommu-debug-usecase"; iommus = <&kgsl_smmu 0x7 0xC00>; From 978df55da63e736e526fcf5b0ffe9e90bd3cbe88 Mon Sep 17 00:00:00 2001 From: Venkata Rao Kakani Date: Mon, 10 Oct 2022 01:33:11 -0700 Subject: [PATCH 54/65] Revert "ARM: dts: msm: disable ethernet on SA8155" This reverts commit 235569fc22a04793cba328a91ea30df66838f7b8. Change-Id: Icbcf2975ee6fb97ca5e519c1802b1a876836eb4b --- qcom/sa8155.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi index e7106ff0..5ce5c715 100644 --- a/qcom/sa8155.dtsi +++ b/qcom/sa8155.dtsi @@ -291,7 +291,6 @@ hsi2s: qcom,hsi2s { snps,reset-delays-us = <0 11000 70000>; phy-mode = "rgmii"; eth-c22-mdio-probe; - status = "disabled"; ethqos_emb_smmu: ethqos_emb_smmu { compatible = "qcom,emac-smmu-embedded"; From d7de2904e9c5d1a7c45df67b31541ea9b265c7c4 Mon Sep 17 00:00:00 2001 From: Zou Shunxiang Date: Fri, 22 Jul 2022 10:50:58 +0800 Subject: [PATCH 55/65] ARM: dts: qcom: Add power reset and watchdog nodes for vm Enables virtual power reset and watchdog, adds related dts for GVM platform. Change-Id: Ic4106c3dea6658683fa1baa410603450a437feb5 --- qcom/quin-vm-common.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/qcom/quin-vm-common.dtsi b/qcom/quin-vm-common.dtsi index 6c76233d..3711ca27 100644 --- a/qcom/quin-vm-common.dtsi +++ b/qcom/quin-vm-common.dtsi @@ -61,6 +61,19 @@ ranges = <0x0 0x0 0x0 0xffffffff>; compatible = "simple-bus"; + wdog: qcom,wdt@17c10000 { + compatible = "qcom,msm-watchdog"; + reg = <0x17c10000 0x1000>; + reg-names = "wdt-base"; + interrupts = , + ; + }; + + vm_restart: restart { + compatible = "qcom,vm-restart"; + status = "ok"; + }; + intc: vgic@0 { qvm,vdev = "gic"; #interrupt-cells = <3>; From a2af929a0aab884eae0d1c33d027968d4d44580b Mon Sep 17 00:00:00 2001 From: Singa Reddy Dasari Date: Fri, 2 Sep 2022 22:41:06 +0530 Subject: [PATCH 56/65] ARM: dts: qcom: Add the APSS SMMU node for the Auto VM platforms Add the APSS SMMU node for the Auto VM platform to enable IOMMU control from the VM. Change-Id: I771e2e8170aac01b36a47afc9a5cbab1aadd4744 --- qcom/quin-vm-common.dtsi | 2 +- qcom/sa8155-vm.dtsi | 103 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 104 insertions(+), 1 deletion(-) diff --git a/qcom/quin-vm-common.dtsi b/qcom/quin-vm-common.dtsi index 6c76233d..305ae555 100644 --- a/qcom/quin-vm-common.dtsi +++ b/qcom/quin-vm-common.dtsi @@ -22,7 +22,7 @@ #size-cells = <2>; ranges; - linux,cma { + system_cma: linux,cma { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x0 0x0 0xffffffff>; reusable; diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi index 5e8d65ae..ff12398e 100644 --- a/qcom/sa8155-vm.dtsi +++ b/qcom/sa8155-vm.dtsi @@ -130,6 +130,109 @@ }; }; +&soc { + apps_smmu: apps-smmu@0x15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x100000>, + <0x15182000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,disable-atos; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + dma_dev@0x0 { + compatible = "qcom,iommu-dma"; + memory-region = <&system_cma>; + }; +}; + #include "sm8150-pinctrl.dtsi" &tlmm { From 1c1c78e573a00f0c7152ffcb0d90fdbb118676e8 Mon Sep 17 00:00:00 2001 From: Fei Yang Date: Thu, 15 Sep 2022 12:02:13 +0000 Subject: [PATCH 57/65] ARM: dts: msm: Add virtual spmi device tree node for autogvm Add virtual spmi pmic and its dependent device tree node to support SA8155 for automotive linux guest platform. Change-Id: Ibb18c555af52cd6f7386ce008a00b7f60e5c49df --- qcom/pm8150-vm.dtsi | 62 ++++++++++++++++++++++++++++++++++++++++ qcom/quin-vm-common.dtsi | 13 +++++++++ qcom/sa8155-vm.dtsi | 1 + 3 files changed, 76 insertions(+) create mode 100644 qcom/pm8150-vm.dtsi diff --git a/qcom/pm8150-vm.dtsi b/qcom/pm8150-vm.dtsi new file mode 100644 index 00000000..0e8d9700 --- /dev/null +++ b/qcom/pm8150-vm.dtsi @@ -0,0 +1,62 @@ +#include +#include +#include +#include + +&spmi_bus { + qcom,pm8150@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8150_gpios: pinctrl@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm8150_rtc: qcom,pm8150_rtc { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_LEVEL_HIGH>; + qcom,disable-alarm-wakeup; + }; + }; +}; + +&pm8150_gpios { + key_home { + key_home_default: key_home_default { + pins = "gpio1"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; + + storage_sd_detect { + storage_cd_default: storage_cd_default { + pins = "gpio4"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; + + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <1>; + }; + }; +}; diff --git a/qcom/quin-vm-common.dtsi b/qcom/quin-vm-common.dtsi index 6c76233d..c363975a 100644 --- a/qcom/quin-vm-common.dtsi +++ b/qcom/quin-vm-common.dtsi @@ -190,5 +190,18 @@ reg = <0xc221000 0x1000>; clock-frequency = <32768>; }; + + spmi_bus: virtio-spmi@1c800000 { + compatible = "virtio,mmio"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1c800000 0x1100>; + interrupt-names = "periph_irq"; + interrupts = ; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + status = "okay"; + }; }; diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi index 5e8d65ae..0f24526b 100644 --- a/qcom/sa8155-vm.dtsi +++ b/qcom/sa8155-vm.dtsi @@ -1,4 +1,5 @@ #include "quin-vm-common.dtsi" +#include "pm8150-vm.dtsi" / { model = "Qualcomm Technologies, Inc. SA8155 Guest Virtual Machine"; From ab7084266420ea97e6707dc14f656b2837287900 Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Fri, 23 Sep 2022 11:14:22 +0530 Subject: [PATCH 58/65] ARM: dts: msm: Add smmu and bus voting support for sdxpinn nand Add smmu & bus voting support for sdxpinn nand. Change-Id: I53ca32ab4b06a8b673070778ac6aa9369abb2934 --- qcom/sdxpinn.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/qcom/sdxpinn.dtsi b/qcom/sdxpinn.dtsi index 208f4f3f..fc2cef49 100644 --- a/qcom/sdxpinn.dtsi +++ b/qcom/sdxpinn.dtsi @@ -780,6 +780,19 @@ clock-names = "core_clk"; clocks = <&rpmhcc RPMH_QPIC_CLK>; + interconnects = <&system_noc MASTER_QPIC &mc_virt SLAVE_EBI1>; + interconnect-names = "nand-ddr"; + qcom,msm-bus,name = "qpic_nand"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <0 0>, + /* Voting for max b/w on PNOC bus for now */ + <1057800 725760>; + + iommus = <&apps_smmu 0x100 0x7>; + qcom,iommu-dma = "bypass"; + status = "disabled"; }; From fb6df9f6d0c5ff0bd376542a5811e51a76828314 Mon Sep 17 00:00:00 2001 From: Nagireddy Annem Date: Tue, 11 Oct 2022 18:08:10 +0530 Subject: [PATCH 59/65] ARM: dts: msm: Add standalone base dt support for monaco Add standalone base dt support for monaco. Change-Id: Ibf3a515e26759cf2435dd1ad99c013de8fa58343 --- qcom/Makefile | 7 ++++++- qcom/monaco-standalone-atp-v1-overlay.dts | 9 +++++++++ qcom/monaco-standalone-atp-v1.dtsi | 1 + qcom/monaco-standalone-idp-v1-overlay.dts | 9 +++++++++ qcom/monaco-standalone-idp-v1.dtsi | 1 + qcom/monaco-standalone-idp-v2-overlay.dts | 9 +++++++++ qcom/monaco-standalone-idp-v2.dtsi | 2 ++ qcom/monaco-standalone-idp-v3-overlay.dts | 9 +++++++++ qcom/monaco-standalone-idp-v3.dtsi | 1 + qcom/monaco-standalone-wdp-v1-overlay.dts | 9 +++++++++ qcom/monaco-standalone-wdp-v1.dtsi | 1 + 11 files changed, 57 insertions(+), 1 deletion(-) create mode 100644 qcom/monaco-standalone-atp-v1-overlay.dts create mode 100644 qcom/monaco-standalone-atp-v1.dtsi create mode 100644 qcom/monaco-standalone-idp-v1-overlay.dts create mode 100644 qcom/monaco-standalone-idp-v1.dtsi create mode 100644 qcom/monaco-standalone-idp-v2-overlay.dts create mode 100644 qcom/monaco-standalone-idp-v2.dtsi create mode 100644 qcom/monaco-standalone-idp-v3-overlay.dts create mode 100644 qcom/monaco-standalone-idp-v3.dtsi create mode 100644 qcom/monaco-standalone-wdp-v1-overlay.dts create mode 100644 qcom/monaco-standalone-wdp-v1.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 2c359468..7b806044 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -126,10 +126,15 @@ MONACO_BASE_DTB += monaco.dtb monacop.dtb MONACO_BOARDS += \ monaco-idp-v1-overlay.dtbo \ + monaco-standalone-idp-v1-overlay.dtbo \ monaco-idp-v2-overlay.dtbo \ + monaco-standalone-idp-v2-overlay.dtbo \ monaco-idp-v3-overlay.dtbo \ + monaco-standalone-idp-v3-overlay.dtbo \ monaco-wdp-v1-overlay.dtbo \ - monaco-atp-v1-overlay.dtbo + monaco-standalone-wdp-v1-overlay.dtbo \ + monaco-atp-v1-overlay.dtbo \ + monaco-standalone-atp-v1-overlay.dtbo monaco-dtb-$(CONFIG_ARCH_MONACO) += \ $(call add-overlays, $(MONACO_BOARDS) ,$(MONACO_BASE_DTB)) diff --git a/qcom/monaco-standalone-atp-v1-overlay.dts b/qcom/monaco-standalone-atp-v1-overlay.dts new file mode 100644 index 00000000..fdd0c502 --- /dev/null +++ b/qcom/monaco-standalone-atp-v1-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "monaco-standalone-atp-v1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco standalone ATP V1.0"; + qcom,board-id = <0x010021 0x1>; +}; diff --git a/qcom/monaco-standalone-atp-v1.dtsi b/qcom/monaco-standalone-atp-v1.dtsi new file mode 100644 index 00000000..d8a5c8c6 --- /dev/null +++ b/qcom/monaco-standalone-atp-v1.dtsi @@ -0,0 +1 @@ +#include "monaco-standalone-idp-v1.dtsi" diff --git a/qcom/monaco-standalone-idp-v1-overlay.dts b/qcom/monaco-standalone-idp-v1-overlay.dts new file mode 100644 index 00000000..22c69bed --- /dev/null +++ b/qcom/monaco-standalone-idp-v1-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "monaco-standalone-idp-v1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco standalone IDP V1.0"; + qcom,board-id = <0x010022 0x1>; +}; diff --git a/qcom/monaco-standalone-idp-v1.dtsi b/qcom/monaco-standalone-idp-v1.dtsi new file mode 100644 index 00000000..b897432c --- /dev/null +++ b/qcom/monaco-standalone-idp-v1.dtsi @@ -0,0 +1 @@ +#include "monaco-idp-v1-common.dtsi" diff --git a/qcom/monaco-standalone-idp-v2-overlay.dts b/qcom/monaco-standalone-idp-v2-overlay.dts new file mode 100644 index 00000000..a3d1a924 --- /dev/null +++ b/qcom/monaco-standalone-idp-v2-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "monaco-standalone-idp-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco standalone IDP V2.0"; + qcom,board-id = <0x020022 0x1>; +}; diff --git a/qcom/monaco-standalone-idp-v2.dtsi b/qcom/monaco-standalone-idp-v2.dtsi new file mode 100644 index 00000000..272f2670 --- /dev/null +++ b/qcom/monaco-standalone-idp-v2.dtsi @@ -0,0 +1,2 @@ + +#include "monaco-standalone-idp-v1.dtsi" diff --git a/qcom/monaco-standalone-idp-v3-overlay.dts b/qcom/monaco-standalone-idp-v3-overlay.dts new file mode 100644 index 00000000..253330f8 --- /dev/null +++ b/qcom/monaco-standalone-idp-v3-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "monaco-standalone-idp-v3.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco standalone IDP V3.0"; + qcom,board-id = <0x030022 0x1>; +}; diff --git a/qcom/monaco-standalone-idp-v3.dtsi b/qcom/monaco-standalone-idp-v3.dtsi new file mode 100644 index 00000000..d8a5c8c6 --- /dev/null +++ b/qcom/monaco-standalone-idp-v3.dtsi @@ -0,0 +1 @@ +#include "monaco-standalone-idp-v1.dtsi" diff --git a/qcom/monaco-standalone-wdp-v1-overlay.dts b/qcom/monaco-standalone-wdp-v1-overlay.dts new file mode 100644 index 00000000..66f93312 --- /dev/null +++ b/qcom/monaco-standalone-wdp-v1-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "monaco-standalone-wdp-v1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco standalone WDP V1.0"; + qcom,board-id = <0x010024 0x1>; +}; diff --git a/qcom/monaco-standalone-wdp-v1.dtsi b/qcom/monaco-standalone-wdp-v1.dtsi new file mode 100644 index 00000000..d8a5c8c6 --- /dev/null +++ b/qcom/monaco-standalone-wdp-v1.dtsi @@ -0,0 +1 @@ +#include "monaco-standalone-idp-v1.dtsi" From ef8065b23f657c469d3cc5b74591ac61d11a1f18 Mon Sep 17 00:00:00 2001 From: Nagireddy Annem Date: Mon, 26 Sep 2022 08:03:45 +0530 Subject: [PATCH 60/65] ARM: dts: msm: Update video pil memory map for monaco Update video pil memory map for monaco. Change-Id: I3e7eb68a4fab3489a34344adc2d75a88df3d54fa --- qcom/monaco.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index be5225ce..856c0ea1 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -198,29 +198,29 @@ reg = <0x0 0x4ab00000 0x0 0x5E00000>; }; - pil_video_mem: pil_video_region@50900000 { + video_mem: video_region@50900000 { no-map; - reg = <0x0 0x50900000 0x0 0x500000>; + reg = <0x0 0x50900000 0x0 0x700000>; }; - pil_adsp_mem: adsp_regions@50E00000 { + pil_adsp_mem: adsp_regions@51000000 { no-map; - reg = <0x0 0x50E00000 0x0 0x1900000>; + reg = <0x0 0x51000000 0x0 0x1900000>; }; - pil_ipa_fw_mem: ips_fw_region@52700000 { + pil_ipa_fw_mem: ips_fw_region@52900000 { no-map; - reg = <0x0 0x52700000 0x0 0x10000>; + reg = <0x0 0x52900000 0x0 0x10000>; }; - pil_ipa_gsi_mem: ipa_gsi_region@52710000 { + pil_ipa_gsi_mem: ipa_gsi_region@52910000 { no-map; - reg = <0x0 0x52710000 0x0 0x5000>; + reg = <0x0 0x52910000 0x0 0x5000>; }; - pil_gpu_mem: gpu_region@52715000 { + pil_gpu_mem: gpu_region@52915000 { no-map; - reg = <0x0 0x52715000 0x0 0x2000>; + reg = <0x0 0x52915000 0x0 0x2000>; }; stats_region: stats_region@60000000 { From c56de2a02f63327aaaf4800bb2ba430dae533af1 Mon Sep 17 00:00:00 2001 From: Priyansh Jain Date: Tue, 11 Oct 2022 16:28:56 +0530 Subject: [PATCH 61/65] ARM: dts: msm: Add thermal, tsens, bcl devicetree for monaco Add thermal, tsens, bcl devicetree nodes for monaco chipset. Change-Id: I8bccd6a945875fd1b50a9071776ed8752192d8e4 --- qcom/monaco-thermal-overlay.dtsi | 14 +- qcom/monaco-thermal.dtsi | 526 +++++++++++++++---------------- qcom/pm5100.dtsi | 30 +- 3 files changed, 285 insertions(+), 285 deletions(-) diff --git a/qcom/monaco-thermal-overlay.dtsi b/qcom/monaco-thermal-overlay.dtsi index eba02e00..d9b05e60 100644 --- a/qcom/monaco-thermal-overlay.dtsi +++ b/qcom/monaco-thermal-overlay.dtsi @@ -12,12 +12,12 @@ trip1_cpu2 { trip = <&pm5100_trip0>; - cooling-device = <&cpu2_isolate 1 1>; + cooling-device = <&cpu2_pause 1 1>; }; trip1_cpu3 { trip = <&pm5100_trip0>; - cooling-device = <&cpu3_isolate 1 1>; + cooling-device = <&cpu3_pause 1 1>; }; }; }; @@ -33,12 +33,12 @@ cpu2_cdev { trip = <&bcl_lvl0>; - cooling-device = <&cpu2_isolate 1 1>; + cooling-device = <&cpu2_pause 1 1>; }; cpu3_cdev { trip = <&bcl_lvl0>; - cooling-device = <&cpu3_isolate 1 1>; + cooling-device = <&cpu3_pause 1 1>; }; gpu_cdev { @@ -60,7 +60,7 @@ cpu1_cdev { trip = <&bcl_lvl1>; - cooling-device = <&cpu1_isolate 1 1>; + cooling-device = <&cpu1_pause 1 1>; }; gpu_cdev { @@ -88,12 +88,12 @@ soc_cpu2 { trip = <&socd_trip>; - cooling-device = <&cpu2_isolate 1 1>; + cooling-device = <&cpu2_pause 1 1>; }; soc_cpu3 { trip = <&socd_trip>; - cooling-device = <&cpu3_isolate 1 1>; + cooling-device = <&cpu3_pause 1 1>; }; gpu_cdev { diff --git a/qcom/monaco-thermal.dtsi b/qcom/monaco-thermal.dtsi index 31ccb318..ae46ae06 100644 --- a/qcom/monaco-thermal.dtsi +++ b/qcom/monaco-thermal.dtsi @@ -1,6 +1,10 @@ #include -&cpufreq_hw { +&msm_gpu { + #cooling-cells = <2>; +}; + +&soc { #address-cells = <1>; #size-cells = <1>; lmh_dcvs0: qcom,limits-dcvs@f550800 { @@ -9,42 +13,61 @@ qcom,affinity = <0>; reg = <0xf550800 0x1000>, <0xf521000 0x1000>; - qcom,no-cooling-device-register; }; - qcom,cpu-isolation { - compatible = "qcom,cpu-isolate"; - cpu0_isolate: cpu0-isolate { - qcom,cpu = <&CPU0>; + qcom,cpu-pause { + compatible = "qcom,thermal-pause"; + + cpu0_pause: cpu0-pause { + qcom,cpus = <&CPU0>; #cooling-cells = <2>; }; - cpu1_isolate: cpu1-isolate { - qcom,cpu = <&CPU1>; + cpu1_pause: cpu1-pause { + qcom,cpus = <&CPU1>; #cooling-cells = <2>; }; - cpu2_isolate: cpu2-isolate { - qcom,cpu = <&CPU2>; + cpu2_pause: cpu2-pause { + qcom,cpus = <&CPU2>; #cooling-cells = <2>; }; - cpu3_isolate: cpu3-isolate { - qcom,cpu = <&CPU3>; + cpu3_pause: cpu3-pause { + qcom,cpus = <&CPU3>; #cooling-cells = <2>; }; + + /* Thermal-engine cooling devices */ + pause-cpu0 { + qcom,cpus = <&CPU0>; + qcom,cdev-alias = "pause-cpu0"; + }; + + pause-cpu1 { + qcom,cpus = <&CPU1>; + qcom,cdev-alias = "pause-cpu1"; + }; + + pause-cpu2 { + qcom,cpus = <&CPU2>; + qcom,cdev-alias = "pause-cpu2"; + }; + + pause-cpu3 { + qcom,cpus = <&CPU3>; + qcom,cdev-alias = "pause-cpu3"; + }; }; -}; -&soc { tsens0:tsens@4410000 { compatible = "qcom,tsens26xx"; reg = <0x04410000 0x20>, <0x04411000 0x140>; reg-names = "tsens_srot_physical", "tsens_tm_physical"; - interrupts-extended = <&intc 0 275 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 190 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <&mpm 89 IRQ_TYPE_EDGE_RISING>; interrupt-names = "tsens-upper-lower", "tsens-critical", @@ -111,15 +134,218 @@ reg = <0xf550800 0x1000>; #cooling-cells = <2>; }; + + qcom,devfreq-cdev { + compatible = "qcom,devfreq-cdev"; + qcom,devfreq = <&msm_gpu>; + }; + + qcom,cpufreq-cdev { + compatible = "qcom,cpufreq-cdev"; + qcom,cpus = <&CPU0>; + }; }; &thermal_zones { - gpu-step { - polling-delay-passive = <10>; + mapss { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 0>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + wlan { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 1>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 2>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu0_2_config: cpu-0-2-config { + temperature = <100000>; + hysteresis = <10000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu0_cdev { + trip = <&cpu0_2_config>; + cooling-device = <&cpu0_pause 1 1>; + }; + + cpu2_cdev { + trip = <&cpu0_2_config>; + cooling-device = <&cpu2_pause 1 1>; + }; + }; + }; + + cpuss-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 3>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu1_3_config: cpu-1-3-config { + temperature = <100000>; + hysteresis = <10000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu1_cdev { + trip = <&cpu1_3_config>; + cooling-device = <&cpu1_pause 1 1>; + }; + + cpu3_cdev { + trip = <&cpu1_3_config>; + cooling-device = <&cpu3_pause 1 1>; + }; + }; + }; + + mdm-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdm0_cx_mon: mdm0-cx-mon { + temperature = <90000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + mdm0-cx-cdev0 { + trip = <&mdm0_cx_mon>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + mdm0-cx-cdev1 { + trip = <&mdm0_cx_mon>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; + + mdm-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdm1_cx_mon: mdm1-cx-mon { + temperature = <90000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + mdm1-cx-cdev0 { + trip = <&mdm1_cx_mon>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + mdm1-cx-cdev1 { + trip = <&mdm1_cx_mon>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; + + gpu { + polling-delay-passive = <0>; polling-delay = <0>; - thermal-governor = "step_wise"; thermal-sensors = <&tsens0 6>; trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + gpu_step_trip: gpu-trip { temperature = <85000>; hysteresis = <0>; @@ -132,6 +358,11 @@ type = "passive"; }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; }; cooling-maps { @@ -154,277 +385,29 @@ }; }; - cpuss-0-step { + camera { polling-delay-passive = <0>; polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 2>; - trips { - cpu0_2_config: cpu-0-2-config { - temperature = <100000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - - cooling-maps { - cpu0_cdev { - trip = <&cpu0_2_config>; - cooling-device = <&cpu0_isolate 1 1>; - }; - - cpu2_cdev { - trip = <&cpu0_2_config>; - cooling-device = <&cpu2_isolate 1 1>; - }; - }; - }; - - cpuss-1-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 3>; - trips { - cpu1_3_config: cpu-1-3-config { - temperature = <100000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - - cooling-maps { - cpu1_cdev { - trip = <&cpu1_3_config>; - cooling-device = <&cpu1_isolate 1 1>; - }; - - cpu3_cdev { - trip = <&cpu1_3_config>; - cooling-device = <&cpu3_isolate 1 1>; - }; - }; - }; - - mdm-0-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 4>; - trips { - mdm0_cx_mon: mdm0-cx-mon { - temperature = <90000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - - cooling-maps { - mdm0-cx-cdev0 { - trip = <&mdm0_cx_mon>; - cooling-device = <&msm_gpu THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - - mdm0-cx-cdev1 { - trip = <&mdm0_cx_mon>; - cooling-device = <&modem_tj 3 3>; - }; - }; - }; - - mdm-1-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 5>; - trips { - mdm1_cx_mon: mdm1-cx-mon { - temperature = <90000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - - cooling-maps { - mdm1-cx-cdev0 { - trip = <&mdm1_cx_mon>; - cooling-device = <&msm_gpu THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - - mdm1-cx-cdev1 { - trip = <&mdm1_cx_mon>; - cooling-device = <&modem_tj 3 3>; - }; - }; - }; - - mapss-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens0 0>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <105000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - wlan-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens0 1>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <105000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpuss-0-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens0 2>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <105000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpuss-1-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens0 3>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <105000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - mdm-0-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens0 4>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <105000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - mdm-1-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens0 5>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <105000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - gpu-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&tsens0 6>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <105000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - camera-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; thermal-sensors = <&tsens0 7>; trips { - active-config0 { + thermal-engine-config { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; reset-mon-cfg { - temperature = <105000>; + temperature = <115000>; hysteresis = <5000>; type = "passive"; }; }; }; - zeroc-0-step { + zeroc { polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&tsens0 16>; - thermal-governor = "step_wise"; trips { zeroc_0_trip: active-config0 { temperature = <1>; @@ -461,7 +444,6 @@ polling-delay = <0>; thermal-sensors = <&qmi_sensor (QMI_MODEM_INST_ID)>; - thermal-governor = "step_wise"; trips { rf_cal_trip: rf-cal-config { temperature = <2000>; diff --git a/qcom/pm5100.dtsi b/qcom/pm5100.dtsi index 39cce56e..121c119a 100644 --- a/qcom/pm5100.dtsi +++ b/qcom/pm5100.dtsi @@ -570,7 +570,6 @@ pm5100-ibat-lvl0 { polling-delay-passive = <0>; polling-delay = <0>; - thermal-governor = "step_wise"; thermal-sensors = <&pm5100_bcl 0>; trips { @@ -585,7 +584,6 @@ pm5100-ibat-lvl1 { polling-delay-passive = <0>; polling-delay = <0>; - thermal-governor = "step_wise"; thermal-sensors = <&pm5100_bcl 1>; trips { @@ -600,10 +598,15 @@ pm5100-bcl-lvl0 { polling-delay-passive = <100>; polling-delay = <0>; - thermal-governor = "step_wise"; thermal-sensors = <&pm5100_bcl 5>; trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + bcl_lvl0: bcl-lvl0 { temperature = <1>; hysteresis = <1>; @@ -615,10 +618,15 @@ pm5100-bcl-lvl1 { polling-delay-passive = <100>; polling-delay = <0>; - thermal-governor = "step_wise"; thermal-sensors = <&pm5100_bcl 6>; trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + bcl_lvl1: bcl-lvl1 { temperature = <1>; hysteresis = <1>; @@ -630,10 +638,15 @@ pm5100-bcl-lvl2 { polling-delay-passive = <100>; polling-delay = <0>; - thermal-governor = "step_wise"; thermal-sensors = <&pm5100_bcl 7>; trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + bcl_lvl2: bcl-lvl2 { temperature = <1>; hysteresis = <1>; @@ -645,10 +658,15 @@ socd { polling-delay-passive = <100>; polling-delay = <0>; - thermal-governor = "step_wise"; thermal-sensors = <&bcl_soc>; trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + socd_trip:socd-trip { temperature = <90>; hysteresis = <0>; From c4a54ee930ffc19e95c5e46c2f967d13a29565f5 Mon Sep 17 00:00:00 2001 From: Anjana Hari Date: Wed, 12 Oct 2022 11:28:20 +0530 Subject: [PATCH 62/65] ARM: dts: msm: Enable primary UFS for Lemans Enable UFS0 instance for Lemans. Change-Id: I1bf4f1f8246f1e538490e56af6caeaa9aa63c0f2 --- qcom/lemans.dtsi | 177 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 177 insertions(+) diff --git a/qcom/lemans.dtsi b/qcom/lemans.dtsi index 9cb45947..c7ef9af7 100644 --- a/qcom/lemans.dtsi +++ b/qcom/lemans.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include / { model = "Qualcomm Technologies, Inc. Lemans"; @@ -24,6 +25,7 @@ aliases { serial0 = &qupv3_se10_2uart; + ufshc1 = &ufshc_mem; /* Embedded UFS slot */ }; soc: soc { }; @@ -988,6 +990,150 @@ thermal_zones: thermal-zones { }; + + ufsphy_mem: ufsphy_mem@1d87000 { + reg = <0x1d87000 0xe10>; + reg-names = "phy_mem"; + #phy-cells = <0>; + + lanes-per-direction = <2>; + clock-names = "ref_clk_src", + "ref_clk", + "ref_aux_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + resets = <&ufshc_mem 0>; + status = "disabled"; + }; + + ufshc_mem: ufshc@1d84000 { + compatible = "qcom,ufshc"; + reg = <0x1d84000 0x3000>; + reg-names = "ufs_mem"; + interrupts = ; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + #reset-cells = <1>; + + lanes-per-direction = <2>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + + freq-table-hz = + <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + qcom,ufs-bus-bw,name = "ufshc_mem"; + qcom,ufs-bus-bw,num-cases = <26>; + qcom,ufs-bus-bw,num-paths = <2>; + qcom,ufs-bus-bw,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <0 0>, <0 0>, /* No vote */ + <922 0>, <1000 0>, /* PWM G1 */ + <1844 0>, <1000 0>, /* PWM G2 */ + <3688 0>, <1000 0>, /* PWM G3 */ + <7376 0>, <1000 0>, /* PWM G4 */ + <1844 0>, <1000 0>, /* PWM G1 L2 */ + <3688 0>, <1000 0>, /* PWM G2 L2 */ + <7376 0>, <1000 0>, /* PWM G3 L2 */ + <14752 0>, <1000 0>, /* PWM G4 L2 */ + <127796 0>, <1000 0>, /* HS G1 RA */ + <255591 0>, <1000 0>, /* HS G2 RA */ + <1492582 0>, <102400 0>, /* HS G3 RA */ + <2915200 0>, <204800 0>, /* HS G4 RA */ + <255591 0>, <1000 0>, /* HS G1 RA L2 */ + <511181 0>, <1000 0>, /* HS G2 RA L2 */ + <1492582 0>, <204800 0>, /* HS G3 RA L2 */ + <2915200 0>, <409600 0>, /* HS G4 RA L2 */ + <149422 0>, <1000 0>, /* HS G1 RB */ + <298189 0>, <1000 0>, /* HS G2 RB */ + <1492582 0>, <102400 0>, /* HS G3 RB */ + <2915200 0>, <204800 0>, /* HS G4 RB */ + <298189 0>, <1000 0>, /* HS G1 RB L2 */ + <596378 0>, <1000 0>, /* HS G2 RB L2 */ + /* As UFS working in HS G3 RB L2 mode, aggregated + * bandwidth (AB) should take care of providing + * optimum throughput requested. However, as tested, + * in order to scale up CNOC clock, instantaneous + * bindwidth (IB) needs to be given a proper value too. + */ + <1492582 0>, <204800 409600>, /* HS G3 RB L2 KBPs */ + <2915200 0>, <409600 409600>, /* HS G4 RB L2 */ + <7643136 0>, <307200 0>; /* Max. bandwidth */ + + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", + "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", + "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", + "MAX"; + + reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + iommus = <&apps_smmu 0x100 0x0>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + qcom,disable-lpm; + + status = "disabled"; + + qos0 { + mask = <0xf0>; + vote = <44>; + }; + + qos1 { + mask = <0x0f>; + vote = <44>; + }; + }; }; #include "lemans-4pmic-regulators.dtsi" @@ -1150,6 +1296,37 @@ status = "ok"; }; +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-waipio"; + + vdda-phy-supply = <&L4A>; + vdda-pll-supply = <&L1C>; + vdda-phy-max-microamp = <137000>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + + vcc-supply = <&L8A>; + vcc-voltage-level = <2504000 2506000>; + vcc-max-microamp = <1100000>; + + vccq-supply = <&L4C>; + vccq-max-microamp = <1200000>; + + vccq2-supply = <&S4A>; + vccq2-max-microamp = <800000>; + + qcom,vddp-ref-clk-supply = <&L4C>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; + #include "lemans-debug.dtsi" #include "lemans-qupv3.dtsi" From 4caedac05760fa2fade24465737cc6df2d7ab207 Mon Sep 17 00:00:00 2001 From: Zou Shunxiang Date: Tue, 20 Sep 2022 18:55:17 +0800 Subject: [PATCH 63/65] ARM: dts: msm: Add direwolf dts files for lvgvm Add base direwolf dts files for lvgvm. Change-Id: I08ace37bc86a8da6196fbc9e1e6a75e2b87134b7 --- qcom/Makefile | 12 +++++++++--- qcom/direwolf-vm-lv-overlay.dts | 11 +++++++++++ qcom/direwolf-vm-lv.dts | 10 ++++++++++ qcom/direwolf-vm-lv.dtsi | 2 ++ qcom/direwolf-vm.dtsi | 7 +++++++ 5 files changed, 39 insertions(+), 3 deletions(-) create mode 100644 qcom/direwolf-vm-lv-overlay.dts create mode 100644 qcom/direwolf-vm-lv.dts create mode 100644 qcom/direwolf-vm-lv.dtsi create mode 100644 qcom/direwolf-vm.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 7b806044..d231a7d4 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -235,10 +235,16 @@ SA8155_LA_GVM_BASE_DTB += sa8155-vm-la.dtb SA8155_LA_GVM_BOARDS += \ sa8155-vm-la-overlay.dtbo -autogvm-dtb-$(CONFIG_QTI_QUIN_GVM) += \ - $(call add-overlays, $(SA8155_LA_GVM_BOARDS),$(SA8155_LA_GVM_BASE_DTB)) -autogvm-overlays-dtb-$(CONFIG_QTI_QUIN_GVM) += $(SA8155_LA_GVM_BOARDS) $(SA8155_LA_GVM_BASE_DTB) +DIREWOLF_LV_GVM_BASE_DTB += direwolf-vm-lv.dtb +DIREWOLF_LV_GVM_BOARDS += \ + direwolf-vm-lv-overlay.dtbo + +autogvm-dtb-$(CONFIG_QTI_QUIN_GVM) += \ + $(call add-overlays, $(SA8155_LA_GVM_BOARDS),$(SA8155_LA_GVM_BASE_DTB)) \ + $(call add-overlays, $(DIREWOLF_LV_GVM_BOARDS),$(DIREWOLF_LV_GVM_BASE_DTB)) +autogvm-overlays-dtb-$(CONFIG_QTI_QUIN_GVM) += \ + $(SA8155_LA_GVM_BOARDS) $(DIREWOLF_LV_GVM_BOARDS) $(SA8155_LA_GVM_BASE_DTB) $(DIREWOLF_LV_GVM_BASE_DTB) dtb-y += $(autogvm-dtb-y) SCUBA_AUTO_BASE_DTB += scuba_auto.dtb diff --git a/qcom/direwolf-vm-lv-overlay.dts b/qcom/direwolf-vm-lv-overlay.dts new file mode 100644 index 00000000..db42d935 --- /dev/null +++ b/qcom/direwolf-vm-lv-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "direwolf-vm.dtsi" +#include "direwolf-vm-lv.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Direwolf Single LV Virtual Machine"; + compatible = "qcom,direwolf", "qcom,quinvm"; + qcom,board-id = <0 0x1000002>; +}; diff --git a/qcom/direwolf-vm-lv.dts b/qcom/direwolf-vm-lv.dts new file mode 100644 index 00000000..6758100c --- /dev/null +++ b/qcom/direwolf-vm-lv.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "direwolf-vm.dtsi" +#include "direwolf-vm-lv.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Direwolf Single LV Virtual Machine"; + compatible = "qcom,direwolf", "qcom,quinvm"; + qcom,board-id = <0 0x1000002>; +}; diff --git a/qcom/direwolf-vm-lv.dtsi b/qcom/direwolf-vm-lv.dtsi new file mode 100644 index 00000000..17f1e228 --- /dev/null +++ b/qcom/direwolf-vm-lv.dtsi @@ -0,0 +1,2 @@ +&soc { +}; diff --git a/qcom/direwolf-vm.dtsi b/qcom/direwolf-vm.dtsi new file mode 100644 index 00000000..285fb72f --- /dev/null +++ b/qcom/direwolf-vm.dtsi @@ -0,0 +1,7 @@ +#include "quin-vm-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Direwolf Virtual Machine"; + qcom,msm-name = "SA_DIREWOLF_IVI"; + qcom,msm-id = <460 0x10000>; +}; From 694e3b6ce0bf6acbeb9b0a8114e8eecc81fcca02 Mon Sep 17 00:00:00 2001 From: Priyansh Jain Date: Wed, 12 Oct 2022 14:45:17 +0530 Subject: [PATCH 64/65] ARM: dts: qcom: Enable quiet-therm thermalzone for khaje Enable quiet-therm thermalzone for khaje. Change-Id: I973165ce921ef41dff4b1bc843da99ac0cab6488 --- qcom/bengal-thermal.dtsi | 120 --------------------------------------- qcom/khaje-qrd.dtsi | 7 --- 2 files changed, 127 deletions(-) diff --git a/qcom/bengal-thermal.dtsi b/qcom/bengal-thermal.dtsi index 023d19e1..913eb910 100644 --- a/qcom/bengal-thermal.dtsi +++ b/qcom/bengal-thermal.dtsi @@ -856,132 +856,12 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&pm6125_adc_tm 1>; - status = "disabled"; trips { active-config0 { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; - - skin_batt_trip0: batt-trip0 { - temperature = <39000>; - hysteresis = <2000>; - type = "passive"; - }; - - skin_modem_trip0: modem-trip0 { - temperature = <40000>; - hysteresis = <4000>; - type = "passive"; - }; - - skin_gold_trip: gold-trip { - temperature = <40000>; - hysteresis = <0>; - type = "passive"; - }; - - skin_batt_trip1: batt-trip1 { - temperature = <41000>; - hysteresis = <2000>; - type = "passive"; - }; - - skin_silver_trip: silver-trip { - temperature = <41000>; - hysteresis = <0>; - type = "passive"; - }; - - skin_modem_trip1: modem-trip1 { - temperature = <42000>; - hysteresis = <4000>; - type = "passive"; - }; - - skin_modem_trip2: modem-trip2 { - temperature = <43000>; - hysteresis = <4000>; - type = "passive"; - }; - - skin_batt_trip2: batt-trip2 { - temperature = <43000>; - hysteresis = <2000>; - type = "passive"; - }; - - skin_gpu_trip: gpu-trip { - temperature = <43000>; - hysteresis = <0>; - type = "passive"; - }; - - skin_batt_trip3: batt-trip3 { - temperature = <45000>; - hysteresis = <2000>; - type = "passive"; - }; - - skin_modem_trip3: modem-trip3 { - temperature = <50000>; - hysteresis = <5000>; - type = "passive"; - }; - - skin_hvx_trip: hvx-trip { - temperature = <52000>; - hysteresis = <4000>; - type = "passive"; - }; - }; - - cooling-maps { - gold_cdev { - trip = <&skin_gold_trip>; - cooling-device = <&CPU4 0 3>; - }; - - silver_cdev { - trip = <&skin_silver_trip>; - cooling-device = <&CPU0 0 2>; - }; - - gpu_cdev { - trip = <&skin_gpu_trip>; - cooling-device = <&msm_gpu 0 3>; - }; - - hvx_cdev { - trip = <&skin_hvx_trip>; - cooling-device = <&cdsp_sw 4 4>; - }; - - mdm_cdev0 { - trip = <&skin_modem_trip0>; - cooling-device = <&modem_proc 1 1>; - }; - - mdm_cdev1 { - trip = <&skin_modem_trip1>; - cooling-device = <&modem_pa 1 1>; - }; - - mdm_cdev2 { - trip = <&skin_modem_trip2>; - cooling-device = <&modem_pa 2 2>; - }; - - mdm_cdev3 { - trip = <&skin_modem_trip3>; - cooling-device = <&modem_pa 3 3>; - }; - - mdm_cdev4 { - trip = <&skin_modem_trip3>; - cooling-device = <&modem_proc 3 3>; - }; }; }; diff --git a/qcom/khaje-qrd.dtsi b/qcom/khaje-qrd.dtsi index 485d0e1d..c628fabd 100644 --- a/qcom/khaje-qrd.dtsi +++ b/qcom/khaje-qrd.dtsi @@ -209,9 +209,6 @@ &thermal_zones { quiet-therm { polling-delay-passive = <2000>; - polling-delay = <0>; - thermal-sensors = <&pm6125_adc_tm 1>; - trips { quiet_batt_trip0: batt-trip0 { temperature = <41000>; @@ -316,10 +313,6 @@ }; pa-therm0 { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm6125_adc_tm 0>; - trips { pa_therm0_trip0: pa-therm0-trip0 { temperature = <52000>; From f3c31092887d64a1a2ce689c9f468ed97c6a083c Mon Sep 17 00:00:00 2001 From: Nishant Pandey Date: Wed, 12 Oct 2022 05:08:49 -0700 Subject: [PATCH 65/65] ARM: dts: msm: Add tz-log dt node in sa410m Add tz-log dt node in sa410m. Change-Id: I1229501fa62c54bc0c9669f9784614d907485665 --- qcom/sa410m.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/sa410m.dtsi b/qcom/sa410m.dtsi index 28354d71..bd53a80f 100644 --- a/qcom/sa410m.dtsi +++ b/qcom/sa410m.dtsi @@ -291,6 +291,14 @@ clock-frequency = <19200000>; }; + qcom_tzlog: tz-log@c125720 { + compatible = "qcom,tz-log"; + reg = <0xc125720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + }; + memtimer: timer@f120000 { #address-cells = <1>; #size-cells = <1>;