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dt-bindings: Clean up files with copyright markings

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Fixes: 1cc7395a15 ("dt-bindings: Add devicetree bindings to devicetree project")
Change-Id: I29b9b601593e27c9f4445eb02c580bc9bd4ef17a
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Blagovest Kolenichev
2021-08-23 08:10:09 -07:00
parent b146158974
commit e7ca1ca91a
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53
bindings/net/can/mpc5xxx-mscan.txt
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CAN Device Tree Bindings
------------------------
(c) 2006-2009 Secret Lab Technologies Ltd
Grant Likely <grant.likely@secretlab.ca>
fsl,mpc5200-mscan nodes
-----------------------
In addition to the required compatible-, reg- and interrupt-properties, you can
also specify which clock source shall be used for the controller:
- fsl,mscan-clock-source : a string describing the clock source. Valid values
are: "ip" for ip bus clock
"ref" for reference clock (XTAL)
"ref" is default in case this property is not
present.
fsl,mpc5121-mscan nodes
-----------------------
In addition to the required compatible-, reg- and interrupt-properties, you can
also specify which clock source and divider shall be used for the controller:
- fsl,mscan-clock-source : a string describing the clock source. Valid values
are: "ip" for ip bus clock
"ref" for reference clock
"sys" for system clock
If this property is not present, an optimal CAN
clock source and frequency based on the system
clock will be selected. If this is not possible,
the reference clock will be used.
- fsl,mscan-clock-divider: for the reference and system clock, an additional
clock divider can be specified. By default, a
value of 1 is used.
Note that the MPC5121 Rev. 1 processor is not supported.
Examples:
can@1300 {
compatible = "fsl,mpc5121-mscan";
interrupts = <12 0x8>;
interrupt-parent = <&ipic>;
reg = <0x1300 0x80>;
};
can@1380 {
compatible = "fsl,mpc5121-mscan";
interrupts = <13 0x8>;
interrupt-parent = <&ipic>;
reg = <0x1380 0x80>;
fsl,mscan-clock-source = "ref";
fsl,mscan-clock-divider = <3>;
};

255
bindings/serial/8250.yaml
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# Copyright 2020 Lubomir Rintel <lkundrak@v3.sk>
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/8250.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: UART (Universal Asynchronous Receiver/Transmitter) bindings
maintainers:
- devicetree@vger.kernel.org
allOf:
- $ref: /schemas/serial.yaml#
- if:
anyOf:
- required:
- aspeed,lpc-io-reg
- required:
- aspeed,lpc-interrupts
- required:
- aspeed,sirq-polarity-sense
then:
properties:
compatible:
const: aspeed,ast2500-vuart
- if:
properties:
compatible:
const: mrvl,mmp-uart
then:
properties:
reg-shift:
const: 2
required:
- reg-shift
- if:
not:
properties:
compatible:
items:
- enum:
- ns8250
- ns16450
- ns16550
- ns16550a
then:
anyOf:
- required: [ clock-frequency ]
- required: [ clocks ]
properties:
compatible:
oneOf:
- const: ns8250
- const: ns16450
- const: ns16550
- const: ns16550a
- const: ns16850
- const: aspeed,ast2400-vuart
- const: aspeed,ast2500-vuart
- const: intel,xscale-uart
- const: mrvl,pxa-uart
- const: nuvoton,wpcm450-uart
- const: nuvoton,npcm750-uart
- const: nvidia,tegra20-uart
- const: nxp,lpc3220-uart
- items:
- enum:
- altr,16550-FIFO32
- altr,16550-FIFO64
- altr,16550-FIFO128
- fsl,16550-FIFO64
- fsl,ns16550
- andestech,uart16550
- nxp,lpc1850-uart
- opencores,uart16550-rtlsvn105
- ti,da830-uart
- const: ns16550a
- items:
- enum:
- ns16750
- cavium,octeon-3860-uart
- xlnx,xps-uart16550-2.00.b
- ralink,rt2880-uart
- enum:
- ns16550 # Deprecated, unless the FIFO really is broken
- ns16550a
- items:
- enum:
- ralink,mt7620a-uart
- ralink,rt3052-uart
- ralink,rt3883-uart
- const: ralink,rt2880-uart
- enum:
- ns16550 # Deprecated, unless the FIFO really is broken
- ns16550a
- items:
- enum:
- mediatek,mt7622-btif
- mediatek,mt7623-btif
- const: mediatek,mtk-btif
- items:
- enum:
- mediatek,mt7622-btif
- mediatek,mt7623-btif
- const: mediatek,mtk-btif
- items:
- const: mrvl,mmp-uart
- const: intel,xscale-uart
- items:
- enum:
- nvidia,tegra30-uart
- nvidia,tegra114-uart
- nvidia,tegra124-uart
- nvidia,tegra186-uart
- nvidia,tegra194-uart
- nvidia,tegra210-uart
- const: nvidia,tegra20-uart
reg:
maxItems: 1
interrupts:
maxItems: 1
clock-frequency: true
clocks:
maxItems: 1
resets:
maxItems: 1
current-speed:
$ref: /schemas/types.yaml#/definitions/uint32
description: The current active speed of the UART.
reg-offset:
description: |
Offset to apply to the mapbase from the start of the registers.
reg-shift:
description: Quantity to shift the register offsets by.
reg-io-width:
description: |
The size (in bytes) of the IO accesses that should be performed on the
device. There are some systems that require 32-bit accesses to the
UART (e.g. TI davinci).
used-by-rtas:
type: boolean
description: |
Set to indicate that the port is in use by the OpenFirmware RTAS and
should not be registered.
no-loopback-test:
type: boolean
description: |
Set to indicate that the port does not implement loopback test mode.
fifo-size:
$ref: /schemas/types.yaml#/definitions/uint32
description: The fifo size of the UART.
auto-flow-control:
type: boolean
description: |
One way to enable automatic flow control support. The driver is
allowed to detect support for the capability even without this
property.
tx-threshold:
description: |
Specify the TX FIFO low water indication for parts with programmable
TX FIFO thresholds.
overrun-throttle-ms:
description: |
How long to pause uart rx when input overrun is encountered.
rts-gpios: true
cts-gpios: true
dtr-gpios: true
dsr-gpios: true
rng-gpios: true
dcd-gpios: true
aspeed,sirq-polarity-sense:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: |
Phandle to aspeed,ast2500-scu compatible syscon alongside register
offset and bit number to identify how the SIRQ polarity should be
configured. One possible data source is the LPC/eSPI mode bit. Only
applicable to aspeed,ast2500-vuart.
deprecated: true
aspeed,lpc-io-reg:
$ref: '/schemas/types.yaml#/definitions/uint32'
description: |
The VUART LPC address. Only applicable to aspeed,ast2500-vuart.
aspeed,lpc-interrupts:
$ref: "/schemas/types.yaml#/definitions/uint32-array"
minItems: 2
maxItems: 2
description: |
A 2-cell property describing the VUART SIRQ number and SIRQ
polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH). Only
applicable to aspeed,ast2500-vuart.
required:
- reg
- interrupts
unevaluatedProperties: false
examples:
- |
serial@80230000 {
compatible = "ns8250";
reg = <0x80230000 0x100>;
interrupts = <10>;
reg-shift = <2>;
clock-frequency = <48000000>;
};
- |
#include <dt-bindings/gpio/gpio.h>
serial@49042000 {
compatible = "andestech,uart16550", "ns16550a";
reg = <0x49042000 0x400>;
interrupts = <80>;
clock-frequency = <48000000>;
cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
- |
#include <dt-bindings/clock/aspeed-clock.h>
#include <dt-bindings/interrupt-controller/irq.h>
serial@1e787000 {
compatible = "aspeed,ast2500-vuart";
reg = <0x1e787000 0x40>;
reg-shift = <2>;
interrupts = <8>;
clocks = <&syscon ASPEED_CLK_APB>;
no-loopback-test;
aspeed,lpc-io-reg = <0x3f8>;
aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
};
...