From ea4c3553690101f59a9cde098a361bf3ebd5c5f6 Mon Sep 17 00:00:00 2001
From: Tushar Nimkar <tnimkar@qti.qualcomm.com>
Date: Mon, 23 May 2022 11:48:13 +0530
Subject: [PATCH] ARM: dts: msm: Add stats support for sdxpinn

This change adds various stats support.

Change-Id: I71d9c14e039badc8995d162cb7e4d686c4d500b1
---
 qcom/sdxpinn.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/qcom/sdxpinn.dtsi b/qcom/sdxpinn.dtsi
index 222e0a40..fc01b05e 100644
--- a/qcom/sdxpinn.dtsi
+++ b/qcom/sdxpinn.dtsi
@@ -265,6 +265,27 @@
 		};
 	};
 
+	cpuss-sleep-stats@17800054 {
+		compatible = "qcom,cpuss-sleep-stats-v2";
+		reg = <0x17800054 0x4>, <0x17810054 0x4>, <0x17820054 0x4>,
+		      <0x17830054 0x4>, <0x17880098 0x4>, <0x178c0000 0x10000>;
+		reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1",
+			    "seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3",
+			    "l3_seq_lpm_cntr_cfg", "apss_seq_mem_base";
+		num-cpus = <4>;
+	};
+
+	soc-sleep-stats@c3f0000 {
+		compatible = "qcom,rpmh-sleep-stats";
+		reg = <0xc3f0000 0x400>;
+		ss-name = "modem", "adsp", "apss";
+	};
+
+	subsystem-sleep-stats@c3f0000 {
+		compatible = "qcom,subsystem-sleep-stats";
+		reg = <0xc3f0000 0x400>;
+	};
+
 	arch_timer: timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,