From ec1c0d2963ae669890c2ee37ce7ce82f49eceeae Mon Sep 17 00:00:00 2001
From: Suraj Jaiswal <jsuraj@qti.qualcomm.com>
Date: Tue, 14 Jul 2020 15:03:25 +0530
Subject: [PATCH] ARM: dts: msm: STMMAC changes for SA8155 LV

Add support for STMMAC in SA8155 dtsi.

Change-Id: I68855a9bb8492abdf366e07959c398534b28788e
---
 qcom/sa8155-v2.dtsi |  4 +++
 qcom/sa8155.dtsi    | 74 +++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 78 insertions(+)

diff --git a/qcom/sa8155-v2.dtsi b/qcom/sa8155-v2.dtsi
index 09d9488c..87fd3673 100644
--- a/qcom/sa8155-v2.dtsi
+++ b/qcom/sa8155-v2.dtsi
@@ -6,3 +6,7 @@
 	qcom,msm-name = "SA8155 V2";
 	qcom,msm-id = <362 0x20000>;
 };
+
+&ethqos_hw {
+	emac-core-version = <0x20010002>;
+};
diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi
index 2a7e73df..0966ebf2 100644
--- a/qcom/sa8155.dtsi
+++ b/qcom/sa8155.dtsi
@@ -61,6 +61,80 @@
 		read-only;
 		ranges;
 	};
+	ethqos_hw: qcom,ethernet@00020000 {
+		compatible = "qcom,stmmac-ethqos";
+		qcom,arm-smmu;
+		reg = <0x20000 0x10000>,
+			<0x36000 0x100>,
+			<0x3D00000 0x300000>;
+		reg-names = "stmmaceth", "rgmii","tlmm-central-base";
+		clocks = <&gcc GCC_EMAC_AXI_CLK>,
+			<&gcc GCC_EMAC_SLV_AHB_CLK>,
+			<&gcc GCC_EMAC_PTP_CLK>,
+			<&gcc GCC_EMAC_RGMII_CLK>;
+		clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
+		interrupts-extended = <&intc 0 689 4>, <&intc 0 699 4>,
+			<&tlmm 124 2>;
+		interrupt-names = "macirq", "eth_lpi",
+			"phy-intr";
+		snps,tso;
+		rx-fifo-depth = <4096>;
+		tx-fifo-depth = <4096>;
+		snps,reset-gpios = <&tlmm 79 GPIO_ACTIVE_HIGH>;
+		qcom,phy-intr-redirect = <&tlmm 124 GPIO_ACTIVE_LOW>;
+		gdsc_emac-supply = <&emac_gdsc>;
+
+		pinctrl-names = "dev-emac-mdc",
+			"dev-emac-mdio",
+			"dev-emac-rgmii_txd0_state",
+			"dev-emac-rgmii_txd1_state",
+			"dev-emac-rgmii_txd2_state",
+			"dev-emac-rgmii_txd3_state",
+			"dev-emac-rgmii_txc_state",
+			"dev-emac-rgmii_tx_ctl_state",
+			"dev-emac-rgmii_rxd0_state",
+			"dev-emac-rgmii_rxd1_state",
+			"dev-emac-rgmii_rxd2_state",
+			"dev-emac-rgmii_rxd3_state",
+			"dev-emac-rgmii_rxc_state",
+			"dev-emac-rgmii_rx_ctl_state",
+			"dev-emac-phy_intr",
+			"dev-emac-phy_reset_state",
+			"dev-emac_pin_pps_0";
+
+		pinctrl-0 = <&emac_mdc>;
+		pinctrl-1 = <&emac_mdio>;
+
+		pinctrl-2 = <&emac_rgmii_txd0>;
+		pinctrl-3 = <&emac_rgmii_txd1>;
+		pinctrl-4 = <&emac_rgmii_txd2>;
+		pinctrl-5 = <&emac_rgmii_txd3>;
+		pinctrl-6 = <&emac_rgmii_txc>;
+		pinctrl-7 = <&emac_rgmii_tx_ctl>;
+
+		pinctrl-8 = <&emac_rgmii_rxd0>;
+		pinctrl-9 = <&emac_rgmii_rxd1>;
+		pinctrl-10 = <&emac_rgmii_rxd2>;
+		pinctrl-11 = <&emac_rgmii_rxd3>;
+		pinctrl-12 = <&emac_rgmii_rxc>;
+		pinctrl-13 = <&emac_rgmii_rx_ctl>;
+
+		pinctrl-14 = <&emac_phy_intr>;
+		pinctrl-15 = <&emac_phy_reset_state>;
+		pinctrl-16 = <&emac_pin_pps_0>;
+
+		snps,reset-delays-us = <0 11000 70000>;
+		phy-mode = "rgmii";
+		eth-c22-mdio-probe;
+
+		ethqos_emb_smmu: ethqos_emb_smmu {
+			compatible = "qcom,emac-smmu-embedded";
+			iommus = <&apps_smmu 0x3C0 0x0>;
+			qcom,iommu-dma = "fastmap";
+			qcom,iommu-dma-addr-pool = <0x80000000 0x40000000>;
+		};
+	};
+
 };
 
 &gpucc {