From fe2c1c62756effd24826d83a43653b39d69ae0d5 Mon Sep 17 00:00:00 2001 From: Adithya Naga Sai Tirumanisetti Date: Tue, 8 Nov 2022 09:32:05 +0530 Subject: [PATCH] ARM: dts: qcom: Add HS-I2S Device tree support on SA8195 adding device node for HS-I2S driver Change-Id: Iecb4ede108ba06ad4619deaab8b71bc0c1bdc330 --- qcom/sa8195p.dtsi | 102 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 101 insertions(+), 1 deletion(-) diff --git a/qcom/sa8195p.dtsi b/qcom/sa8195p.dtsi index e381c9a9..a4ad019f 100644 --- a/qcom/sa8195p.dtsi +++ b/qcom/sa8195p.dtsi @@ -19,10 +19,110 @@ #size-cells = <1>; read-only; ranges; - gpu_speed_bin: gpu_speed_bin@4002 { reg = <0x4002 0x2>; bits = <4 8>; + }; + }; + + hsi2s: qcom,hsi2s { + compatible = "qcom,sa8195-hsi2s", "qcom,hsi2s"; + number-of-interfaces = <3>; + reg = <0x172C0000 0x28000>, + <0x17080000 0xE000>; + reg-names = "lpa_if", "lpass_tcsr"; + interrupts = ; + number-of-rate-detectors = <2>; + rate-detector-interfaces = <0 1>; + iommus = <&apps_smmu 0x1B5C 0x1>, + <&apps_smmu 0x1B5E 0x0>; + qcom,iommu-dma-addr-pool = <0x0 0xFFFFFFFF>; + + sdr0: qcom,hs0_i2s { + compatible = "qcom,hsi2s-interface"; + minor-number = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hs1_i2s_mclk_active &hs1_i2s_sck_active + &hs1_i2s_ws_active &hs1_i2s_data0_active + &hs1_i2s_data1_active>; + pinctrl-1 = <&hs1_i2s_mclk_sleep &hs1_i2s_sck_sleep + &hs1_i2s_ws_sleep &hs1_i2s_data0_sleep + &hs1_i2s_data1_sleep>; + bit-clock-hz = <12288000>; + data-buffer-ms = <10>; + bit-depth = <32>; + spkr-channel-count = <2>; + mic-channel-count = <2>; + pcm-rate = <2>; + pcm-sync-src = <0>; + aux-mode = <0>; + rpcm-width = <1>; + tpcm-width = <1>; + enable-tdm = <1>; + tdm-rate = <32>; + tdm-rpcm-width = <16>; + tdm-tpcm-width = <16>; + tdm-sync-delay = <2>; + tdm-inv-sync = <0>; + pcm-lane-config = <1>; + }; + + sdr1: qcom,hs1_i2s { + compatible = "qcom,hsi2s-interface"; + minor-number = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hs2_i2s_mclk_active &hs2_i2s_sck_active + &hs2_i2s_ws_active &hs2_i2s_data0_active + &hs2_i2s_data1_active>; + pinctrl-1 = <&hs2_i2s_mclk_sleep &hs2_i2s_sck_sleep + &hs2_i2s_ws_sleep &hs2_i2s_data0_sleep + &hs2_i2s_data1_sleep>; + bit-clock-hz = <12288000>; + data-buffer-ms = <10>; + bit-depth = <32>; + spkr-channel-count = <2>; + mic-channel-count = <2>; + pcm-rate = <2>; + pcm-sync-src = <0>; + aux-mode = <0>; + rpcm-width = <1>; + tpcm-width = <1>; + enable-tdm = <1>; + tdm-rate = <32>; + tdm-rpcm-width = <16>; + tdm-tpcm-width = <16>; + tdm-sync-delay = <2>; + tdm-inv-sync = <0>; + pcm-lane-config = <1>; + }; + + sdr2: qcom,hs2_i2s { + compatible = "qcom,hsi2s-interface"; + minor-number = <2>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hs3_i2s_mclk_active &hs3_i2s_sck_active + &hs3_i2s_ws_active &hs3_i2s_data0_active + &hs3_i2s_data1_active>; + pinctrl-1 = <&hs3_i2s_mclk_sleep &hs3_i2s_sck_sleep + &hs3_i2s_ws_sleep &hs3_i2s_data0_sleep + &hs3_i2s_data1_sleep>; + bit-clock-hz = <12288000>; + data-buffer-ms = <10>; + bit-depth = <32>; + spkr-channel-count = <2>; + mic-channel-count = <2>; + pcm-rate = <2>; + pcm-sync-src = <0>; + aux-mode = <0>; + rpcm-width = <1>; + tpcm-width = <1>; + enable-tdm = <1>; + tdm-rate = <32>; + tdm-rpcm-width = <16>; + tdm-tpcm-width = <16>; + tdm-sync-delay = <2>; + tdm-inv-sync = <0>; + pcm-lane-config = <1>; }; }; };