From f23a7016df817a100f87eff7df523d7c026175a0 Mon Sep 17 00:00:00 2001
From: Akshay Adiga <aadiga@qti.qualcomm.com>
Date: Fri, 22 Jul 2022 00:58:30 -0700
Subject: [PATCH] ARM: dts: msm: Add smmu dt nodes for scuba_auto

Add smmu dt nodes for scuba_auto

Change-Id: Ieb3f7e19a2478dc0f0bf861ab7fe6f5392c0abd7
---
 qcom/msm-arm-smmu-scuba_auto.dtsi | 158 ++++++++++++++++++++++++++++++
 qcom/scuba_auto.dtsi              |  11 +++
 2 files changed, 169 insertions(+)
 create mode 100644 qcom/msm-arm-smmu-scuba_auto.dtsi

diff --git a/qcom/msm-arm-smmu-scuba_auto.dtsi b/qcom/msm-arm-smmu-scuba_auto.dtsi
new file mode 100644
index 00000000..bbf7df3d
--- /dev/null
+++ b/qcom/msm-arm-smmu-scuba_auto.dtsi
@@ -0,0 +1,158 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&soc {
+
+	apps_smmu: apps-smmu@0xc600000 {
+				status = "okay";
+				compatible = "qcom,qsmmu-v500";
+				reg = <0xc600000 0x80000>,
+					<0xc782000 0x20>;
+				reg-names = "base", "tcu-base";
+				#iommu-cells = <2>;
+				qcom,skip-init;
+				qcom,use-3-lvl-tables;
+				#global-interrupts = <1>;
+				#size-cells = <1>;
+				#address-cells = <1>;
+				ranges;
+				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+
+				interconnects = <&bimc MASTER_AMPSS_M0
+						&system_noc SLAVE_TCU>;
+
+				qcom,active-only;
+				qcom,actlr =
+					/* For rt TBU +3 deep PF */
+					<0x400 0x3ff 0x103>,
+					/* For nrt TBU +3 deep PF */
+					<0x800 0x3ff 0x103>;
+
+				anoc_1_tbu: anoc_1_tbu@0xc785000 {
+					compatible = "qcom,qsmmuv500-tbu";
+					reg = <0xc785000 0x1000>,
+						<0xc782200 0x8>;
+					reg-names = "base", "status-reg";
+					qcom,stream-id-range = <0x0 0x400>;
+					interconnects = <&bimc MASTER_AMPSS_M0
+						&config_noc SLAVE_IMEM_CFG>,
+						<&bimc MASTER_AMPSS_M0
+						&system_noc SLAVE_TCU>;
+					qcom,iova-width = <36>;
+				};
+
+				mm_rt_tbu: mm_rt_tbu@0xc789000 {
+					compatible = "qcom,qsmmuv500-tbu";
+					reg = <0xc789000 0x1000>,
+						<0xc782208 0x8>;
+					reg-names = "base", "status-reg";
+					qcom,stream-id-range = <0x400 0x400>;
+					interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+					interconnects = <&mmrt_virt MASTER_MDP_PORT0
+						&bimc SLAVE_EBI_CH0>,
+						<&bimc MASTER_AMPSS_M0
+						 &system_noc SLAVE_TCU>;
+					qcom,active-only;
+					qcom,iova-width = <32>;
+				};
+
+				mm_nrt_tbu: mm_nrt_tbu@0xc78d000 {
+					compatible = "qcom,qsmmuv500-tbu";
+					reg = <0xc78d000 0x1000>,
+						<0xc782210 0x8>;
+					reg-names = "base", "status-reg";
+					qcom,stream-id-range = <0x800 0x400>;
+					interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+					interconnects = <&mmnrt_virt MASTER_CAMNOC_SF
+						&bimc SLAVE_EBI_CH0>,
+						<&bimc MASTER_AMPSS_M0
+						&system_noc SLAVE_TCU>;
+					qcom,active-only;
+					qcom,iova-width = <32>;
+				};
+
+	};
+
+	dma_dev@0x0 {
+		compatible = "qcom,iommu-dma";
+		memory-region = <&system_cma>;
+	};
+
+	iommu_test_device {
+		compatible = "qcom,iommu-debug-test";
+		apps_iommu_test_device {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x1E0 0>;
+		};
+
+		apps_iommu_coherent_test_device {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x1E1 0>;
+			dma-coherent;
+		};
+	};
+
+};
diff --git a/qcom/scuba_auto.dtsi b/qcom/scuba_auto.dtsi
index b4e1b53f..d8a21d0d 100644
--- a/qcom/scuba_auto.dtsi
+++ b/qcom/scuba_auto.dtsi
@@ -547,6 +547,15 @@
 		clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
 			<&rpmcc RPM_SMD_BIMC_A_CLK>;
 	};
+
+	qcom-secure-buffer {
+		compatible = "qcom,secure-buffer";
+	};
+
+	qcom_scm: qcomscm {
+		compatible = "qcom,scm";
+	};
+
 };
 
 #include "pm2250-rpm-regulator.dtsi"
@@ -618,3 +627,5 @@
 	reg = <0x599100c 0x4>;
 	status = "ok";
 };
+
+#include "msm-arm-smmu-scuba_auto.dtsi"