From f490eaa904ccf2e6af212f22fd11c67c23ee2ca4 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Tue, 31 May 2022 09:59:26 +0530 Subject: [PATCH] dt-bindings: interconnect: add EPSS L3 bindings Add bindings for the new interconnect EPSS L3 driver. Change-Id: I812f0fd9690b3c5489e8d4d37e685dab03e84a97 --- bindings/interconnect/qcom,epss-l3.txt | 35 ++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 bindings/interconnect/qcom,epss-l3.txt diff --git a/bindings/interconnect/qcom,epss-l3.txt b/bindings/interconnect/qcom,epss-l3.txt new file mode 100644 index 00000000..5459dfc8 --- /dev/null +++ b/bindings/interconnect/qcom,epss-l3.txt @@ -0,0 +1,35 @@ +Qualcomm Technologies, Inc. EPSS L3 interconnect driver binding +----------------------------------------------------------- + +The EPSS L3 Interconnect provider supports the scaling of L3 cache +performance states of the CPU subsystem. + +Required properties : +- compatible : shall contain only one of the following: + "qcom,lahaina-epss-l3-shared", + "qcom,lahaina-epss-l3-cpu"; +- reg : Address and length of the register set for the device +- clock-names: should contain "xo", "alternate" +- clocks: list of phandle and clock specifier pairs corresponding to + entries in the clock-names property. +- #interconnect-cells : should contain 1 + +Examples: + +epss_l3_shared: l3_shared@18590000 { + reg = <0x18590000 0x1000>; + compatible = "qcom,lahaina-epss-l3-shared"; + #interconnect-cells = <1>; + clock-names = "xo", "alternate"; + clocks = <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_GPLL0>; +}; + +epss_l3_cpu: l3_cpu@18590000{ + reg = <0x18590000 0x4000>; + compatible = "qcom,lahaina-epss-l3-cpu"; + #interconnect-cells = <1>; + clock-names = "xo", "alternate"; + clocks = <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_GPLL0>; +};