From f63ea151cfa621c1ec28d68b712e5faf8ff2c052 Mon Sep 17 00:00:00 2001
From: Imran Shaik <imrashai@qti.qualcomm.com>
Date: Wed, 27 Jul 2022 17:58:44 +0530
Subject: [PATCH] ARM: dts: msm: Add support for DEBUGCC node for SDXPINN

Add the support for debug clock controller node for SDXPINN platform.

Change-Id: I17edde591410b356bba0736721924f534d6d1112
---
 qcom/sdxpinn-rumi.dtsi |  5 +++++
 qcom/sdxpinn.dtsi      | 22 ++++++++++++++++++++++
 2 files changed, 27 insertions(+)

diff --git a/qcom/sdxpinn-rumi.dtsi b/qcom/sdxpinn-rumi.dtsi
index 1daa913c..28a223da 100644
--- a/qcom/sdxpinn-rumi.dtsi
+++ b/qcom/sdxpinn-rumi.dtsi
@@ -171,6 +171,11 @@
 	clock-output-names = "rpmh_clocks";
 };
 
+&debugcc {
+	clocks = <&bi_tcxo>, <&gcc 0>;
+	clock-names = "xo_clk_src", "gcc";
+};
+
 &gcc {
 	clocks = <&bi_tcxo>, <&pcie20_phy_aux_clk>, <&pcie_1_pipe_clk>, <&pcie_2_pipe_clk>,
 		 <&pcie_pipe_clk>, <&sleep_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
diff --git a/qcom/sdxpinn.dtsi b/qcom/sdxpinn.dtsi
index a7da0ea2..450006e6 100644
--- a/qcom/sdxpinn.dtsi
+++ b/qcom/sdxpinn.dtsi
@@ -529,6 +529,28 @@
 		#reset-cells = <1>;
 	};
 
+	apsscc: syscon@17aa0000 {
+		compatible = "syscon";
+		reg = <0x17aa0000 0x1c>;
+	};
+
+	mccc: syscon@190ba000 {
+		compatible = "syscon";
+		reg = <0x190ba000 0x54>;
+	};
+
+	debugcc: clock-controller@0 {
+		compatible = "qcom,sdxpinn-debugcc";
+		qcom,apsscc = <&apsscc>;
+		qcom,gcc = <&gcc>;
+		qcom,mccc = <&mccc>;
+		clocks = <&rpmhcc RPMH_CXO_CLK>,
+			<&gcc 0>;
+		clock-names = "xo_clk_src",
+			"gcc";
+		#clock-cells = <1>;
+	};
+
 	/* GCC GDSCs */
 	gcc_emac0_gdsc: qcom,gdsc@f1004 {
 		compatible = "qcom,gdsc";