From f6d308d0859ad6ccfe45c95a2e6fef838f0e2cf3 Mon Sep 17 00:00:00 2001
From: Anaadi Mishra <anaadim@qti.qualcomm.com>
Date: Sun, 9 May 2021 11:35:34 +0530
Subject: [PATCH] bindings: clock: Add support for SCUBA clock controllers

Update the GCC, GPUCC, DISPCC, RPMCC and DEBUGCC controllers
bindings for SCUBA.

Change-Id: I4c2f325c0c677e2f0fa457d809dbbaf21be60d3f
---
 bindings/clock/qcom,debugcc.txt | 1 +
 bindings/clock/qcom,dispcc.txt  | 1 +
 bindings/clock/qcom,gcc.txt     | 1 +
 bindings/clock/qcom,gpucc.txt   | 1 +
 bindings/clock/qcom,rpmcc.txt   | 1 +
 5 files changed, 5 insertions(+)

diff --git a/bindings/clock/qcom,debugcc.txt b/bindings/clock/qcom,debugcc.txt
index 976ad2e4..af6c6d84 100644
--- a/bindings/clock/qcom,debugcc.txt
+++ b/bindings/clock/qcom,debugcc.txt
@@ -17,6 +17,7 @@ Required properties :
 			"qcom,sc8180x-debugcc"
 			"qcom,monaco-debugcc"
 			"qcom,sdxpinn-debugcc"
+			"qcom,scuba-debugcc"
 
 - qcom,gcc: phandle to the GCC device node.
 - qcom,videocc: phandle to the Video CC device node.
diff --git a/bindings/clock/qcom,dispcc.txt b/bindings/clock/qcom,dispcc.txt
index 8582ae8a..73c95a14 100644
--- a/bindings/clock/qcom,dispcc.txt
+++ b/bindings/clock/qcom,dispcc.txt
@@ -25,6 +25,7 @@ Required properties :
 			"qcom,lemans-dispcc0"
 			"qcom,lemans-dispcc1"
 			"qcom,kona-dispcc"
+			"qcom,scuba-dispcc"
 
 - reg : shall contain base register location and length.
 - #clock-cells : from common clock binding, shall contain 1.
diff --git a/bindings/clock/qcom,gcc.txt b/bindings/clock/qcom,gcc.txt
index c98564c2..a30e449f 100644
--- a/bindings/clock/qcom,gcc.txt
+++ b/bindings/clock/qcom,gcc.txt
@@ -40,6 +40,7 @@ Required properties :
 			"qcom,gcc-sc8180x"
 			"qcom,monaco-gcc"
 			"qcom,sdxpinn-gcc"
+			"qcom,scuba-gcc"
 
 - reg : shall contain base register location and length
 - vdd_cx-supply: The vdd_cx logic rail supply.
diff --git a/bindings/clock/qcom,gpucc.txt b/bindings/clock/qcom,gpucc.txt
index ae2a9757..189e6354 100644
--- a/bindings/clock/qcom,gpucc.txt
+++ b/bindings/clock/qcom,gpucc.txt
@@ -15,6 +15,7 @@ Required properties :
 		"qcom,khaje-gpucc",
 		"qcom,sc8180x-gpucc".
 		"qcom,monaco-gpucc",
+		"qcom,scuba-gpucc"
 
 - reg: shall contain base register offset and size.
 - reg-names: names of registers listed in the same order as in the reg property.
diff --git a/bindings/clock/qcom,rpmcc.txt b/bindings/clock/qcom,rpmcc.txt
index b6b4629f..6ba066de 100644
--- a/bindings/clock/qcom,rpmcc.txt
+++ b/bindings/clock/qcom,rpmcc.txt
@@ -28,6 +28,7 @@ Required properties :
 			"qcom,rpmcc-holi", "qcom,rpmcc"
 			"qcom,rpmcc-khaje", "qcom,rpmcc"
 			"qcom,rpmcc-monaco", "qcom,rpmcc"
+			"qcom,rpmcc-scuba", "qcom,rpmcc"
 
 - #clock-cells : shall contain 1