From fae1190d5a17608e47539dbecca48567ca8090a8 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Tue, 9 Aug 2022 18:35:50 +0800 Subject: [PATCH] ARM: dts: msm: add smmu config for etr on sdxpinn Add smmu node config for etr on sdxpinn. Change-Id: Ifb1f04e5522109da48e543685b5cca9cf5174952 --- qcom/sdxpinn-coresight.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/sdxpinn-coresight.dtsi b/qcom/sdxpinn-coresight.dtsi index 36c0699e..266bb98a 100644 --- a/qcom/sdxpinn-coresight.dtsi +++ b/qcom/sdxpinn-coresight.dtsi @@ -2185,9 +2185,9 @@ <0x24064000 0x16000>; reg-names = "tmc-base", "bam-base"; - //qcom,iommu-dma = "bypass"; - //iommus = <&apps_smmu 0x0180 0>, - // <&apps_smmu 0x0160 0>; + qcom,iommu-dma = "bypass"; + iommus = <&apps_smmu 0x0180 0>, + <&apps_smmu 0x0160 0>; qcom,iommu-dma-addr-pool = <0x0 0xffc00000>; @@ -2226,7 +2226,7 @@ coresight-name = "coresight-tmc-etr1"; - //iommus = <&apps_smmu 0x01a0 0>; + iommus = <&apps_smmu 0x01a0 0>; qcom,iommu-dma-addr-pool = <0x0 0xffc00000>; dma-coherent;