From fd4db3b32f51b5f9ba8ba38d2407e595449ccbee Mon Sep 17 00:00:00 2001
From: Neeraj Upadhyay <neeraju@qti.qualcomm.com>
Date: Sun, 4 Apr 2021 17:31:48 +0530
Subject: [PATCH] dt-bindings: Add device-tree bindings for
 gic-interrupt-router

Add device tree bindings for qcom,gic-interrupt-router.

Change-Id: Ibb0b8e8a2c0ac875476d61f1ce54e76673818f15
---
 .../soc/qcom/qcom,gic-interrupt-router.yaml   | 31 +++++++++++++++++++
 1 file changed, 31 insertions(+)
 create mode 100644 bindings/soc/qcom/qcom,gic-interrupt-router.yaml

diff --git a/bindings/soc/qcom/qcom,gic-interrupt-router.yaml b/bindings/soc/qcom/qcom,gic-interrupt-router.yaml
new file mode 100644
index 00000000..357b4440
--- /dev/null
+++ b/bindings/soc/qcom/qcom,gic-interrupt-router.yaml
@@ -0,0 +1,31 @@
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,gic-interrupt-router.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. GIC Interrupt Router
+
+properties:
+  compatible:
+    Usage: required
+    Value type: <string>
+    Definition: Must be "qcom,gic-intr-routing"
+
+  qcom,gic-class0-cpus:
+    Usage: required
+    Value type: <prop-encoded-array>
+    Definition: List of CPUs in GIC class 0.
+
+  qcom,gic-class1-cpus:
+    Usage: required
+    Value type: <prop-encoded-array>
+    Definition: List of CPUs in GIC class 1.
+
+examples:
+  - |+
+    qcom,gic-interrupt-router {
+      compatible = "qcom,gic-intr-routing";
+      qcom,gic-class0-cpus = <0 1 2 3>;
+      qcom,gic-class1-cpus = <4 5 6 7>;
+    };
+...