From a548591fee6b4884e18991f2d1245e3aa7049e14 Mon Sep 17 00:00:00 2001
From: Sarthak Garg <sartgarg@qti.qualcomm.com>
Date: Sun, 5 Jun 2022 10:44:07 +0530
Subject: [PATCH] ARM: dts: msm: Add Qpic Nand support for sdxpinn in device
 tree

Add QPIC NAND Controller support for sdxpinn in device tree.

Change-Id: I3c6de28f8277daf5078186796fad70fae23f39c7
---
 qcom/sdxpinn.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/qcom/sdxpinn.dtsi b/qcom/sdxpinn.dtsi
index 83db095c..04d74526 100644
--- a/qcom/sdxpinn.dtsi
+++ b/qcom/sdxpinn.dtsi
@@ -588,6 +588,23 @@
 		regulator-name = "gcc_usb3_phy_gdsc";
 	};
 
+	qnand_1: nand@1c98000 {
+		compatible = "qcom,msm-nand";
+		reg =   <0x01c98000 0x1000>,
+			<0x01c9C000 0x1c000>;
+		reg-names =     "nand_phys",
+				"bam_phys";
+		qcom,reg-adjustment-offset = <0x4000>;
+
+		interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "bam_irq";
+
+		clock-names = "core_clk";
+		clocks = <&rpmhcc RPMH_QPIC_CLK>;
+
+		status = "disabled";
+	};
+
 	tlmm: pinctrl@f000000 {
 		compatible = "qcom,sdxpinn-pinctrl";
 		reg = <0x0F000000 0x400000>;