From fe036bf2f26139df920e10ba1ff2fe695e8d41eb Mon Sep 17 00:00:00 2001 From: Sanjay Dwivedi Date: Sun, 29 May 2022 00:50:32 +0530 Subject: [PATCH] ARM: dts: msm: Add Initial device tree for SA410M RUMI Add initial device tree support for SA410M RUMI target. Change-Id: I8f5d78eabf3af511abda0fc96394011d0f373f6b --- bindings/arm/msm/msm.txt | 4 + qcom/Makefile | 4 + qcom/sa410m-rumi.dts | 10 ++ qcom/sa410m-rumi.dtsi | 9 ++ qcom/sa410m.dtsi | 204 +++++++++++++++++++++++++++++++++++++++ 5 files changed, 231 insertions(+) create mode 100644 qcom/sa410m-rumi.dts create mode 100644 qcom/sa410m-rumi.dtsi create mode 100644 qcom/sa410m.dtsi diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index 9858b875..eda71945 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -101,6 +101,9 @@ SoCs: - SDXPINN compatible = "qcom,sdxpinn" +- SA410M + compatible = "qcom,sa410m" + Generic board variants: - CDP device: @@ -294,3 +297,4 @@ compatible = "qcom,khaje-idp" compatible = "qcom,khaje-qrd" compatible = "qcom,khaje-atp" compatible = "qcom,sdxpinn-rumi" +compatible = "qcom,sa410m-rumi" diff --git a/qcom/Makefile b/qcom/Makefile index 43826219..fa647044 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -135,6 +135,10 @@ dtb-y += $(sdmsteppeauto-dtb-y) sdxpinn-dtb-$(CONFIG_ARCH_SDXPINN) += sdxpinn-rumi.dtb sa525m-rumi.dtb dtb-y += $(sdxpinn-dtb-y) +sa410m-dtb-$(CONFIG_ARCH_SA410M) += \ + sa410m-rumi.dtb +dtb-y += $(sa410m-dtb-y) + endif ifeq ($(CONFIG_ARCH_KALAMA), y) diff --git a/qcom/sa410m-rumi.dts b/qcom/sa410m-rumi.dts new file mode 100644 index 00000000..233e2d35 --- /dev/null +++ b/qcom/sa410m-rumi.dts @@ -0,0 +1,10 @@ +/dts-v1/; +/memreserve/ 0x80000000 0x00010000; + +#include "sa410m-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA410M RUMI"; + compatible = "qcom,sa410m", "qcom,rumi", "qcom,sa410m-rumi"; + qcom,board-id = <15 0x0>; +}; diff --git a/qcom/sa410m-rumi.dtsi b/qcom/sa410m-rumi.dtsi new file mode 100644 index 00000000..b56f336c --- /dev/null +++ b/qcom/sa410m-rumi.dtsi @@ -0,0 +1,9 @@ +#include "sa410m.dtsi" + +&arch_timer { + clock-frequency = <500000>; +}; + +&memtimer { + clock-frequency = <500000>; +}; diff --git a/qcom/sa410m.dtsi b/qcom/sa410m.dtsi new file mode 100644 index 00000000..37e8efca --- /dev/null +++ b/qcom/sa410m.dtsi @@ -0,0 +1,204 @@ +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&intc>; + + memory { device_type = "memory"; reg = <0 0 0 0>; }; + + reserved_memory: reserved-memory { }; + + firmware: firmware {}; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x80000000>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + }; + + L1_I_0: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_0: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x80000000>; + next-level-cache = <&L2_0>; + + L1_I_1: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_1: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x80000000>; + next-level-cache = <&L2_0>; + + L1_I_2: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_2: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x80000000>; + next-level-cache = <&L2_0>; + + L1_I_3: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_3: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + }; + }; + + chosen { + }; + + soc: soc { }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&intc>; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0xf200000 0x10000>, /* GICD */ + <0xf300000 0x100000>; /* GICR * 8 */ + interrupts = ; + #gpio-cells = <0>; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + memtimer: timer@f120000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xf120000 0x1000>; + clock-frequency = <19200000>; + + frame@f121000 { + frame-number = <0>; + interrupts = , + ; + reg = <0xf121000 0x1000>, + <0xf122000 0x1000>; + }; + + frame@f123000 { + frame-number = <1>; + interrupts = ; + reg = <0xf123000 0x1000>; + status = "disabled"; + }; + + frame@f124000 { + frame-number = <2>; + interrupts = ; + reg = <0xf124000 0x1000>; + status = "disabled"; + }; + + frame@f125000 { + frame-number = <3>; + interrupts = ; + reg = <0xf125000 0x1000>; + status = "disabled"; + }; + + frame@f126000 { + frame-number = <4>; + interrupts = ; + reg = <0xf126000 0x1000>; + status = "disabled"; + }; + + frame@f127000 { + frame-number = <5>; + interrupts = ; + reg = <0xf127000 0x1000>; + status = "disabled"; + }; + + frame@f128000 { + frame-number = <6>; + interrupts = ; + reg = <0xf128000 0x1000>; + status = "disabled"; + }; + }; +};