diff --git a/qcom/sa410m-pcie.dtsi b/qcom/sa410m-pcie.dtsi new file mode 100644 index 00000000..b5268ced --- /dev/null +++ b/qcom/sa410m-pcie.dtsi @@ -0,0 +1,258 @@ +#include + +&soc { + pcie0: qcom,pcie@05020000 { + compatible = "qcom,pci-msm"; + cell-index = <0>; + + reg = <0x05020000 0x3000>, + <0x05026000 0x1000>, + <0x18000000 0xf20>, + <0x18000f20 0xa8>, + <0x18001000 0x1000>, + <0x18100000 0x100000>, + <0x05023000 0x1000>; + + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", + "conf", "mhi"; + #adddress-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x18200000 0x18200000 0x0 0x100000>, + <0x02000000 0x0 0x18300000 0x18300000 0x0 0x27d00000>; + + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; + + qcom,phy-sequence = <0x0800 0x01 0x0 + 0x0804 0x03 0x0 + 0x0034 0x18 0x0 + 0x0038 0x10 0x0 + 0x0070 0x0f 0x0 + 0x00c8 0x01 0x0 + 0x0128 0x00 0x0 + 0x0144 0xff 0x0 + 0x0148 0x1f 0x0 + 0x0194 0x06 0x0 + 0x0048 0x0f 0x0 + 0x0178 0x00 0x0 + 0x019c 0x01 0x0 + 0x018c 0x20 0x0 + 0x0184 0x0a 0x0 + 0x00b4 0x20 0x0 + 0x000c 0x09 0x0 + 0x00ac 0x04 0x0 + 0x00d0 0x82 0x0 + 0x00e4 0x03 0x0 + 0x00e0 0x55 0x0 + 0x00dc 0x55 0x0 + 0x0054 0x00 0x0 + 0x0050 0x0d 0x0 + 0x004c 0x04 0x0 + 0x0174 0x35 0x0 + 0x003c 0x02 0x0 + 0x0040 0x1f 0x0 + 0x0078 0x04 0x0 + 0x0084 0x16 0x0 + 0x0090 0x30 0x0 + 0x010c 0x00 0x0 + 0x0108 0x80 0x0 + 0x00a8 0x01 0x0 + 0x000c 0x0a 0x0 + 0x0010 0x01 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0014 0x02 0x0 + 0x0018 0x00 0x0 + 0x0024 0x2f 0x0 + 0x0028 0x19 0x0 + 0x0268 0x45 0x0 + 0x0194 0x06 0x0 + 0x024c 0x02 0x0 + 0x02ac 0x12 0x0 + 0x0510 0x1c 0x0 + 0x051c 0x14 0x0 + 0x04d8 0x01 0x0 + 0x04dc 0x00 0x0 + 0x04e0 0xdb 0x0 + 0x0448 0x4b 0x0 + 0x041c 0x04 0x0 + 0x0410 0x04 0x0 + 0x0074 0x19 0x0 + 0x0854 0x04 0x0 + 0x09ac 0x00 0x0 + 0x08a0 0x40 0x0 + 0x09e0 0x00 0x0 + 0x09dc 0x40 0x0 + 0x09a8 0x00 0x0 + 0x08a4 0x40 0x0 + 0x08a8 0x73 0x0 + 0x09b0 0x07 0x0 + 0x09d8 0x99 0x0 + 0x0824 0x15 0x0 + 0x0828 0x0e 0x0 + 0x0800 0x00 0x0 + 0x0808 0x03 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_clkreq_default + &pcie0_perst_default + &pcie0_wake_default>; + + perst-gpio = <&tlmm 25 0>; + wake-gpio = <&tlmm 26 0>; + + gdsc-core-vdd-supply = <&gcc_pcie_0_gdsc>; + vreg-1p2-supply = <&L16A>; + vreg-0p9-supply = <&L12A>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + vreg-mx-supply = <&VDD_MX_LEVEL>; + + qcom,vreg-1p2-voltage-level = <1800000 1800000 24000>; + qcom,vreg-0p9-voltage-level = <925000 925000 24000>; + qcom,vreg-cx-voltage-level = ; + qcom,vreg-mx-voltage-level = ; + + dma-coherent; + qcom,bw-scale = /* Gen1 */ + ; + + interconnect-names = "icc_path"; + interconnects = <&sys_noc MASTER_PCIE &bimc_noc SLAVE_EBI_CH0>; + + msi-parent = <&pcie0_msi>; + + qcom,no-l0s-supported; + qcom,no-l1-supported; + qcom,no-l1ss-supported; + qcom,no-aux-clk-sync; + + qcom,max-link-speed = <0x2>; + qcom,target-link-speed = <0x2>; + + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x4000000>; + + qcom,phy-status-offset = <0x974>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x804>; + qcom,core-preset = <0x77777777>; + + qcom,boot-option = <0x0>; + + linux,pci-domain = <0>; + + qcom,pcie-phy-ver = <2609>; + qcom,aux-clk-freq = <20>; + + qcom,smmu-sid-base = <0x0400>; + + iommu-map = <0x0 &apps_smmu 0x0400 0x1>, + <0x100 &apps_smmu 0x0401 0x1>, + <0x200 &apps_smmu 0x0402 0x1>, + <0x300 &apps_smmu 0x0403 0x1>, + <0x400 &apps_smmu 0x0404 0x1>, + <0x500 &apps_smmu 0x0405 0x1>, + <0x600 &apps_smmu 0x0406 0x1>, + <0x700 &apps_smmu 0x0407 0x1>, + <0x800 &apps_smmu 0x0408 0x1>, + <0x900 &apps_smmu 0x0409 0x1>, + <0xa00 &apps_smmu 0x040a 0x1>, + <0xb00 &apps_smmu 0x040b 0x1>, + <0xc00 &apps_smmu 0x040c 0x1>, + <0xd00 &apps_smmu 0x040d 0x1>, + <0xe00 &apps_smmu 0x040e 0x1>, + <0xf00 &apps_smmu 0x040f 0x1>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&pcie_0_pipe_clk>; + + clock-names = "pcie_pipe_clk", "pcie_ref_clk_src", + "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", + "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", + "pcie_0_slv_q2a_axi_clk", + "pcie_pipe_clk_ext_src"; + + clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>; + + clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>; + + resets = <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_PHY_BCR>; + + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; + + pcie0_rp: pcie0_rp { + reg = <0 0 0 0 0>; + }; + }; + + pcie0_msi: qcom,pcie0_msi@0xf200040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0xf200040 0x0>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; +}; + diff --git a/qcom/sa410m-pinctrl.dtsi b/qcom/sa410m-pinctrl.dtsi index e80bf951..609b06df 100644 --- a/qcom/sa410m-pinctrl.dtsi +++ b/qcom/sa410m-pinctrl.dtsi @@ -739,6 +739,44 @@ rclk { pins = "sdc1_rclk"; bias-pull-down; + pcie0 { + pcie0_clkreq_default: pcie0_clkreq_default { + mux { + pins = "gpio24"; + function = "PCIE0_CLK_REQ"; + }; + + config { + pins = "gpio24"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_perst_default: pcie0_perst_default { + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie0_wake_default: pcie0_wake_default { + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + drive-strength = <2>; + bias-pull-up; + }; }; }; }; diff --git a/qcom/sa410m.dtsi b/qcom/sa410m.dtsi index 58bd314b..e5a4a65b 100644 --- a/qcom/sa410m.dtsi +++ b/qcom/sa410m.dtsi @@ -29,6 +29,7 @@ serial0 = &qupv3_se4_2uart; qpic_nand1 = &qnand_1; mmc0 = &sdhc_1; /*SDC1 eMMC slot*/ + pci-domain0 = &pcie0; }; firmware: firmware {}; @@ -203,7 +204,7 @@ }; chosen { - bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 pcie_ports=compat"; }; soc: soc { }; @@ -936,6 +937,7 @@ #include "monaco-gdsc.dtsi" #include "sa410m-qupv3.dtsi" #include "sa410m-dma-heap.dtsi" +#include "sa410m-pcie.dtsi" &gcc_emac0_gdsc { status = "ok";