From b1aa2ac535ad2b4ca7143cbb2f91f1ef6020d3b1 Mon Sep 17 00:00:00 2001
From: Imran Shaik <imrashai@qti.qualcomm.com>
Date: Tue, 28 Jun 2022 15:36:29 +0530
Subject: [PATCH] ARM: dts: msm: Add the support for cpufreq node on SDXPINN

Add the support for cpufreq node to enable the cpufreq scaling
on SDXPINN platform.

Change-Id: I5caf63008c67e5eff817ae2ff1659fa725e231e4
---
 qcom/sdxpinn-rumi.dtsi |  4 ++++
 qcom/sdxpinn.dtsi      | 22 +++++++++++++++++++++-
 2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/qcom/sdxpinn-rumi.dtsi b/qcom/sdxpinn-rumi.dtsi
index 2d648004..4d0e7198 100644
--- a/qcom/sdxpinn-rumi.dtsi
+++ b/qcom/sdxpinn-rumi.dtsi
@@ -248,3 +248,7 @@
 &gcc_usb3_phy_gdsc {
 	compatible = "regulator-fixed";
 };
+
+&cpufreq_hw {
+	clocks = <&bi_tcxo>, <&gcc GPLL0>;
+};
diff --git a/qcom/sdxpinn.dtsi b/qcom/sdxpinn.dtsi
index c55bb099..f7a0c035 100644
--- a/qcom/sdxpinn.dtsi
+++ b/qcom/sdxpinn.dtsi
@@ -20,7 +20,7 @@
 	reserved_memory: reserved-memory { };
 
 	chosen: chosen {
-		bootargs = "disable_dma32=on swiotlb=noforce kpti=off";
+		bootargs = "disable_dma32=on swiotlb=noforce kpti=off cpufreq.default_governor=performance";
 	};
 
 	aliases {
@@ -46,6 +46,7 @@
 			capacity-dmips-mhz = <1024>;
 			dynamic-power-coefficient = <100>;
 			#cooling-cells = <2>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 			L2_0: l2-cache {
 				compatible = "arm,arch-cache";
 				cache-level = <2>;
@@ -70,6 +71,7 @@
 			capacity-dmips-mhz = <1024>;
 			dynamic-power-coefficient = <100>;
 			#cooling-cells = <2>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 
 			L2_1: l2-cache {
 				compatible = "arm,arch-cache";
@@ -90,6 +92,7 @@
 			capacity-dmips-mhz = <1024>;
 			dynamic-power-coefficient = <100>;
 			#cooling-cells = <2>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 
 			L2_2: l2-cache {
 				compatible = "arm,arch-cache";
@@ -110,6 +113,7 @@
 			capacity-dmips-mhz = <1024>;
 			dynamic-power-coefficient = <100>;
 			#cooling-cells = <2>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 
 			L2_3: l2-cache {
 				compatible = "arm,arch-cache";
@@ -568,6 +572,22 @@
 		#clock-cells = <1>;
 	};
 
+	cpufreq_hw: qcom,cpufreq-hw {
+		compatible = "qcom,cpufreq-epss";
+		reg = <0x17d91000 0x1000>;
+		reg-names = "freq-domain0";
+		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+		clock-names = "xo", "alternate";
+		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "dcvsh0_int";
+		#freq-domain-cells = <1>;
+	};
+
+	qcom,cpufreq-hw-debug {
+		compatible = "qcom,cpufreq-hw-epss-debug";
+		qcom,freq-hw-domain = <&cpufreq_hw 0>;
+	};
+
 	/* GCC GDSCs */
 	gcc_emac0_gdsc: qcom,gdsc@f1004 {
 		compatible = "qcom,gdsc";