mirror of
https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-02-01 05:00:27 +00:00
cf68933e6a
Remove unsupported routes from crow tanggu platform. update snd card name for idp and qrd tangu variant. Change-Id: I7849c94351c9c021fe6a250e67c6d7ca3b60fae7
761 lines
25 KiB
Plaintext
761 lines
25 KiB
Plaintext
#include <bindings/qcom,audio-ext-clk.h>
|
|
#include <bindings/qcom,lpass-cdc-clk-rsc.h>
|
|
#include <bindings/audio-codec-port-types.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include "crow-lpi.dtsi"
|
|
|
|
&lpass_cdc {
|
|
qcom,num-macros = <4>;
|
|
qcom,lpass-cdc-version = <6>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
lpass-cdc-clk-rsc-mngr {
|
|
compatible = "qcom,lpass-cdc-clk-rsc-mngr";
|
|
qcom,fs-gen-sequence = <0x3000 0x1 0x1>, <0x3004 0x3 0x3>,
|
|
<0x3004 0x3 0x1>, <0x3080 0x2 0x2>;
|
|
qcom,rx_mclk_mode_muxsel = <0x033A40D8>;
|
|
qcom,wsa_mclk_mode_muxsel = <0x033A20E0>;
|
|
qcom,va_mclk_mode_muxsel = <0x03420000>;
|
|
clock-names = "tx_core_clk", "rx_core_clk", "wsa_core_clk",
|
|
"wsa2_core_clk", "rx_tx_core_clk",
|
|
"wsa_tx_core_clk", "wsa2_tx_core_clk", "va_core_clk";
|
|
clocks = <&clock_audio_tx_1 0>, <&clock_audio_rx_1 0>,
|
|
<&clock_audio_wsa_1 0>,
|
|
<&clock_audio_wsa_2 0>, <&clock_audio_rx_tx 0>,
|
|
<&clock_audio_wsa_tx 0>, <&clock_audio_wsa2_tx 0>,
|
|
<&clock_audio_va_1 0>;
|
|
};
|
|
|
|
va_macro: va-macro@33F0000 {
|
|
compatible = "qcom,lpass-cdc-va-macro";
|
|
reg = <0x33F0000 0x0>;
|
|
clock-names = "lpass_audio_hw_vote";
|
|
clocks = <&lpass_audio_hw_vote 0>;
|
|
qcom,va-dmic-sample-rate = <600000>;
|
|
qcom,va-clk-mux-select = <1>;
|
|
qcom,va-island-mode-muxsel = <0x03420000>;
|
|
qcom,default-clk-id = <TX_CORE_CLK>;
|
|
qcom,use-clk-id = <VA_CORE_CLK>;
|
|
qcom,is-used-swr-gpio = <1>;
|
|
qcom,va-swr-gpios = <&va_swr_gpios>;
|
|
swr2: va_swr_master {
|
|
compatible = "qcom,swr-mstr";
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
clock-names = "lpass_core_hw_vote",
|
|
"lpass_audio_hw_vote";
|
|
clocks = <&lpass_core_hw_vote 0>,
|
|
<&lpass_audio_hw_vote 0>;
|
|
qcom,swr_master_id = <3>;
|
|
qcom,mipi-sdw-block-packing-mode = <1>;
|
|
swrm-io-base = <0x33b0000 0x0>;
|
|
interrupts =
|
|
<GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "swr_master_irq", "swr_wake_irq";
|
|
qcom,swr-wakeup-required = <1>;
|
|
qcom,swr-num-ports = <5>;
|
|
qcom,swr-port-mapping = <1 SWRM_TX_PCM_OUT 0x3>,
|
|
<2 SWRM_TX1_CH1 0x1>, <2 SWRM_TX1_CH2 0x2>,
|
|
<2 SWRM_TX1_CH3 0x4>, <2 SWRM_TX1_CH4 0x8>,
|
|
<3 SWRM_TX2_CH1 0x1>, <3 SWRM_TX2_CH2 0x2>,
|
|
<3 SWRM_TX2_CH3 0x4>, <3 SWRM_TX2_CH4 0x8>,
|
|
<4 SWRM_TX3_CH1 0x1>, <4 SWRM_TX3_CH2 0x2>,
|
|
<4 SWRM_TX3_CH3 0x4>, <4 SWRM_TX3_CH4 0x8>,
|
|
<5 SWRM_TX_PCM_IN 0x3>;
|
|
qcom,swr-num-dev = <5>;
|
|
qcom,swr-clock-stop-mode0 = <1>;
|
|
qcom,swr-mstr-irq-wakeup-capable = <1>;
|
|
qcom,is-always-on = <1>;
|
|
wcd937x_tx_slave: wcd937x-tx-slave {
|
|
compatible = "qcom,wcd937x-slave";
|
|
reg = <0x0A 0x01170223>;
|
|
};
|
|
|
|
wcd939x_tx_slave: wcd939x-tx-slave {
|
|
status = "disabled";
|
|
compatible = "qcom,wcd939x-slave";
|
|
reg = <0x0E 0x01170223>;
|
|
};
|
|
|
|
swr_dmic_04: dmic_swr@58350223 {
|
|
compatible = "qcom,swr-dmic";
|
|
reg = <0x08 0x58350223>;
|
|
sound-name-prefix = "SWR_MIC3";
|
|
qcom,codec-name = "swr-dmic.04";
|
|
qcom,swr-dmic-supply = <3>;
|
|
qcom,wcd-handle = <&wcd937x_codec>;
|
|
status = "disabled";
|
|
};
|
|
|
|
swr_dmic_03: dmic_swr@58350222 {
|
|
compatible = "qcom,swr-dmic";
|
|
reg = <0x08 0x58350222>;
|
|
sound-name-prefix = "SWR_MIC2";
|
|
qcom,codec-name = "swr-dmic.03";
|
|
qcom,swr-dmic-supply = <1>;
|
|
qcom,wcd-handle = <&wcd937x_codec>;
|
|
status = "disabled";
|
|
};
|
|
|
|
swr_dmic_02: dmic_swr@58350221 {
|
|
compatible = "qcom,swr-dmic";
|
|
reg = <0x08 0x58350221>;
|
|
sound-name-prefix = "SWR_MIC1";
|
|
qcom,codec-name = "swr-dmic.02";
|
|
qcom,swr-dmic-supply = <1>;
|
|
qcom,wcd-handle = <&wcd937x_codec>;
|
|
status = "disabled";
|
|
};
|
|
|
|
swr_dmic_01: dmic_swr@58350220 {
|
|
compatible = "qcom,swr-dmic";
|
|
reg = <0x08 0x58350220>;
|
|
sound-name-prefix = "SWR_MIC0";
|
|
qcom,codec-name = "swr-dmic.01";
|
|
qcom,swr-dmic-supply = <3>;
|
|
qcom,wcd-handle = <&wcd937x_codec>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
tx_macro: tx-macro@3220000 {
|
|
compatible = "qcom,lpass-cdc-tx-macro";
|
|
reg = <0x3220000 0x0>;
|
|
qcom,default-clk-id = <TX_CORE_CLK>;
|
|
qcom,tx-dmic-sample-rate = <2400000>;
|
|
qcom,is-used-swr-gpio = <0>;
|
|
};
|
|
|
|
rx_macro: rx-macro@3200000 {
|
|
compatible = "qcom,lpass-cdc-rx-macro";
|
|
reg = <0x3200000 0x0>;
|
|
qcom,rx-swr-gpios = <&rx_swr_gpios>;
|
|
qcom,rx_mclk_mode_muxsel = <0x033A40D8>;
|
|
qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;
|
|
qcom,default-clk-id = <RX_TX_CORE_CLK>;
|
|
clock-names = "rx_mclk2_2x_clk";
|
|
clocks = <&clock_audio_rx_mclk2_2x_clk 0>;
|
|
swr1: rx_swr_master {
|
|
compatible = "qcom,swr-mstr";
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
clock-names = "lpass_core_hw_vote",
|
|
"lpass_audio_hw_vote";
|
|
clocks = <&lpass_core_hw_vote 0>,
|
|
<&lpass_audio_hw_vote 0>;
|
|
qcom,swr_master_id = <2>;
|
|
qcom,mipi-sdw-block-packing-mode = <1>;
|
|
swrm-io-base = <0x3210000 0x0>;
|
|
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "swr_master_irq";
|
|
qcom,swr-num-ports = <12>;
|
|
qcom,swr-port-mapping = <1 HPH_L 0x1>,
|
|
<1 HPH_R 0x2>, <2 CLSH 0x3>,
|
|
<3 COMP_L 0x1>, <3 COMP_R 0x2>,
|
|
<4 LO 0x1>, <5 DSD_L 0x1>,
|
|
<5 DSD_R 0x2>, <6 PCM_OUT1 0x01>,
|
|
<7 GPPO 0x03>, <8 HAPT 0x03>,
|
|
<9 HIFI 0x03>, <10 HPTH 0x03>,
|
|
<11 CMPT 0x03>, <12 IPCM 0x03>;
|
|
qcom,swr-num-dev = <2>;
|
|
qcom,swr-clock-stop-mode0 = <1>;
|
|
swr_haptics: swr_haptics@f0170220 {
|
|
compatible = "qcom,pm8550b-swr-haptics";
|
|
reg = <0x02 0xf0170220>;
|
|
qcom,rx_swr_ch_map = <0 0x01 0x01 0 PCM_OUT1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
wcd937x_rx_slave: wcd937x-rx-slave {
|
|
compatible = "qcom,wcd937x-slave";
|
|
reg = <0x0A 0x01170224>;
|
|
};
|
|
|
|
wcd939x_rx_slave: wcd939x-rx-slave {
|
|
status = "disabled";
|
|
compatible = "qcom,wcd939x-slave";
|
|
reg = <0x0E 0x01170224>;
|
|
};
|
|
};
|
|
};
|
|
|
|
wsa_macro: wsa-macro@3240000 {
|
|
compatible = "qcom,lpass-cdc-wsa-macro";
|
|
reg = <0x3240000 0x0>;
|
|
qcom,wsa-swr-gpios = <&wsa_swr_gpios>;
|
|
qcom,wsa-bat-cfgs= <1>, <1>;
|
|
qcom,wsa-rloads= <2>, <2>;
|
|
qcom,wsa-system-gains= <0 9>, <0 9>;
|
|
qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;
|
|
qcom,default-clk-id = <WSA_TX_CORE_CLK>;
|
|
qcom,thermal-max-state = <11>;
|
|
qcom,noise-gate-mode = <2>;
|
|
#cooling-cells = <2>;
|
|
swr0: wsa_swr_master {
|
|
compatible = "qcom,swr-mstr";
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
clock-names = "lpass_core_hw_vote",
|
|
"lpass_audio_hw_vote";
|
|
clocks = <&lpass_core_hw_vote 0>,
|
|
<&lpass_audio_hw_vote 0>;
|
|
qcom,swr_master_id = <1>;
|
|
qcom,mipi-sdw-block-packing-mode = <0>;
|
|
swrm-io-base = <0x3250000 0x0>;
|
|
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "swr_master_irq";
|
|
qcom,swr-num-ports = <13>;
|
|
qcom,swr-clock-stop-mode0 = <1>;
|
|
qcom,swr-port-mapping = <1 SPKR_L 0x1>,
|
|
<2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>,
|
|
<4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>,
|
|
<6 SPKR_R_BOOST 0x3>, <7 PBR 0x3>,
|
|
<8 SPKR_HAPT 0x3>, <9 OCPM 0x3>,
|
|
<10 SPKR_L_VI 0x3>, <11 SPKR_R_VI 0x3>,
|
|
<12 SPKR_IPCM 0x3>, <13 CPS 0x3>;
|
|
qcom,swr-num-dev = <2>;
|
|
qcom,dynamic-port-map-supported = <0>;
|
|
wsa884x_0220: wsa884x@02170220 {
|
|
status = "disabled";
|
|
compatible = "qcom,wsa884x";
|
|
reg = <0x4 0x2170220>;
|
|
qcom,spkr-sd-n-node = <&wsa_spkr_en00>;
|
|
qcom,lpass-cdc-handle = <&lpass_cdc>;
|
|
qcom,wsa-macro-handle = <&wsa_macro>;
|
|
qcom,swr-wsa-port-params =
|
|
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
|
|
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
|
|
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
|
|
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>;
|
|
cdc-vdd-1p8-supply = <&L7B>;
|
|
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
|
|
qcom,cdc-vdd-1p8-current = <20000>;
|
|
qcom,cdc-vdd-1p8-lpm-supported = <1>;
|
|
qcom,cdc-static-supplies = "cdc-vdd-1p8";
|
|
sound-name-prefix = "SpkrLeft";
|
|
};
|
|
|
|
wsa884x_0221: wsa884x@02170221 {
|
|
status = "disabled";
|
|
compatible = "qcom,wsa884x";
|
|
reg = <0x4 0x2170221>;
|
|
qcom,spkr-sd-n-node = <&wsa_spkr_en01>;
|
|
qcom,lpass-cdc-handle = <&lpass_cdc>;
|
|
qcom,wsa-macro-handle = <&wsa_macro>;
|
|
qcom,swr-wsa-port-params =
|
|
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
|
|
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
|
|
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
|
|
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>;
|
|
cdc-vdd-1p8-supply = <&L7B>;
|
|
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
|
|
qcom,cdc-vdd-1p8-current = <20000>;
|
|
qcom,cdc-vdd-1p8-lpm-supported = <1>;
|
|
qcom,cdc-static-supplies = "cdc-vdd-1p8";
|
|
sound-name-prefix = "SpkrRight";
|
|
};
|
|
|
|
wsa883x_0221: wsa883x@02170221 {
|
|
compatible = "qcom,wsa883x";
|
|
reg = <0x2 0x2170221>;
|
|
qcom,spkr-sd-n-node = <&wsa_spkr_en00>;
|
|
qcom,lpass-cdc-handle = <&lpass_cdc>;
|
|
|
|
cdc-vdd-1p8-supply = <&L7B>;
|
|
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
|
|
qcom,cdc-vdd-1p8-current = <20000>;
|
|
qcom,cdc-static-supplies = "cdc-vdd-1p8";
|
|
sound-name-prefix = "SpkrLeft";
|
|
};
|
|
|
|
wsa883x_0222: wsa883x@02170222 {
|
|
compatible = "qcom,wsa883x";
|
|
reg = <0x2 0x2170222>;
|
|
qcom,spkr-sd-n-node = <&wsa_spkr_en01>;
|
|
qcom,lpass-cdc-handle = <&lpass_cdc>;
|
|
|
|
cdc-vdd-1p8-supply = <&L7B>;
|
|
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
|
|
qcom,cdc-vdd-1p8-current = <20000>;
|
|
qcom,cdc-static-supplies = "cdc-vdd-1p8";
|
|
sound-name-prefix = "SpkrRight";
|
|
};
|
|
};
|
|
};
|
|
|
|
wsa2_macro: wsa2-macro@31B0000 {
|
|
compatible = "qcom,lpass-cdc-wsa2-macro";
|
|
reg = <0x031B0000 0x0>;
|
|
qcom,wsa2-swr-gpios = <&wsa2_swr_gpios>;
|
|
qcom,wsa-bat-cfgs= <1>, <1>;
|
|
qcom,wsa-rloads= <2>, <2>;
|
|
qcom,wsa-system-gains= <0 9>, <0 9>;
|
|
qcom,wsa2-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;
|
|
qcom,default-clk-id = <WSA2_TX_CORE_CLK>;
|
|
qcom,thermal-max-state = <11>;
|
|
qcom,noise-gate-mode = <2>;
|
|
#cooling-cells = <2>;
|
|
status = "disabled";
|
|
swr3: wsa2_swr_master {
|
|
compatible = "qcom,swr-mstr";
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
clock-names = "lpass_core_hw_vote",
|
|
"lpass_audio_hw_vote";
|
|
clocks = <&lpass_core_hw_vote 0>,
|
|
<&lpass_audio_hw_vote 0>;
|
|
qcom,swr_master_id = <4>;
|
|
qcom,mipi-sdw-block-packing-mode = <0>;
|
|
swrm-io-base = <0x31F0000 0x0>;
|
|
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "swr_master_irq";
|
|
qcom,swr-num-ports = <13>;
|
|
qcom,swr-clock-stop-mode0 = <1>;
|
|
qcom,swr-port-mapping = <1 SPKR_L 0x1>,
|
|
<2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>,
|
|
<4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>,
|
|
<6 SPKR_R_BOOST 0x3>, <7 PBR 0x3>,
|
|
<8 SPKR_HAPT 0x3>, <9 OCPM 0x3>,
|
|
<10 SPKR_L_VI 0x3>, <11 SPKR_R_VI 0x3>,
|
|
<12 SPKR_IPCM 0x3>, <13 CPS 0x3>;
|
|
qcom,swr-num-dev = <2>;
|
|
qcom,dynamic-port-map-supported = <0>;
|
|
wsa884x_2_0220: wsa884x@02170220 {
|
|
compatible = "qcom,wsa884x_2";
|
|
reg = <0x4 0x2170220>;
|
|
qcom,spkr-sd-n-node = <&wsa_spkr_en00>;
|
|
qcom,lpass-cdc-handle = <&lpass_cdc>;
|
|
qcom,wsa-macro-handle = <&wsa2_macro>;
|
|
qcom,swr-wsa-port-params =
|
|
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
|
|
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
|
|
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>,
|
|
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL3 LANE0>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL0 LANE0>, <OFFSET1_VAL6 LANE0>, <OFFSET1_VAL0 LANE0>;
|
|
cdc-vdd-1p8-supply = <&L7B>;
|
|
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
|
|
qcom,cdc-vdd-1p8-current = <30000>;
|
|
qcom,cdc-vdd-1p8-lpm-supported = <1>;
|
|
qcom,cdc-static-supplies = "cdc-vdd-1p8";
|
|
sound-name-prefix = "Spkr2Left";
|
|
};
|
|
|
|
wsa884x_2_0221: wsa884x@02170221 {
|
|
compatible = "qcom,wsa884x_2";
|
|
reg = <0x4 0x2170221>;
|
|
qcom,spkr-sd-n-node = <&wsa_spkr_en01>;
|
|
qcom,lpass-cdc-handle = <&lpass_cdc>;
|
|
qcom,wsa-macro-handle = <&wsa2_macro>;
|
|
qcom,swr-wsa-port-params =
|
|
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
|
|
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
|
|
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>,
|
|
<OFFSET1_VAL2 LANE0>, <OFFSET1_VAL4 LANE0>, <OFFSET1_VAL21 LANE0>, <OFFSET1_VAL9 LANE0>, <OFFSET1_VAL13 LANE0>, <OFFSET1_VAL25 LANE0>;
|
|
cdc-vdd-1p8-supply = <&L7B>;
|
|
qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
|
|
qcom,cdc-vdd-1p8-current = <30000>;
|
|
qcom,cdc-vdd-1p8-lpm-supported = <1>;
|
|
qcom,cdc-static-supplies = "cdc-vdd-1p8";
|
|
sound-name-prefix = "Spkr2Right";
|
|
};
|
|
};
|
|
};
|
|
|
|
wcd937x_codec: wcd937x-codec {
|
|
compatible = "qcom,wcd937x-codec";
|
|
qcom,split-codec = <1>;
|
|
qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
|
|
<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
|
|
<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
|
|
<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
|
|
<4 DSD_R 0x2 0 DSD_R>;
|
|
qcom,tx_swr_ch_map = <0 ADC1 0x1 4800000 SWRM_TX1_CH1>,
|
|
<1 ADC2 0x1 4800000 SWRM_TX2_CH1>,
|
|
<1 ADC3 0x2 4800000 SWRM_TX2_CH2>,
|
|
<2 DMIC0 0x1 0 SWRM_TX1_CH4>,
|
|
<2 DMIC1 0x2 0 SWRM_TX2_CH1>,
|
|
<2 MBHC 0x4 4800000 SWRM_TX2_CH2>,
|
|
<3 DMIC2 0x1 0 SWRM_TX2_CH3>,
|
|
<3 DMIC3 0x2 0 SWRM_TX2_CH4>,
|
|
<3 DMIC4 0x4 0 SWRM_TX3_CH1>,
|
|
<3 DMIC5 0x8 0 SWRM_TX3_CH2>;
|
|
|
|
qcom,swr-tx-port-params =
|
|
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,
|
|
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,
|
|
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
|
|
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>;
|
|
|
|
qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>;
|
|
qcom,rx-slave = <&wcd937x_rx_slave>;
|
|
qcom,tx-slave = <&wcd937x_tx_slave>;
|
|
|
|
cdc-vdd-rxtx-supply = <&L7B>;
|
|
qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;
|
|
qcom,cdc-vdd-rxtx-current = <13890>;
|
|
|
|
cdc-vddpx-supply = <&L7B>;
|
|
qcom,cdc-vddpx-voltage = <1800000 1800000>;
|
|
qcom,cdc-vddpx-current = <13890>;
|
|
|
|
cdc-vdd-buck-supply = <&L7B>;
|
|
qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
|
|
qcom,cdc-vdd-buck-current = <361110>;
|
|
|
|
cdc-vdd-mic-bias-supply = <&BOB>;
|
|
qcom,cdc-vdd-mic-bias-voltage = <3328000 3328000>;
|
|
qcom,cdc-vdd-mic-bias-current = <6760>;
|
|
|
|
qcom,cdc-micbias1-mv = <1800>;
|
|
qcom,cdc-micbias2-mv = <1800>;
|
|
qcom,cdc-micbias3-mv = <1800>;
|
|
|
|
qcom,cdc-static-supplies = "cdc-vdd-rxtx",
|
|
"cdc-vddpx";
|
|
qcom,cdc-on-demand-supplies = "cdc-vdd-buck";
|
|
};
|
|
|
|
wcd939x_codec: wcd939x-codec {
|
|
status = "disabled";
|
|
compatible = "qcom,wcd939x-codec";
|
|
qcom,split-codec = <1>;
|
|
qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
|
|
<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
|
|
<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
|
|
<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
|
|
<4 DSD_R 0x2 0 DSD_R>;
|
|
|
|
qcom,tx_swr_ch_map = <0 ADC1 0x1 0 SWRM_TX1_CH1>,
|
|
<0 ADC2 0x2 0 SWRM_TX1_CH2>,
|
|
<1 ADC3 0x1 0 SWRM_TX1_CH3>,
|
|
<1 ADC4 0x2 0 SWRM_TX1_CH4>,
|
|
<2 DMIC0 0x1 0 SWRM_TX2_CH1>,
|
|
<2 DMIC1 0x2 0 SWRM_TX2_CH2>,
|
|
<2 MBHC 0x4 0 SWRM_TX2_CH3>,
|
|
<2 DMIC2 0x4 0 SWRM_TX2_CH3>,
|
|
<2 DMIC3 0x8 0 SWRM_TX2_CH4>,
|
|
<3 DMIC4 0x1 0 SWRM_TX3_CH1>,
|
|
<3 DMIC5 0x2 0 SWRM_TX3_CH2>,
|
|
<3 DMIC6 0x4 0 SWRM_TX3_CH3>,
|
|
<3 DMIC7 0x8 0 SWRM_TX3_CH4>;
|
|
|
|
qcom,swr-tx-port-params =
|
|
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL0 LANE2>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,
|
|
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,
|
|
<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
|
|
<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>;
|
|
|
|
qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>;
|
|
qcom,rx-slave = <&wcd939x_rx_slave>;
|
|
qcom,tx-slave = <&wcd939x_tx_slave>;
|
|
|
|
cdc-vdd-rx-supply = <&L7B>;
|
|
qcom,cdc-vdd-rx-voltage = <1800000 1800000>;
|
|
qcom,cdc-vdd-rx-current = <45000>;
|
|
qcom,cdc-vdd-rx-lpm-supported = <1>;
|
|
|
|
cdc-vdd-tx-supply = <&L7B>;
|
|
qcom,cdc-vdd-tx-voltage = <1800000 1800000>;
|
|
qcom,cdc-vdd-tx-current = <45000>;
|
|
qcom,cdc-vdd-tx-lpm-supported = <1>;
|
|
|
|
cdc-vdd-buck-supply = <&L7B>;
|
|
qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
|
|
qcom,cdc-vdd-buck-current = <650000>;
|
|
qcom,cdc-vdd-buck-lpm-supported = <1>;
|
|
|
|
cdc-vdd-mic-bias-supply = <&BOB>;
|
|
qcom,cdc-vdd-mic-bias-voltage = <3328000 3328000>;
|
|
qcom,cdc-vdd-mic-bias-current = <30000>;
|
|
|
|
cdc-vdd-px-supply = <&L7B>;
|
|
qcom,cdc-vdd-px-voltage = <1800000 1800000>;
|
|
qcom,cdc-vdd-px-current = <15000>;
|
|
qcom,cdc-vdd-px-lpm-supported = <1>;
|
|
|
|
qcom,cdc-micbias1-mv = <1800>;
|
|
qcom,cdc-micbias2-mv = <1800>;
|
|
qcom,cdc-micbias3-mv = <1800>;
|
|
qcom,cdc-micbias4-mv = <1800>;
|
|
|
|
qcom,cdc-static-supplies = "cdc-vdd-rx",
|
|
"cdc-vdd-tx",
|
|
"cdc-vdd-mic-bias",
|
|
"cdc-vdd-px";
|
|
qcom,cdc-on-demand-supplies = "cdc-vdd-buck";
|
|
};
|
|
|
|
};
|
|
|
|
&swr_haptics {
|
|
status = "disabled";
|
|
};
|
|
|
|
&spf_core_platform {
|
|
kalama_snd: sound {
|
|
qcom,model = "crow-idp-wsa883x-snd-card";
|
|
qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>;
|
|
qcom,mi2s-tdm-is-hw-vote-needed = <1>, <0>, <1>, <0>, <0>, <0>;
|
|
qcom,wcn-bt = <0>;
|
|
qcom,ext-disp-audio-rx = <0>;
|
|
qcom,tdm-max-slots = <8>;
|
|
qcom,tdm-clk-attribute = <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>;
|
|
qcom,mi2s-clk-attribute = <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>;
|
|
swr-haptics-unsupported;
|
|
qcom,audio-routing =
|
|
"AMIC1", "Analog Mic1",
|
|
"AMIC1", "MIC BIAS1",
|
|
"AMIC2", "Analog Mic2",
|
|
"AMIC2", "MIC BIAS2",
|
|
"AMIC3", "Analog Mic3",
|
|
"AMIC3", "MIC BIAS3",
|
|
"AMIC4", "Analog Mic4",
|
|
"AMIC4", "MIC BIAS3",
|
|
"TX DMIC0", "Digital Mic0",
|
|
"TX DMIC0", "MIC BIAS3",
|
|
"TX DMIC1", "Digital Mic1",
|
|
"TX DMIC1", "MIC BIAS3",
|
|
"TX DMIC2", "Digital Mic2",
|
|
"TX DMIC2", "MIC BIAS1",
|
|
"TX DMIC3", "Digital Mic3",
|
|
"TX DMIC3", "MIC BIAS1",
|
|
"IN1_HPHL", "HPHL_OUT",
|
|
"IN2_HPHR", "HPHR_OUT",
|
|
"IN3_AUX", "AUX_OUT",
|
|
"WSA SRC0_INP", "SRC0",
|
|
"WSA_TX DEC0_INP", "TX DEC0 MUX",
|
|
"WSA_TX DEC1_INP", "TX DEC1 MUX",
|
|
"RX_TX DEC0_INP", "TX DEC0 MUX",
|
|
"RX_TX DEC1_INP", "TX DEC1 MUX",
|
|
"RX_TX DEC2_INP", "TX DEC2 MUX",
|
|
"RX_TX DEC3_INP", "TX DEC3 MUX",
|
|
"SpkrLeft IN", "WSA_SPK1 OUT",
|
|
"SpkrRight IN", "WSA_SPK2 OUT",
|
|
"TX SWR_INPUT", "WCD_TX_OUTPUT",
|
|
"VA SWR_INPUT", "VA_SWR_CLK",
|
|
"VA SWR_INPUT", "WCD_TX_OUTPUT",
|
|
"VA_AIF1 CAP", "VA_SWR_CLK",
|
|
"VA_AIF2 CAP", "VA_SWR_CLK",
|
|
"VA_AIF3 CAP", "VA_SWR_CLK",
|
|
"VA DMIC0", "Digital Mic0",
|
|
"VA DMIC1", "Digital Mic1",
|
|
"VA DMIC2", "Digital Mic2",
|
|
"VA DMIC3", "Digital Mic3",
|
|
"VA DMIC0", "VA MIC BIAS3",
|
|
"VA DMIC1", "VA MIC BIAS3",
|
|
"VA DMIC2", "VA MIC BIAS1",
|
|
"VA DMIC3", "VA MIC BIAS1";
|
|
qcom,msm-mbhc-usbc-audio-supported = <0>;
|
|
qcom,msm-mbhc-hphl-swh = <1>;
|
|
qcom,msm-mbhc-gnd-swh = <1>;
|
|
|
|
qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
|
|
qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;
|
|
qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>;
|
|
asoc-codec = <&stub_codec>, <&lpass_cdc>,
|
|
<&wcd937x_codec>, <&wsa883x_0221>,
|
|
<&wsa883x_0222>;
|
|
asoc-codec-names = "msm-stub-codec.1", "lpass-cdc",
|
|
"wcd937x_codec", "wsa-codec1",
|
|
"wsa-codec2";
|
|
qcom,wsa-max-devs = <2>;
|
|
qcom,msm_audio_ssr_devs = <&audio_gpr>, <&lpi_tlmm>,
|
|
<&lpass_cdc>;
|
|
qcom,upd_backends_used = "wcd";
|
|
qcom,upd_lpass_reg_addr = <0x00000418 0x33B0300>;
|
|
qcom,upd_ear_pa_reg_addr = <0x300A>;
|
|
};
|
|
|
|
fm_i2s0_gpios: fm_i2s0_pinctrl {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active", "aud_sleep";
|
|
pinctrl-0 = <&i2s0_sck_active &i2s0_ws_active
|
|
&i2s0_sd0_active>;
|
|
pinctrl-1 = <&i2s0_sck_sleep &i2s0_ws_sleep
|
|
&i2s0_sd0_sleep>;
|
|
#gpio-cells = <0>;
|
|
};
|
|
|
|
wsa_swr_gpios: wsa_swr_clk_data_pinctrl {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active", "aud_sleep";
|
|
pinctrl-0 = <&wsa_swr_clk_active &wsa_swr_data_active>;
|
|
pinctrl-1 = <&wsa_swr_clk_sleep &wsa_swr_data_sleep>;
|
|
qcom,lpi-gpios;
|
|
#gpio-cells = <0>;
|
|
};
|
|
|
|
wsa2_swr_gpios: wsa2_swr_clk_data_pinctrl {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active", "aud_sleep";
|
|
pinctrl-0 = <&wsa2_swr_clk_active &wsa2_swr_data_active>;
|
|
pinctrl-1 = <&wsa2_swr_clk_sleep &wsa2_swr_data_sleep>;
|
|
qcom,lpi-gpios;
|
|
#gpio-cells = <0>;
|
|
};
|
|
|
|
rx_swr_gpios: rx_swr_clk_data_pinctrl {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active", "aud_sleep";
|
|
pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active
|
|
&rx_swr_data1_active>;
|
|
pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep
|
|
&rx_swr_data1_sleep>;
|
|
qcom,lpi-gpios;
|
|
#gpio-cells = <0>;
|
|
};
|
|
|
|
va_swr_gpios: tx_swr_clk_data_pinctrl {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active", "aud_sleep";
|
|
pinctrl-0 = <&tx_swr_clk_active &tx_swr_data0_active
|
|
&tx_swr_data1_active &tx_swr_data2_active>;
|
|
pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data0_sleep
|
|
&tx_swr_data1_sleep &tx_swr_data2_sleep>;
|
|
qcom,lpi-gpios;
|
|
#gpio-cells = <0>;
|
|
};
|
|
|
|
cdc_dmic01_gpios: cdc_dmic01_pinctrl {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active", "aud_sleep";
|
|
pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>;
|
|
pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>;
|
|
qcom,lpi-gpios;
|
|
#gpio-cells = <0>;
|
|
};
|
|
|
|
cdc_dmic23_gpios: cdc_dmic23_pinctrl {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active", "aud_sleep";
|
|
pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>;
|
|
pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>;
|
|
qcom,lpi-gpios;
|
|
#gpio-cells = <0>;
|
|
};
|
|
|
|
cdc_dmic45_gpios: cdc_dmic45_pinctrl {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active", "aud_sleep";
|
|
pinctrl-0 = <&cdc_dmic45_clk_active &cdc_dmic45_data_active>;
|
|
pinctrl-1 = <&cdc_dmic45_clk_sleep &cdc_dmic45_data_sleep>;
|
|
qcom,lpi-gpios;
|
|
#gpio-cells = <0>;
|
|
};
|
|
|
|
cdc_dmic67_gpios: cdc_dmic67_pinctrl {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active", "aud_sleep";
|
|
pinctrl-0 = <&cdc_dmic67_clk_active &cdc_dmic67_data_active>;
|
|
pinctrl-1 = <&cdc_dmic67_clk_sleep &cdc_dmic67_data_sleep>;
|
|
qcom,lpi-gpios;
|
|
#gpio-cells = <0>;
|
|
};
|
|
};
|
|
|
|
&soc {
|
|
wsa_spkr_en00: wsa_spkr_en1_pinctrl {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active", "aud_sleep";
|
|
pinctrl-0 = <&spkr_00_sd_n_active>;
|
|
pinctrl-1 = <&spkr_00_sd_n_sleep>;
|
|
qcom,lpi-gpios;
|
|
};
|
|
|
|
wsa_spkr_en01: wsa_spkr_en2_pinctrl {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active", "aud_sleep";
|
|
pinctrl-0 = <&spkr_01_sd_n_active>;
|
|
pinctrl-1 = <&spkr_01_sd_n_sleep>;
|
|
qcom,lpi-gpios;
|
|
};
|
|
|
|
wcd_rst_gpio: msm_cdc_pinctrl@32 {
|
|
compatible = "qcom,msm-cdc-pinctrl";
|
|
pinctrl-names = "aud_active", "aud_sleep";
|
|
pinctrl-0 = <&wcd_reset_active>;
|
|
pinctrl-1 = <&wcd_reset_sleep>;
|
|
};
|
|
|
|
|
|
clock_audio_va_1: va_core_clk {
|
|
compatible = "qcom,audio-ref-clk";
|
|
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK>;
|
|
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
|
qcom,codec-lpass-clk-id = <0x307>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
clock_audio_wsa_1: wsa_core_clk {
|
|
compatible = "qcom,audio-ref-clk";
|
|
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_2>;
|
|
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
|
qcom,codec-lpass-clk-id = <0x309>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
clock_audio_wsa_2: wsa2_core_clk {
|
|
compatible = "qcom,audio-ref-clk";
|
|
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_9>;
|
|
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
|
qcom,codec-lpass-clk-id = <0x310>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
clock_audio_rx_1: rx_core_clk {
|
|
compatible = "qcom,audio-ref-clk";
|
|
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_4>;
|
|
qcom,codec-lpass-ext-clk-freq = <22579200>;
|
|
qcom,codec-lpass-clk-id = <0x30E>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
clock_audio_rx_tx: rx_core_tx_clk {
|
|
compatible = "qcom,audio-ref-clk";
|
|
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_10>;
|
|
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
|
qcom,codec-lpass-clk-id = <0x312>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
clock_audio_tx_1: tx_core_clk {
|
|
compatible = "qcom,audio-ref-clk";
|
|
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_6>;
|
|
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
|
qcom,codec-lpass-clk-id = <0x30C>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
clock_audio_wsa_tx: wsa_core_tx_clk {
|
|
compatible = "qcom,audio-ref-clk";
|
|
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_11>;
|
|
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
|
qcom,codec-lpass-clk-id = <0x314>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
clock_audio_wsa2_tx: wsa2_core_tx_clk {
|
|
compatible = "qcom,audio-ref-clk";
|
|
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_12>;
|
|
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
|
qcom,codec-lpass-clk-id = <0x316>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
clock_audio_rx_mclk2_2x_clk: rx_mclk2_2x_clk {
|
|
compatible = "qcom,audio-ref-clk";
|
|
qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_13>;
|
|
qcom,codec-lpass-ext-clk-freq = <19200000>;
|
|
qcom,codec-lpass-clk-id = <0x318>;
|
|
#clock-cells = <1>;
|
|
};
|
|
};
|
|
|
|
&adsp_loader {
|
|
nvmem-cells = <&adsp_variant>;
|
|
nvmem-cell-names = "adsp_variant";
|
|
adsp-fw-names = "adsp2.mdt";
|
|
adsp-fw-bit-values = <0x7>;
|
|
};
|