kernel_oneplus_sm8550-devicetrees/qcom/sdxbaagha.dtsi

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	model = "Qualcomm Technologies, Inc. SDXBAAGHA";
	compatible = "qcom,sdxbaagha";
	qcom,msm-id = <570 0x10000>, <571 0x10000>;
	interrupt-parent = <&intc>;

	aliases { };

	chosen { };

	memory { device_type = "memory"; reg = <0 0>; };

	reserved_memory: reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		mpss_mem: mpss_region@82400000 {
			no-map;
			reg = <0x82400000 0x4600000>;
		};

		quickboot_mem: quickboot_region@86a00000 {
			no-map;
			reg = <0x86a00000 0x100000>;
		};

		aop_image_mem: aop_image_region@86b00000 {
			no-map;
			reg = <0x86b00000 0x20000>;
		};

		aop_cmd_db_mem: aop_cmd_db_region@86b20000 {
			compatible = "qcom,cmd-db";
			no-map;
			reg = <0x86b20000 0x20000>;
		};

		aop_config_mem: aop_config_region@86b40000 {
			no-map;
			reg = <0x86b40000 0x40000>;
		};

		smem_mem: smem_region@86b80000 {
			no-map;
			reg = <0x86b80000 0xc0000>;
		};

		tme_crashdump_mem: tme_crashdump_region@86c40000 {
			no-map;
			reg = <0x86c40000 0x40000>;
		};

		tme_log_mem: tme_log_region@86c80000 {
			no-map;
			reg = <0x86c80000 0x4000>;
		};

		access_control_db_mem: access_control_db_region@86c84000 {
			no-map;
			reg = <0x86c84000 0x20000>;
		};

		secdata_mem: secdata_region@86ca4000 {
			no-map;
			reg = <0x86ca4000 0x1000>;
		};

		xbl_ramdump_mem: xbl_ramdump_region@86d00000 {
			no-map;
			reg = <0x86d00000 0x100000>;
		};

		qtee_tz_mem: qtee_tz_region@86e00000 {
			no-map;
			reg = <0x86e00000 0x200000>;
		};

		trusted_apps_mem: trusted_apps_region@87000000 {
			no-map;
			reg = <0x87000000 0x400000>;
		};

		/* global autoconfigured region for contiguous allocations */
		system_cma: linux,cma {
			compatible = "shared-dma-pool";
			alloc-ranges = <0x00000000 0xffffffff>;
			reusable;
			alignment = <0x400000>;
			size = <0xc00000>;
			linux,cma-default;
		};

	};

	cpus {
		#size-cells = <0>;
		#address-cells = <1>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
		};
	};

	soc: soc { };
};

#include "sdxbaagha-stub-regulator.dtsi"

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	compatible = "simple-bus";

	intc: interrupt-controller@17000000 {
		compatible = "qcom,msm-qgic2";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x17000000 0x1000>,
		      <0x17002000 0x1000>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 13 0xf08>,
			<1 12 0xf08>,
			<1 10 0xf08>,
			<1 11 0xf08>;
		clock-frequency = <19200000>;
	};

	timer@17020000 {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "arm,armv7-timer-mem";
		reg = <0x17020000 0x1000>;
		clock-frequency = <19200000>;

		frame@17021000 {
			frame-number = <0>;
			interrupts = <0 7 0x4>,
				     <0 6 0x4>;
			reg = <0x17021000 0x1000>,
			      <0x17022000 0x1000>;
		};

		frame@17023000 {
			frame-number = <1>;
			interrupts = <0 8 0x4>;
			reg = <0x17023000 0x1000>;
			status = "disabled";
		};

		frame@17024000 {
			frame-number = <2>;
			interrupts = <0 9 0x4>;
			reg = <0x17024000 0x1000>;
			status = "disabled";
		};

		frame@17025000 {
			frame-number = <3>;
			interrupts = <0 10 0x4>;
			reg = <0x17025000 0x1000>;
			status = "disabled";
		};

		frame@17026000 {
			frame-number = <4>;
			interrupts = <0 11 0x4>;
			reg = <0x17026000 0x1000>;
			status = "disabled";
		};

		frame@17027000 {
			frame-number = <5>;
			interrupts = <0 12 0x4>;
			reg = <0x17027000 0x1000>;
			status = "disabled";
		};

		frame@17028000 {
			frame-number = <6>;
			interrupts = <0 13 0x4>;
			reg = <0x17028000 0x1000>;
			status = "disabled";
		};

		frame@17029000 {
			frame-number = <7>;
			interrupts = <0 14 0x4>;
			reg = <0x17029000 0x1000>;
			status = "disabled";
		};
	};
};

#include "sdxbaagha-pinctrl.dtsi"
#include "sdxbaagha-dma-heaps.dtsi"