mirror of
https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-02-01 09:49:52 +00:00
4eba3d089f
Include IPCC test node for sdxpinn, so IPCC kernel-tests can run on sdxpinn. Change-Id: I963f1bdc00862d77d7816f5a52c51698674ff0d3
379 lines
8.2 KiB
Plaintext
379 lines
8.2 KiB
Plaintext
#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-sdxpinn.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/soc/qcom,ipcc.h>
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/ {
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model = "Qualcomm Technologies, Inc. SDXPINN";
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compatible = "qcom,sdxpinn";
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qcom,msm-id = <556 0x10000>, <580 0x10000>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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reserved_memory: reserved-memory { };
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chosen: chosen { };
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aliases { };
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x0>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x90f00000>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "arm,arch-cache";
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cache-level = <3>;
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x100>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x90f00000>;
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L2_1: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x200>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x90f00000>;
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L2_2: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x300>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x90f00000>;
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L2_3: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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};
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};
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soc: soc { };
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};
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#include "sdxpinn-reserved-memory.dtsi"
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&reserved_memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* global autoconfigured region for contiguous allocations */
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system_cma: linux,cma {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x2000000>;
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linux,cma-default;
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};
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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intc: interrupt-controller@17200000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x20000>;
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reg = <0x17200000 0x10000>,/* GICD */
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<0x17260000 0x80000>;/* GICR * 4 */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <19200000>;
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};
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memtimer: timer@17420000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x17420000 0x1000>;
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clock-frequency = <19200000>;
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frame@17421000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17421000 0x1000>,
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<0x17422000 0x1000>;
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};
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frame@17423000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17423000 0x1000>;
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status = "disabled";
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};
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frame@17425000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17425000 0x1000>;
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status = "disabled";
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};
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frame@17427000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17427000 0x1000>;
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status = "disabled";
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};
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frame@17429000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17429000 0x1000>;
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status = "disabled";
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};
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frame@1742b000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x1742b000 0x1000>;
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status = "disabled";
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};
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frame@1742d000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x1742d000 0x1000>;
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status = "disabled";
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};
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};
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clocks {
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xo_board: xo_board {
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compatible = "fixed-clock";
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clock-frequency = <19200000>;
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clock-output-names = "xo_board";
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#clock-cells = <0>;
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};
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sleep_clk: sleep_clk {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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clock-output-names = "sleep_clk";
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#clock-cells = <0>;
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};
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pcie20_phy_aux_clk: pcie20_phy_aux_clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "pcie20_phy_aux_clk";
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#clock-cells = <0>;
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};
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pcie_1_pipe_clk: pcie_1_pipe_clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "pcie_1_pipe_clk";
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#clock-cells = <0>;
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};
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pcie_2_pipe_clk: pcie_2_pipe_clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "pcie_2_pipe_clk";
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#clock-cells = <0>;
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};
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pcie_pipe_clk: pcie_pipe_clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "pcie_pipe_clk";
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#clock-cells = <0>;
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};
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usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
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#clock-cells = <0>;
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};
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};
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bi_tcxo: bi_tcxo {
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compatible = "fixed-factor-clock";
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clocks = <&xo_board>;
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clock-mult = <1>;
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clock-div = <1>;
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#clock-cells = <0>;
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clock-output-names = "bi_tcxo";
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};
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bi_tcxo_ao: bi_tcxo_ao {
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compatible = "fixed-factor-clock";
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clocks = <&xo_board>;
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clock-mult = <1>;
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clock-div = <1>;
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#clock-cells = <0>;
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clock-output-names = "bi_tcxo_ao";
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};
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rpmhcc: clock-controller {
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compatible = "fixed-clock";
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clock-output-names = "rpmh_clocks";
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clock-frequency = <19200000>;
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#clock-cells = <1>;
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};
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gcc: clock-controller@80000 {
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compatible = "qcom,dummycc";
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clock-output-names = "gcc_clocks";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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/* GCC GDSCs */
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gcc_emac0_gdsc: qcom,gdsc@f1004 {
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compatible = "regulator-fixed";
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regulator-name = "gcc_emac0_gdsc";
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qcom,support-hw-trigger;
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};
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gcc_emac1_gdsc: qcom,gdsc@f2004 {
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compatible = "regulator-fixed";
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regulator-name = "gcc_emac1_gdsc";
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qcom,support-hw-trigger;
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};
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gcc_pcie_1_gdsc: qcom,gdsc@e7004 {
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compatible = "regulator-fixed";
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regulator-name = "gcc_pcie_1_gdsc";
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qcom,support-hw-trigger;
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};
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gcc_pcie_1_phy_gdsc: qcom,gdsc@d6004 {
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compatible = "regulator-fixed";
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regulator-name = "gcc_pcie_1_phy_gdsc";
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qcom,support-hw-trigger;
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};
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gcc_pcie_2_gdsc: qcom,gdsc@e8004 {
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compatible = "regulator-fixed";
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regulator-name = "gcc_pcie_2_gdsc";
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qcom,support-hw-trigger;
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};
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gcc_pcie_2_phy_gdsc: qcom,gdsc@ee004 {
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compatible = "regulator-fixed";
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regulator-name = "gcc_pcie_2_phy_gdsc";
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qcom,support-hw-trigger;
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};
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gcc_pcie_gdsc: qcom,gdsc@d3004 {
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compatible = "regulator-fixed";
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regulator-name = "gcc_pcie_gdsc";
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qcom,support-hw-trigger;
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};
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gcc_pcie_phy_gdsc: qcom,gdsc@d4004 {
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compatible = "regulator-fixed";
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regulator-name = "gcc_pcie_phy_gdsc";
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qcom,support-hw-trigger;
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};
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gcc_usb30_gdsc: qcom,gdsc@a7004 {
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compatible = "regulator-fixed";
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regulator-name = "gcc_usb30_gdsc";
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};
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gcc_usb3_phy_gdsc: qcom,gdsc@a8008 {
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compatible = "regulator-fixed";
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regulator-name = "gcc_usb3_phy_gdsc";
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};
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tlmm: pinctrl@f000000 {
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compatible = "qcom,sdxpinn-pinctrl";
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reg = <0x0F000000 0x400000>;
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interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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ipcc_mproc: qcom,ipcc@408000 {
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compatible = "qcom,ipcc";
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reg = <0x408000 0x1000>;
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interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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#mbox-cells = <2>;
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};
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};
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#include "ipcc-test-sdxpinn.dtsi"
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#include "sdxpinn-regulators.dtsi"
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#include "sdxpinn-pinctrl.dtsi"
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