mirror of
https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-02-01 09:49:52 +00:00
8e2b844580
On SA8195, the primary and secondary USB ports are HS capable. Add support for primary USB controller and HSPHY,secondary USB controller and HSPHY. Change-Id: Ib4a58698174d18c711968cb107b074268cb7d858
171 lines
4.6 KiB
Plaintext
171 lines
4.6 KiB
Plaintext
#include <dt-bindings/clock/qcom,gcc-sc8180x.h>
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#include <dt-bindings/phy/qcom,sm8150-qmp-usb3.h>
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&soc {
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/* Primary USB port related controller */
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usb0: ssusb@a600000 {
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compatible = "qcom,dwc-usb3-msm";
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reg = <0x0a600000 0x100000>;
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reg-names = "core_base";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
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<&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
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<&pdc 8 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
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"dm_hs_phy_irq";
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qcom,use-pdc-interrupts;
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USB3_GDSC-supply = <&usb30_prim_gdsc>;
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clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
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<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
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"utmi_clk", "sleep_clk", "xo";
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resets = <&gcc GCC_USB30_PRIM_BCR>;
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reset-names = "core_reset";
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qcom,core-clk-rate = <200000000>;
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qcom,core-clk-rate-hs = <66666667>;
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qcom,host-poweroff-in-pm-suspend;
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interconnect-names = "usb-ddr", "ddr-usb";
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interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>;
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dwc3@a600000 {
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compatible = "snps,dwc3";
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reg = <0x0a600000 0xcd00>;
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iommus = <&apps_smmu 0x140 0x0>;
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qcom,iommu-dma = "atomic";
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qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
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interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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usb-phy = <&usb2_phy0>, <&usb_nop_phy>;
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snps,disable-clk-gating;
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x0>;
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snps,is-utmi-l1-suspend;
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snps,usb2-gadget-lpm-disable;
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tx-fifo-resize;
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maximum-speed = "high-speed";
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dr_mode = "otg";
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usb-role-switch;
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};
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};
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/* Primary USB port related High Speed PHY */
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usb2_phy0: hsphy@88e2000 {
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compatible = "qcom,usb-hsphy-snps-femto";
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reg = <0x88e2000 0x110>,
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<0x007801f8 0x4>;
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reg-names = "hsusb_phy_base",
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"phy_rcal_reg";
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vdd-supply = <&L5E>;
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vdda18-supply = <&L12A>;
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vdda33-supply = <&L16E>;
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qcom,vdd-voltage-level = <0 880000 880000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "ref_clk_src";
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resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
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reset-names = "phy_reset";
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qcom,param-override-seq = <0x43 0x70>;
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qcom,rcal-mask = <0x1e00000>;
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};
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usb_nop_phy: usb_nop_phy {
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compatible = "usb-nop-xceiv";
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};
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/* Secondary USB port related controller */
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usb1: ssusb@a800000 {
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compatible = "qcom,dwc-usb3-msm";
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reg = <0x0a800000 0x100000>;
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reg-names = "core_base";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupts-extended = <&pdc 11 IRQ_TYPE_EDGE_RISING>,
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<&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
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<&pdc 10 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
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"dm_hs_phy_irq";
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qcom,use-pdc-interrupts;
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qcom,default-mode-host;
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qcom,host-poweroff-in-pm-suspend;
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USB3_GDSC-supply = <&usb30_sec_gdsc>;
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clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>,
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<&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
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<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
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<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_SEC_SLEEP_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
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"utmi_clk", "sleep_clk", "xo";
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resets = <&gcc GCC_USB30_SEC_BCR>;
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reset-names = "core_reset";
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qcom,core-clk-rate = <200000000>;
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qcom,core-clk-rate-hs = <66666667>;
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interconnect-names = "usb-ddr", "ddr-usb";
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interconnects = <&aggre1_noc MASTER_USB3_1 &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_1>;
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dwc3@a800000 {
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compatible = "snps,dwc3";
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reg = <0x0a800000 0xcd00>;
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iommus = <&apps_smmu 0x160 0x0>;
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qcom,iommu-dma = "atomic";
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qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
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interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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usb-phy = <&usb2_phy1>, <&usb_nop_phy>;
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snps,disable-clk-gating;
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x0>;
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snps,is-utmi-l1-suspend;
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snps,usb2-gadget-lpm-disable;
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tx-fifo-resize;
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maximum-speed = "high-speed";
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dr_mode = "otg";
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usb-role-switch;
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};
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};
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/* Secondary USB port related High Speed PHY */
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usb2_phy1: hsphy@88e3000 {
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compatible = "qcom,usb-hsphy-snps-femto";
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reg = <0x88e3000 0x110>,
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<0x007801f8 0x4>;
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reg-names = "hsusb_phy_base",
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"phy_rcal_reg";
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vdd-supply = <&L5E>;
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vdda18-supply = <&L12A>;
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vdda33-supply = <&L16E>;
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qcom,vdd-voltage-level = <0 880000 880000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "ref_clk_src";
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resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
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reset-names = "phy_reset";
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qcom,param-override-seq = <0x43 0x70>;
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qcom,rcal-mask = <0x1e00000>;
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};
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};
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