mirror of
https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-02-01 09:49:52 +00:00
a8a9c53ed3
Add kona-regulators.dtsi to enable regulator. Change-Id: I74e2c8c1d3018834f09afc58618916000af0e5ea
1156 lines
23 KiB
Plaintext
1156 lines
23 KiB
Plaintext
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
|
|
#include <dt-bindings/interconnect/qcom,icc.h>
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
|
|
/ {
|
|
model = "Qualcomm Technologies, Inc. kona";
|
|
compatible = "qcom,kona";
|
|
qcom,msm-id = <356 0x10000>;
|
|
interrupt-parent = <&intc>;
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
memory { device_type = "memory"; reg = <0 0 0 0>; };
|
|
|
|
chosen {
|
|
bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off";
|
|
};
|
|
|
|
reserved_memory: reserved-memory { };
|
|
|
|
aliases { };
|
|
|
|
cpus {
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
|
|
CPU0: cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "qcom,kryo";
|
|
reg = <0x0 0x0>;
|
|
enable-method = "psci";
|
|
cpu-release-addr = <0x0 0x90000000>;
|
|
next-level-cache = <&L2_0>;
|
|
qcom,freq-domain = <&cpufreq_hw 0 4>;
|
|
capacity-dmips-mhz = <1024>;
|
|
dynamic-power-coefficient = <100>;
|
|
#cooling-cells = <2>;
|
|
L2_0: l2-cache {
|
|
compatible = "arm,arch-cache";
|
|
cache-level = <2>;
|
|
next-level-cache = <&L3_0>;
|
|
|
|
L3_0: l3-cache {
|
|
compatible = "arm,arch-cache";
|
|
cache-level = <3>;
|
|
};
|
|
};
|
|
|
|
L1_I_0: l1-icache {
|
|
compatible = "arm,arch-cache";
|
|
};
|
|
|
|
L1_D_0: l1-dcache {
|
|
compatible = "arm,arch-cache";
|
|
};
|
|
};
|
|
|
|
CPU1: cpu@100 {
|
|
device_type = "cpu";
|
|
compatible = "qcom,kryo";
|
|
reg = <0x0 0x100>;
|
|
enable-method = "psci";
|
|
cpu-release-addr = <0x0 0x90000000>;
|
|
next-level-cache = <&L2_1>;
|
|
qcom,freq-domain = <&cpufreq_hw 0 4>;
|
|
capacity-dmips-mhz = <1024>;
|
|
dynamic-power-coefficient = <100>;
|
|
L2_1: l2-cache {
|
|
compatible = "arm,arch-cache";
|
|
cache-level = <2>;
|
|
next-level-cache = <&L3_0>;
|
|
};
|
|
|
|
L1_I_100: l1-icache {
|
|
compatible = "arm,arch-cache";
|
|
};
|
|
|
|
L1_D_100: l1-dcache {
|
|
compatible = "arm,arch-cache";
|
|
};
|
|
};
|
|
|
|
CPU2: cpu@200 {
|
|
device_type = "cpu";
|
|
compatible = "qcom,kryo";
|
|
reg = <0x0 0x200>;
|
|
enable-method = "psci";
|
|
cpu-release-addr = <0x0 0x90000000>;
|
|
next-level-cache = <&L2_2>;
|
|
qcom,freq-domain = <&cpufreq_hw 0 4>;
|
|
capacity-dmips-mhz = <1024>;
|
|
dynamic-power-coefficient = <100>;
|
|
L2_2: l2-cache {
|
|
compatible = "arm,arch-cache";
|
|
cache-level = <2>;
|
|
next-level-cache = <&L3_0>;
|
|
};
|
|
|
|
L1_I_200: l1-icache {
|
|
compatible = "arm,arch-cache";
|
|
};
|
|
|
|
L1_D_200: l1-dcache {
|
|
compatible = "arm,arch-cache";
|
|
};
|
|
};
|
|
|
|
CPU3: cpu@300 {
|
|
device_type = "cpu";
|
|
compatible = "qcom,kryo";
|
|
reg = <0x0 0x300>;
|
|
enable-method = "psci";
|
|
cpu-release-addr = <0x0 0x90000000>;
|
|
next-level-cache = <&L2_3>;
|
|
qcom,freq-domain = <&cpufreq_hw 0 4>;
|
|
capacity-dmips-mhz = <1024>;
|
|
dynamic-power-coefficient = <100>;
|
|
L2_3: l2-cache {
|
|
compatible = "arm,arch-cache";
|
|
cache-level = <2>;
|
|
next-level-cache = <&L3_0>;
|
|
};
|
|
|
|
L1_I_300: l1-icache {
|
|
compatible = "arm,arch-cache";
|
|
};
|
|
|
|
L1_D_300: l1-dcache {
|
|
compatible = "arm,arch-cache";
|
|
};
|
|
};
|
|
|
|
CPU4: cpu@400 {
|
|
device_type = "cpu";
|
|
compatible = "qcom,kryo";
|
|
reg = <0x0 0x400>;
|
|
enable-method = "psci";
|
|
cpu-release-addr = <0x0 0x90000000>;
|
|
next-level-cache = <&L2_4>;
|
|
qcom,freq-domain = <&cpufreq_hw 1 4>;
|
|
capacity-dmips-mhz = <1894>;
|
|
dynamic-power-coefficient = <514>;
|
|
#cooling-cells = <2>;
|
|
L2_4: l2-cache {
|
|
compatible = "arm,arch-cache";
|
|
cache-level = <2>;
|
|
next-level-cache = <&L3_0>;
|
|
};
|
|
|
|
L1_I_400: l1-icache {
|
|
compatible = "arm,arch-cache";
|
|
};
|
|
|
|
L1_D_400: l1-dcache {
|
|
compatible = "arm,arch-cache";
|
|
};
|
|
};
|
|
|
|
CPU5: cpu@500 {
|
|
device_type = "cpu";
|
|
compatible = "qcom,kryo";
|
|
reg = <0x0 0x500>;
|
|
enable-method = "psci";
|
|
cpu-release-addr = <0x0 0x90000000>;
|
|
next-level-cache = <&L2_5>;
|
|
qcom,freq-domain = <&cpufreq_hw 1 4>;
|
|
capacity-dmips-mhz = <1894>;
|
|
dynamic-power-coefficient = <514>;
|
|
L2_5: l2-cache {
|
|
compatible = "arm,arch-cache";
|
|
cache-level = <2>;
|
|
next-level-cache = <&L3_0>;
|
|
};
|
|
|
|
L1_I_500: l1-icache {
|
|
compatible = "arm,arch-cache";
|
|
};
|
|
|
|
L1_D_500: l1-dcache {
|
|
compatible = "arm,arch-cache";
|
|
};
|
|
};
|
|
|
|
CPU6: cpu@600 {
|
|
device_type = "cpu";
|
|
compatible = "qcom,kryo";
|
|
reg = <0x0 0x600>;
|
|
enable-method = "psci";
|
|
cpu-release-addr = <0x0 0x90000000>;
|
|
next-level-cache = <&L2_6>;
|
|
qcom,freq-domain = <&cpufreq_hw 1 4>;
|
|
capacity-dmips-mhz = <1894>;
|
|
dynamic-power-coefficient = <514>;
|
|
L2_6: l2-cache {
|
|
compatible = "arm,arch-cache";
|
|
cache-level = <2>;
|
|
next-level-cache = <&L3_0>;
|
|
};
|
|
|
|
L1_I_600: l1-icache {
|
|
compatible = "arm,arch-cache";
|
|
};
|
|
|
|
L1_D_600: l1-dcache {
|
|
compatible = "arm,arch-cache";
|
|
};
|
|
};
|
|
|
|
CPU7: cpu@700 {
|
|
device_type = "cpu";
|
|
compatible = "qcom,kryo";
|
|
reg = <0x0 0x700>;
|
|
enable-method = "psci";
|
|
cpu-release-addr = <0x0 0x90000000>;
|
|
next-level-cache = <&L2_7>;
|
|
qcom,freq-domain = <&cpufreq_hw 2 4>;
|
|
capacity-dmips-mhz = <1894>;
|
|
dynamic-power-coefficient = <598>;
|
|
#cooling-cells = <2>;
|
|
L2_7: l2-cache {
|
|
compatible = "arm,arch-cache";
|
|
cache-level = <2>;
|
|
next-level-cache = <&L3_0>;
|
|
};
|
|
|
|
L1_I_700: l1-icache {
|
|
compatible = "arm,arch-cache";
|
|
};
|
|
|
|
L1_D_700: l1-dcache {
|
|
compatible = "arm,arch-cache";
|
|
};
|
|
};
|
|
|
|
cpu-map {
|
|
cluster0 {
|
|
core0 {
|
|
cpu = <&CPU0>;
|
|
};
|
|
|
|
core1 {
|
|
cpu = <&CPU1>;
|
|
};
|
|
|
|
core2 {
|
|
cpu = <&CPU2>;
|
|
};
|
|
|
|
core3 {
|
|
cpu = <&CPU3>;
|
|
};
|
|
};
|
|
|
|
cluster1 {
|
|
core0 {
|
|
cpu = <&CPU4>;
|
|
};
|
|
|
|
core1 {
|
|
cpu = <&CPU5>;
|
|
};
|
|
|
|
core2 {
|
|
cpu = <&CPU6>;
|
|
};
|
|
};
|
|
|
|
cluster2 {
|
|
core0 {
|
|
cpu = <&CPU7>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
idle-states {
|
|
SILVER_OFF: silver-c4 { /* C4 */
|
|
compatible = "arm,idle-state";
|
|
idle-state-name = "rail-pc";
|
|
entry-latency-us = <360>;
|
|
exit-latency-us = <531>;
|
|
min-residency-us = <3934>;
|
|
arm,psci-suspend-param = <0x40000004>;
|
|
local-timer-stop;
|
|
};
|
|
|
|
GOLD_OFF: gold-c4 { /* C4 */
|
|
compatible = "arm,idle-state";
|
|
idle-state-name = "rail-pc";
|
|
entry-latency-us = <702>;
|
|
exit-latency-us = <1061>;
|
|
min-residency-us = <4488>;
|
|
arm,psci-suspend-param = <0x40000004>;
|
|
local-timer-stop;
|
|
};
|
|
|
|
APSS_OFF: cluster-e3 { /* LLCC off, AOSS sleep */
|
|
compatible = "domain-idle-state";
|
|
idle-state-name = "llcc-off";
|
|
entry-latency-us = <3263>;
|
|
exit-latency-us = <6562>;
|
|
min-residency-us = <9987>;
|
|
arm,psci-suspend-param = <0x4100c344>;
|
|
};
|
|
};
|
|
|
|
soc: soc {
|
|
cpufreq_hw: qcom,cpufreq-hw {
|
|
compatible = "qcom,cpufreq-epss";
|
|
reg = <0x18591000 0x1000>, <0x18592000 0x1000>,
|
|
<0x18593000 0x1000>;
|
|
reg-names = "freq-domain0", "freq-domain1",
|
|
"freq-domain2";
|
|
|
|
//clocks = <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GPLL0>;
|
|
//clock-names = "xo", "alternate";
|
|
|
|
qcom,lut-row-size = <4>;
|
|
qcom,skip-enable-check;
|
|
|
|
#freq-domain-cells = <2>;
|
|
|
|
cpu7_notify: cpu7-notify {
|
|
qcom,cooling-cpu = <&CPU7>;
|
|
#cooling-cells = <2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-1.0";
|
|
method = "smc";
|
|
};
|
|
|
|
firmware: firmware {
|
|
qcom_scm {
|
|
compatible = "qcom,scm";
|
|
};
|
|
|
|
qtee_shmbridge {
|
|
compatible = "qcom,tee-shared-memory-bridge";
|
|
};
|
|
|
|
android {
|
|
compatible = "android,firmware";
|
|
vbmeta {
|
|
compatible = "android,vbmeta";
|
|
parts = "vbmeta,boot,system,vendor,dtbo,recovery";
|
|
};
|
|
|
|
fstab {
|
|
compatible = "android,fstab";
|
|
vendor {
|
|
compatible = "android,vendor";
|
|
dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor";
|
|
type = "ext4";
|
|
mnt_flags = "ro,barrier=1,discard";
|
|
fsmgr_flags = "wait,slotselect,avb";
|
|
status = "ok";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&reserved_memory {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
hyp_mem: hyp_region@80000000 {
|
|
no-map;
|
|
reg = <0x0 0x80000000 0x0 0x600000>;
|
|
};
|
|
|
|
xbl_aop_mem: xbl_aop_region@80700000 {
|
|
no-map;
|
|
reg = <0x0 0x80700000 0x0 0x160000>;
|
|
};
|
|
|
|
cmd_db: reserved-memory@80860000 {
|
|
reg = <0x0 0x80860000 0x0 0x20000>;
|
|
compatible = "qcom,cmd-db";
|
|
no-map;
|
|
};
|
|
|
|
smem_mem: smem_region@80900000 {
|
|
no-map;
|
|
reg = <0x0 0x80900000 0x0 0x200000>;
|
|
};
|
|
|
|
removed_mem: removed_region@80b00000 {
|
|
no-map;
|
|
reg = <0x0 0x80b00000 0x0 0x5300000>;
|
|
};
|
|
|
|
pil_camera_mem: pil_camera_region@86200000 {
|
|
no-map;
|
|
reg = <0x0 0x86200000 0x0 0x500000>;
|
|
};
|
|
|
|
pil_wlan_fw_mem: pil_wlan_fw_region@86700000 {
|
|
no-map;
|
|
reg = <0x0 0x86700000 0x0 0x100000>;
|
|
};
|
|
|
|
pil_ipa_fw_mem: pil_ipa_fw_region@86800000 {
|
|
no-map;
|
|
reg = <0x0 0x86800000 0x0 0x10000>;
|
|
};
|
|
|
|
pil_ipa_gsi_mem: pil_ipa_gsi_region@86810000 {
|
|
no-map;
|
|
reg = <0x0 0x86810000 0x0 0xa000>;
|
|
};
|
|
|
|
pil_gpu_mem: pil_gpu_region@8681a000 {
|
|
no-map;
|
|
reg = <0x0 0x8681a000 0x0 0x2000>;
|
|
};
|
|
|
|
pil_npu_mem: pil_npu_region@86900000 {
|
|
no-map;
|
|
reg = <0x0 0x86900000 0x0 0x500000>;
|
|
};
|
|
|
|
video_mem: video_region@86e00000 {
|
|
no-map;
|
|
reg = <0x0 0x86e00000 0x0 0x500000>;
|
|
};
|
|
|
|
pil_cvp_mem: pil_cvp_region@87300000 {
|
|
no-map;
|
|
reg = <0x0 0x87300000 0x0 0x500000>;
|
|
};
|
|
|
|
pil_cdsp_mem: pil_cdsp_region@87800000 {
|
|
no-map;
|
|
reg = <0x0 0x87800000 0x0 0x1400000>;
|
|
};
|
|
|
|
pil_slpi_mem: pil_slpi_region@88c00000 {
|
|
no-map;
|
|
reg = <0x0 0x88c00000 0x0 0x1500000>;
|
|
};
|
|
|
|
pil_adsp_mem: pil_adsp_region@8a100000 {
|
|
no-map;
|
|
reg = <0x0 0x8a100000 0x0 0x1d00000>;
|
|
};
|
|
|
|
pil_spss_mem: pil_spss_region@8be00000 {
|
|
no-map;
|
|
reg = <0x0 0x8be00000 0x0 0x100000>;
|
|
};
|
|
|
|
cdsp_secure_heap: cdsp_secure_heap@8bf00000 {
|
|
no-map;
|
|
reg = <0x0 0x8bf00000 0x0 0x4600000>;
|
|
};
|
|
|
|
adsp_mem: adsp_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0xC00000>;
|
|
};
|
|
|
|
sdsp_mem: sdsp_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0x800000>;
|
|
};
|
|
|
|
cdsp_mem: cdsp_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0x400000>;
|
|
};
|
|
|
|
cont_splash_memory: cont_splash_region@9c000000 {
|
|
reg = <0x0 0x9c000000 0x0 0x02300000>;
|
|
label = "cont_splash_region";
|
|
};
|
|
|
|
disp_rdump_memory: disp_rdump_region@9c000000 {
|
|
reg = <0x0 0x9c000000 0x0 0x00800000>;
|
|
label = "disp_rdump_region";
|
|
};
|
|
|
|
dfps_data_memory: dfps_data_region@9e300000 {
|
|
reg = <0x0 0x9e300000 0x0 0x0100000>;
|
|
label = "dfps_data_region";
|
|
};
|
|
|
|
dump_mem: mem_dump_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
size = <0 0x2800000>;
|
|
};
|
|
|
|
sp_mem: sp_region { /* SPSS-HLOS ION shared mem */
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0x1000000>;
|
|
};
|
|
|
|
user_contig_mem: user_contig_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0x1000000>;
|
|
};
|
|
|
|
qseecom_mem: qseecom_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0x1400000>;
|
|
};
|
|
|
|
qseecom_ta_mem: qseecom_ta_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0x1000000>;
|
|
};
|
|
|
|
secure_display_memory: secure_display_region { /* Secure UI */
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0xA400000>;
|
|
};
|
|
|
|
cnss_wlan_mem: cnss_wlan_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0x1400000>;
|
|
};
|
|
|
|
/* global autoconfigured region for contiguous allocations */
|
|
linux,cma {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0x2000000>;
|
|
linux,cma-default;
|
|
};
|
|
|
|
mailbox_mem: mailbox_region {
|
|
compatible = "shared-dma-pool";
|
|
no-map;
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0x20000>;
|
|
};
|
|
};
|
|
|
|
&soc {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0 0xffffffff>;
|
|
compatible = "simple-bus";
|
|
|
|
intc: interrupt-controller@17a00000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
#redistributor-regions = <1>;
|
|
redistributor-stride = <0x0 0x20000>;
|
|
reg = <0x17a00000 0x10000>, /* GICD */
|
|
<0x17a60000 0x100000>; /* GICR * 8 */
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
arch_timer: timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
|
clock-frequency = <19200000>;
|
|
};
|
|
|
|
memtimer: timer@17c20000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
compatible = "arm,armv7-timer-mem";
|
|
reg = <0x17c20000 0x1000>;
|
|
clock-frequency = <19200000>;
|
|
|
|
frame@17c21000 {
|
|
frame-number = <0>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c21000 0x1000>,
|
|
<0x17c22000 0x1000>;
|
|
};
|
|
|
|
frame@17c23000 {
|
|
frame-number = <1>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c23000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c25000 {
|
|
frame-number = <2>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c25000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c27000 {
|
|
frame-number = <3>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c27000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c29000 {
|
|
frame-number = <4>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c29000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c2b000 {
|
|
frame-number = <5>;
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c2b000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c2d000 {
|
|
frame-number = <6>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c2d000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
cpu_pmu: cpu-pmu {
|
|
compatible = "arm,armv8-pmuv3";
|
|
qcom,irq-is-percpu;
|
|
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
apps_rsc: rsc@18200000 {
|
|
label = "apps_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0x18200000 0x10000>,
|
|
<0x18210000 0x10000>,
|
|
<0x18220000 0x10000>;
|
|
reg-names = "drv-0", "drv-1", "drv-2";
|
|
qcom,drv-count = <3>;
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
apps_rsc_drv2: drv@2 {
|
|
qcom,drv-id = <2>;
|
|
qcom,tcs-offset = <0xd00>;
|
|
channel@0 {
|
|
qcom,tcs-config = <ACTIVE_TCS 2>,
|
|
<SLEEP_TCS 3>,
|
|
<WAKE_TCS 3>,
|
|
<CONTROL_TCS 0>,
|
|
<FAST_PATH_TCS 0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
disp_rsc: rsc@af20000 {
|
|
label = "disp_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0xaf20000 0x10000>;
|
|
reg-names = "drv-0";
|
|
qcom,drv-count = <1>;
|
|
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
disp_rsc_drv0: drv@0 {
|
|
qcom,drv-id = <0>;
|
|
qcom,tcs-offset = <0x1c00>;
|
|
channel@0 {
|
|
qcom,tcs-config = <ACTIVE_TCS 0>,
|
|
<SLEEP_TCS 1>,
|
|
<WAKE_TCS 1>,
|
|
<CONTROL_TCS 0>,
|
|
<FAST_PATH_TCS 0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pdc: interrupt-controller@b220000 {
|
|
compatible = "qcom,pdc", "qcom,kona-pdc";
|
|
reg = <0xb220000 0x30000>, <0x17c000f0 0x60>;
|
|
qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>, <126 716 12>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-parent = <&intc>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
qcom,chd_silver {
|
|
compatible = "qcom,core-hang-detect";
|
|
label = "silver";
|
|
qcom,threshold-arr = <0x18000058 0x18010058
|
|
0x18020058 0x18030058>;
|
|
qcom,config-arr = <0x18000060 0x18010060
|
|
0x18020060 0x18030060>;
|
|
};
|
|
|
|
qcom,chd_gold {
|
|
compatible = "qcom,core-hang-detect";
|
|
label = "gold";
|
|
qcom,threshold-arr = <0x18040058 0x18050058
|
|
0x18060058 0x18070058>;
|
|
qcom,config-arr = <0x18040060 0x18050060
|
|
0x18060060 0x18070060>;
|
|
};
|
|
|
|
cache-controller@9200000 {
|
|
//compatible = "qcom,kona-llcc";
|
|
reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>;
|
|
reg-names = "llcc_base", "llcc_broadcast_base";
|
|
cap-based-alloc-and-pwr-collapse;
|
|
};
|
|
|
|
wdog: qcom,wdt@17c10000 {
|
|
compatible = "qcom,msm-watchdog";
|
|
reg = <0x17c10000 0x1000>;
|
|
reg-names = "wdt-base";
|
|
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,bark-time = <11000>;
|
|
qcom,pet-time = <9360>;
|
|
qcom,wakeup-enable;
|
|
qcom,ipi-ping;
|
|
};
|
|
|
|
qcom,msm-imem@146bf000 {
|
|
compatible = "qcom,msm-imem";
|
|
reg = <0x146bf000 0x1000>;
|
|
ranges = <0x0 0x146bf000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
mem_dump_table@10 {
|
|
compatible = "qcom,msm-imem-mem_dump_table";
|
|
reg = <0x10 0x8>;
|
|
};
|
|
|
|
restart_reason@65c {
|
|
compatible = "qcom,msm-imem-restart_reason";
|
|
reg = <0x65c 0x4>;
|
|
};
|
|
|
|
dload_type@1c {
|
|
compatible = "qcom,msm-imem-dload-type";
|
|
reg = <0x1c 0x4>;
|
|
};
|
|
|
|
boot_stats@6b0 {
|
|
compatible = "qcom,msm-imem-boot_stats";
|
|
reg = <0x6b0 0x20>;
|
|
};
|
|
|
|
kaslr_offset@6d0 {
|
|
compatible = "qcom,msm-imem-kaslr_offset";
|
|
reg = <0x6d0 0xc>;
|
|
};
|
|
|
|
pil@94c {
|
|
compatible = "qcom,msm-imem-pil";
|
|
reg = <0x94c 0xc8>;
|
|
};
|
|
|
|
diag_dload@c8 {
|
|
compatible = "qcom,msm-imem-diag-dload";
|
|
reg = <0xc8 0xc8>;
|
|
};
|
|
};
|
|
|
|
qcom,mpm2-sleep-counter@c221000 {
|
|
compatible = "qcom,mpm2-sleep-counter";
|
|
reg = <0xc221000 0x1000>;
|
|
clock-frequency = <32768>;
|
|
};
|
|
|
|
qcom-secure-buffer {
|
|
compatible = "qcom,secure-buffer";
|
|
};
|
|
|
|
mem_dump {
|
|
compatible = "qcom,mem-dump";
|
|
memory-region = <&dump_mem>;
|
|
|
|
c0_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x0>;
|
|
};
|
|
|
|
c100_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x1>;
|
|
};
|
|
|
|
c200_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x2>;
|
|
};
|
|
|
|
c300_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x3>;
|
|
};
|
|
|
|
c400_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x4>;
|
|
};
|
|
|
|
c500_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x5>;
|
|
};
|
|
|
|
c600_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x6>;
|
|
};
|
|
|
|
c700_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x7>;
|
|
};
|
|
|
|
c0_scandump {
|
|
qcom,dump-size = <0x10100>;
|
|
qcom,dump-id = <0x130>;
|
|
};
|
|
|
|
c100_scandump {
|
|
qcom,dump-size = <0x10100>;
|
|
qcom,dump-id = <0x131>;
|
|
};
|
|
|
|
c200_scandump {
|
|
qcom,dump-size = <0x10100>;
|
|
qcom,dump-id = <0x132>;
|
|
};
|
|
|
|
c300_scandump {
|
|
qcom,dump-size = <0x10100>;
|
|
qcom,dump-id = <0x133>;
|
|
};
|
|
|
|
c400_scandump {
|
|
qcom,dump-size = <0x1a4c0>;
|
|
qcom,dump-id = <0x134>;
|
|
};
|
|
|
|
c500_scandump {
|
|
qcom,dump-size = <0x1a4c0>;
|
|
qcom,dump-id = <0x135>;
|
|
};
|
|
|
|
c600_scandump {
|
|
qcom,dump-size = <0x1a4c0>;
|
|
qcom,dump-id = <0x136>;
|
|
};
|
|
|
|
c700_scandump {
|
|
qcom,dump-size = <0x1a4c0>;
|
|
qcom,dump-id = <0x137>;
|
|
};
|
|
|
|
cpuss_reg {
|
|
qcom,dump-size = <0x30000>;
|
|
qcom,dump-id = <0xef>;
|
|
};
|
|
|
|
l1_icache0 {
|
|
qcom,dump-size = <0x10800>;
|
|
qcom,dump-id = <0x60>;
|
|
};
|
|
|
|
l1_icache100 {
|
|
qcom,dump-size = <0x10800>;
|
|
qcom,dump-id = <0x61>;
|
|
};
|
|
|
|
l1_icache200 {
|
|
qcom,dump-size = <0x10800>;
|
|
qcom,dump-id = <0x62>;
|
|
};
|
|
|
|
l1_icache300 {
|
|
qcom,dump-size = <0x10800>;
|
|
qcom,dump-id = <0x63>;
|
|
};
|
|
|
|
l1_icache400 {
|
|
qcom,dump-size = <0x26000>;
|
|
qcom,dump-id = <0x64>;
|
|
};
|
|
|
|
l1_icache500 {
|
|
qcom,dump-size = <0x26000>;
|
|
qcom,dump-id = <0x65>;
|
|
};
|
|
|
|
l1_icache600 {
|
|
qcom,dump-size = <0x26000>;
|
|
qcom,dump-id = <0x66>;
|
|
};
|
|
|
|
l1_icache700 {
|
|
qcom,dump-size = <0x26000>;
|
|
qcom,dump-id = <0x67>;
|
|
};
|
|
|
|
l1_dcache0 {
|
|
qcom,dump-size = <0x9000>;
|
|
qcom,dump-id = <0x80>;
|
|
};
|
|
|
|
l1_dcache100 {
|
|
qcom,dump-size = <0x9000>;
|
|
qcom,dump-id = <0x81>;
|
|
};
|
|
|
|
l1_dcache200 {
|
|
qcom,dump-size = <0x9000>;
|
|
qcom,dump-id = <0x82>;
|
|
};
|
|
|
|
l1_dcache300 {
|
|
qcom,dump-size = <0x9000>;
|
|
qcom,dump-id = <0x83>;
|
|
};
|
|
|
|
l1_dcache400 {
|
|
qcom,dump-size = <0x1A000>;
|
|
qcom,dump-id = <0x84>;
|
|
};
|
|
|
|
l1_dcache500 {
|
|
qcom,dump-size = <0x1A000>;
|
|
qcom,dump-id = <0x85>;
|
|
};
|
|
|
|
l1_dcache600 {
|
|
qcom,dump-size = <0x1A000>;
|
|
qcom,dump-id = <0x86>;
|
|
};
|
|
|
|
l1_dcache700 {
|
|
qcom,dump-size = <0x1A000>;
|
|
qcom,dump-id = <0x87>;
|
|
};
|
|
|
|
l1_itlb400 {
|
|
qcom,dump-size = <0x300>;
|
|
qcom,dump-id = <0x24>;
|
|
};
|
|
|
|
l1_itlb500 {
|
|
qcom,dump-size = <0x300>;
|
|
qcom,dump-id = <0x25>;
|
|
};
|
|
|
|
l1_itlb600 {
|
|
qcom,dump-size = <0x300>;
|
|
qcom,dump-id = <0x26>;
|
|
};
|
|
|
|
l1_itlb700 {
|
|
qcom,dump-size = <0x300>;
|
|
qcom,dump-id = <0x27>;
|
|
};
|
|
|
|
l1_dtlb400 {
|
|
qcom,dump-size = <0x480>;
|
|
qcom,dump-id = <0x44>;
|
|
};
|
|
|
|
l1_dtlb500 {
|
|
qcom,dump-size = <0x480>;
|
|
qcom,dump-id = <0x45>;
|
|
};
|
|
|
|
l1_dtlb600 {
|
|
qcom,dump-size = <0x480>;
|
|
qcom,dump-id = <0x46>;
|
|
};
|
|
|
|
l1_dtlb700 {
|
|
qcom,dump-size = <0x480>;
|
|
qcom,dump-id = <0x47>;
|
|
};
|
|
|
|
l2_cache400 {
|
|
qcom,dump-size = <0x68000>;
|
|
qcom,dump-id = <0xc4>;
|
|
};
|
|
|
|
l2_cache500 {
|
|
qcom,dump-size = <0x68000>;
|
|
qcom,dump-id = <0xc5>;
|
|
};
|
|
|
|
l2_cache600 {
|
|
qcom,dump-size = <0x68000>;
|
|
qcom,dump-id = <0xc6>;
|
|
};
|
|
|
|
l2_cache700 {
|
|
qcom,dump-size = <0xD0000>;
|
|
qcom,dump-id = <0xc7>;
|
|
};
|
|
|
|
l2_tlb0 {
|
|
qcom,dump-size = <0x6000>;
|
|
qcom,dump-id = <0x120>;
|
|
};
|
|
|
|
l2_tlb100 {
|
|
qcom,dump-size = <0x6000>;
|
|
qcom,dump-id = <0x121>;
|
|
};
|
|
|
|
l2_tlb200 {
|
|
qcom,dump-size = <0x6000>;
|
|
qcom,dump-id = <0x122>;
|
|
};
|
|
|
|
l2_tlb300 {
|
|
qcom,dump-size = <0x6000>;
|
|
qcom,dump-id = <0x123>;
|
|
};
|
|
|
|
l2_tlb400 {
|
|
qcom,dump-size = <0x7800>;
|
|
qcom,dump-id = <0x124>;
|
|
};
|
|
|
|
l2_tlb500 {
|
|
qcom,dump-size = <0x7800>;
|
|
qcom,dump-id = <0x125>;
|
|
};
|
|
|
|
l2_tlb600 {
|
|
qcom,dump-size = <0x7800>;
|
|
qcom,dump-id = <0x126>;
|
|
};
|
|
|
|
l2_tlb700 {
|
|
qcom,dump-size = <0x7800>;
|
|
qcom,dump-id = <0x127>;
|
|
};
|
|
|
|
gemnoc {
|
|
qcom,dump-size = <0x100000>;
|
|
qcom,dump-id = <0x162>;
|
|
};
|
|
|
|
mhm_scan {
|
|
qcom,dump-size = <0x20000>;
|
|
qcom,dump-id = <0x161>;
|
|
};
|
|
|
|
rpmh {
|
|
qcom,dump-size = <0x2000000>;
|
|
qcom,dump-id = <0xec>;
|
|
};
|
|
|
|
rpm_sw {
|
|
qcom,dump-size = <0x28000>;
|
|
qcom,dump-id = <0xea>;
|
|
};
|
|
|
|
pmic {
|
|
qcom,dump-size = <0x80000>;
|
|
qcom,dump-id = <0xe4>;
|
|
};
|
|
|
|
fcm {
|
|
qcom,dump-size = <0x8400>;
|
|
qcom,dump-id = <0xee>;
|
|
};
|
|
|
|
etf_swao {
|
|
qcom,dump-size = <0x10000>;
|
|
qcom,dump-id = <0xf1>;
|
|
};
|
|
|
|
etr_reg {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0x100>;
|
|
};
|
|
|
|
etfswao_reg {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0x102>;
|
|
};
|
|
|
|
misc_data {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0xe8>;
|
|
};
|
|
|
|
etf_slpi {
|
|
qcom,dump-size = <0x4000>;
|
|
qcom,dump-id = <0xf3>;
|
|
};
|
|
|
|
etfslpi_reg {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0x103>;
|
|
};
|
|
|
|
etf_lpass {
|
|
qcom,dump-size = <0x4000>;
|
|
qcom,dump-id = <0xf4>;
|
|
};
|
|
|
|
etflpass_reg {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0x104>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
#include "kona-regulators.dtsi"
|
|
#include "kona-pinctrl.dtsi"
|