mirror of
https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-02-01 09:49:52 +00:00
1cc7395a15
Add devicetree bindings snapshot to the devicetree project Change-Id: Ic48a6fa76bbc126bd8f6bafc7678e7afbc3f18cf
34 lines
1.0 KiB
Plaintext
34 lines
1.0 KiB
Plaintext
Andestech ATCPIT100 timer
|
|
------------------------------------------------------------------
|
|
ATCPIT100 is a generic IP block from Andes Technology, embedded in
|
|
Andestech AE3XX platforms and other designs.
|
|
|
|
This timer is a set of compact multi-function timers, which can be
|
|
used as pulse width modulators (PWM) as well as simple timers.
|
|
|
|
It supports up to 4 PIT channels. Each PIT channel is a
|
|
multi-function timer and provide the following usage scenarios:
|
|
One 32-bit timer
|
|
Two 16-bit timers
|
|
Four 8-bit timers
|
|
One 16-bit PWM
|
|
One 16-bit timer and one 8-bit PWM
|
|
Two 8-bit timer and one 8-bit PWM
|
|
|
|
Required properties:
|
|
- compatible : Should be "andestech,atcpit100"
|
|
- reg : Address and length of the register set
|
|
- interrupts : Reference to the timer interrupt
|
|
- clocks : a clock to provide the tick rate for "andestech,atcpit100"
|
|
- clock-names : should be "PCLK" for the peripheral clock source.
|
|
|
|
Examples:
|
|
|
|
timer0: timer@f0400000 {
|
|
compatible = "andestech,atcpit100";
|
|
reg = <0xf0400000 0x1000>;
|
|
interrupts = <2>;
|
|
clocks = <&apb>;
|
|
clock-names = "PCLK";
|
|
};
|