mirror of
https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-02-01 09:04:24 +00:00
471 lines
9.9 KiB
Plaintext
471 lines
9.9 KiB
Plaintext
#include <dt-bindings/clock/qcom,ecpricc-cinder.h>
|
|
#include <dt-bindings/clock/qcom,gcc-cinder.h>
|
|
#include <dt-bindings/clock/qcom,rpmh.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/soc/qcom,ipcc.h>
|
|
/ {
|
|
interrupt-parent = <&intc>;
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
memory { device_type = "memory"; reg = <0 0 0 0>; };
|
|
|
|
|
|
chosen: chosen { };
|
|
|
|
aliases {
|
|
serial0 = &qupv3_se7_2uart;
|
|
};
|
|
|
|
firmware: firmware { };
|
|
|
|
cpus {
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
|
|
CPU0: cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a55";
|
|
reg = <0x0 0x0>;
|
|
enable-method = "spin-table";
|
|
cpu-release-addr = <0x0 0x80C40000>;
|
|
next-level-cache = <&L2_0>;
|
|
L2_0: l2-cache {
|
|
compatible = "arm,arch-cache";
|
|
cache-level = <2>;
|
|
next-level-cache = <&L3_0>;
|
|
|
|
L3_0: l3-cache {
|
|
compatible = "arm,arch-cache";
|
|
cache-level = <3>;
|
|
};
|
|
};
|
|
};
|
|
|
|
CPU1: cpu@100 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a55";
|
|
reg = <0x0 0x100>;
|
|
enable-method = "spin-table";
|
|
cpu-release-addr = <0x0 0x80C40000>;
|
|
next-level-cache = <&L2_1>;
|
|
L2_1: l2-cache {
|
|
compatible = "arm,arch-cache";
|
|
cache-level = <2>;
|
|
next-level-cache = <&L3_0>;
|
|
};
|
|
|
|
};
|
|
|
|
CPU2: cpu@200 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a55";
|
|
reg = <0x0 0x200>;
|
|
enable-method = "spin-table";
|
|
cpu-release-addr = <0x0 0x80C40000>;
|
|
next-level-cache = <&L2_2>;
|
|
L2_2: l2-cache {
|
|
compatible = "arm,arch-cache";
|
|
cache-level = <2>;
|
|
next-level-cache = <&L3_0>;
|
|
};
|
|
};
|
|
|
|
CPU3: cpu@300 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a55";
|
|
reg = <0x0 0x300>;
|
|
enable-method = "spin-table";
|
|
cpu-release-addr = <0x0 0x80C40000>;
|
|
next-level-cache = <&L2_3>;
|
|
L2_3: l2-cache {
|
|
compatible = "arm,arch-cache";
|
|
cache-level = <2>;
|
|
next-level-cache = <&L3_0>;
|
|
};
|
|
|
|
};
|
|
|
|
cpu-map {
|
|
cluster0 {
|
|
core0 {
|
|
cpu = <&CPU0>;
|
|
};
|
|
|
|
core1 {
|
|
cpu = <&CPU1>;
|
|
};
|
|
|
|
core2 {
|
|
cpu = <&CPU2>;
|
|
};
|
|
|
|
core3 {
|
|
cpu = <&CPU3>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
soc: soc { };
|
|
};
|
|
|
|
#include "cinder-stub-regulator.dtsi"
|
|
|
|
&soc {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0 0xffffffff>;
|
|
compatible = "simple-bus";
|
|
|
|
intc: interrupt-controller@17200000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
#redistributor-regions = <1>;
|
|
redistributor-stride = <0x0 0x20000>;
|
|
reg = <0x17200000 0x10000>, /* GICD */
|
|
<0x17260000 0x80000>; /* GICR * 4 */
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
arch_timer: timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
|
clock-frequency = <19200000>;
|
|
};
|
|
|
|
memtimer: timer@17420000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
compatible = "arm,armv7-timer-mem";
|
|
reg = <0x17420000 0x1000>;
|
|
clock-frequency = <19200000>;
|
|
|
|
frame@17421000 {
|
|
frame-number = <0>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17421000 0x1000>,
|
|
<0x17422000 0x1000>;
|
|
};
|
|
|
|
frame@17423000 {
|
|
frame-number = <1>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17423000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17425000 {
|
|
frame-number = <2>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17425000 0x1000>,
|
|
<0x17426000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17427000 {
|
|
frame-number = <3>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17427000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17429000 {
|
|
frame-number = <4>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17429000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@1742b000 {
|
|
frame-number = <5>;
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x1742b000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@1742d000 {
|
|
frame-number = <6>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x1742d000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
cpu_pmu: cpu-pmu {
|
|
compatible = "arm,armv8-pmuv3";
|
|
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
kryo_erp {
|
|
compatible = "arm,arm64-kryo-cpu-erp";
|
|
interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_PPI 1 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "l1-l2-faultirq",
|
|
"l1-l2-errirq",
|
|
"l3-scu-errirq",
|
|
"l3-scu-faultirq";
|
|
};
|
|
|
|
qcom,msm-imem@14680000 {
|
|
compatible = "qcom,msm-imem";
|
|
reg = <0x14680000 0x1000>;
|
|
ranges = <0x0 0x14680000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
mem_dump_table@10 {
|
|
compatible = "qcom,msm-imem-mem_dump_table";
|
|
reg = <0x10 0x8>;
|
|
};
|
|
|
|
restart_reason@65c {
|
|
compatible = "qcom,msm-imem-restart_reason";
|
|
reg = <0x65c 0x4>;
|
|
};
|
|
|
|
dload_type@1c {
|
|
compatible = "qcom,msm-imem-dload-type";
|
|
reg = <0x1c 0x4>;
|
|
};
|
|
|
|
boot_stats@6b0 {
|
|
compatible = "qcom,msm-imem-boot_stats";
|
|
reg = <0x6b0 0x20>;
|
|
};
|
|
|
|
kaslr_offset@6d0 {
|
|
compatible = "qcom,msm-imem-kaslr_offset";
|
|
reg = <0x6d0 0xc>;
|
|
};
|
|
|
|
pil@94c {
|
|
compatible = "qcom,pil-reloc-info";
|
|
reg = <0x94c 0xc8>;
|
|
};
|
|
|
|
pil@6dc {
|
|
compatible = "qcom,msm-imem-pil-disable-timeout";
|
|
reg = <0x6dc 0x4>;
|
|
};
|
|
|
|
diag_dload@c8 {
|
|
compatible = "qcom,msm-imem-diag-dload";
|
|
reg = <0xc8 0xc8>;
|
|
};
|
|
};
|
|
|
|
qcom,msm-rtb {
|
|
compatible = "qcom,msm-rtb";
|
|
qcom,rtb-size = <0x100000>;
|
|
};
|
|
|
|
tlmm: pinctrl@f000000 {
|
|
compatible = "qcom,cinder-pinctrl";
|
|
reg = <0xf000000 0x1000000>;
|
|
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
qcom,mpm2-sleep-counter@c221000 {
|
|
compatible = "qcom,mpm2-sleep-counter";
|
|
reg = <0xc221000 0x1000>;
|
|
clock-frequency = <32768>;
|
|
};
|
|
|
|
tcsr: syscon@1fc0000 {
|
|
compatible = "syscon";
|
|
reg = <0x1fc0000 0x30000>;
|
|
};
|
|
|
|
qcom,dload-mode {
|
|
compatible = "qcom,dload-mode";
|
|
};
|
|
|
|
ipcc_mproc: qcom,ipcc@408000 {
|
|
compatible = "qcom,ipcc";
|
|
reg = <0x408000 0x1000>;
|
|
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
#mbox-cells = <2>;
|
|
};
|
|
|
|
qcom,smp2p-modem {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <435>, <428>;
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <1>;
|
|
|
|
modem_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
modem_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
aoss_qmp: power-controller@c300000 {
|
|
compatible = "qcom,cinder-aoss-qmp";
|
|
reg = <0xc300000 0x400>;
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_AOP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
|
|
#power-domain-cells = <1>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
qmp_aop: qcom,qmp-aop {
|
|
compatible = "qcom,qmp-mbox";
|
|
qcom,qmp = <&aoss_qmp>;
|
|
label = "aop";
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
qmp_tme: qcom,qmp-tme {
|
|
compatible = "qcom,qmp-mbox";
|
|
qcom,remote-pid = <14>;
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_TME
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
mbox-names = "tme_qmp";
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_TME
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "tme";
|
|
qcom,early-boot;
|
|
priority = <0>;
|
|
mbox-desc-offset = <0x0>;
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
qcom,chd {
|
|
compatible = "qcom,core-hang-detect";
|
|
label = "core";
|
|
qcom,threshold-arr = <0x17800058 0x17810058 0x17820058 0x17830058>;
|
|
qcom,config-arr = <0x17800060 0x17810060 0x17820060 0x17830060>;
|
|
};
|
|
|
|
vendor_hooks: qcom,cpu-vendor-hooks {
|
|
compatible = "qcom,cpu-vendor-hooks";
|
|
};
|
|
|
|
clocks {
|
|
xo_board: xo_board {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <38400000>;
|
|
clock-output-names = "xo_board";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
sleep_clk: sleep_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <32000>;
|
|
clock-output-names = "sleep_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
};
|
|
|
|
bi_tcxo: bi_tcxo {
|
|
compatible = "fixed-factor-clock";
|
|
clock-mult = <1>;
|
|
clock-div = <2>;
|
|
clocks = <&xo_board>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
bi_tcxo_ao: bi_tcxo_ao {
|
|
compatible = "fixed-factor-clock";
|
|
clock-mult = <1>;
|
|
clock-div = <2>;
|
|
clocks = <&xo_board>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
ecpricc: clock-controller@280000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "ecpricc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
gcc: clock-controller@80000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "gcc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
rpmhcc: clock-controller@0 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "rpmhcc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
/* GCC GDSCs */
|
|
gcc_pcie_0_gdsc: qcom,gdsc@11d004 {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "gcc_pcie_0_gdsc";
|
|
};
|
|
|
|
gcc_pcie_0_phy_gdsc: qcom,gdsc@fc004 {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "gcc_pcie_0_phy_gdsc";
|
|
};
|
|
|
|
gcc_usb30_prim_gdsc: qcom,gdsc@c9004 {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "gcc_usb30_prim_gdsc";
|
|
};
|
|
|
|
wdog: qcom,wdt@17410000 {
|
|
compatible ="qcom,msm-watchdog";
|
|
reg = <0x17410000 0x1000>;
|
|
reg-names = "wdt-base";
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
};
|
|
|
|
&firmware {
|
|
qcom_scm {
|
|
compatible = "qcom,scm";
|
|
qcom,dload-mode = <&tcsr 0x13000>;
|
|
};
|
|
|
|
};
|
|
|
|
#include "cinder-pinctrl.dtsi"
|
|
#include "cinder-qupv3.dtsi"
|
|
|
|
&qupv3_se7_2uart {
|
|
status = "ok";
|
|
};
|