mirror of
https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-02-01 09:49:52 +00:00
f4d65850e0
Enable nand smmu for only hlos bam pipes 0x7 enables mask for both hlos and modem 0x3 enables mask for only hlos bam pipes. Change-Id: I3d05e575bf327f29445db5284d31c2eb7ee3a04b
973 lines
20 KiB
Plaintext
973 lines
20 KiB
Plaintext
#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,sa410m.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/qcom,gcc-sa410m.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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/ {
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model = "Qualcomm Technologies, Inc. SA410M";
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compatible = "qcom,sa410m";
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qcom,msm-id = <560 0x10000>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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reserved_memory: reserved-memory { };
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mem-offline {
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compatible = "qcom,mem-offline";
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offline-sizes = <0x1 0x40000000 0x0 0x40000000>,
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<0x1 0xc0000000 0x0 0x80000000>,
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<0x2 0xc0000000 0x1 0x40000000>;
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granule = <512>;
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};
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aliases {
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serial0 = &qupv3_se4_2uart;
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qpic_nand1 = &qnand_1;
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mmc0 = &sdhc_1; /*SDC1 eMMC slot*/
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pci-domain0 = &pcie0;
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};
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firmware: firmware {};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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cpu-idle-states = <&SILVER_OFF>;
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power-domains = <&CPU_PD0>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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next-level-cache = <&L2_0>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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#cooling-cells = <2>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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};
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L1_I_0: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_0: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x1>;
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cpu-idle-states = <&SILVER_OFF>;
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power-domains = <&CPU_PD1>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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next-level-cache = <&L2_0>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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#cooling-cells = <2>;
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L1_I_1: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_1: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x2>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_OFF>;
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power-domains = <&CPU_PD2>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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next-level-cache = <&L2_0>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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#cooling-cells = <2>;
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L1_I_2: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_2: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x3>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_OFF>;
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power-domains = <&CPU_PD3>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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next-level-cache = <&L2_0>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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#cooling-cells = <2>;
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L1_I_3: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_3: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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};
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};
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idle-states {
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SILVER_OFF: silver-c3 { /* C3 */
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compatible = "arm,idle-state";
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idle-state-name = "pc";
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entry-latency-us = <297>;
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exit-latency-us = <324>;
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min-residency-us = <1110>;
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arm,psci-suspend-param = <0x40000003>;
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local-timer-stop;
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};
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SILVER_CLUSTER_D3: silver-cluster-d3 { /* D3 */
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compatible = "domain-idle-state";
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idle-state-name = "pwr-l2-pc";
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entry-latency-us = <800>;
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exit-latency-us = <2118>;
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min-residency-us = <7376>;
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arm,psci-suspend-param = <0x41000043>;
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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CPU_PD0: cpu-pd0 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD1: cpu-pd1 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD2: cpu-pd2 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD3: cpu-pd3 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CLUSTER_PD0: cluster-pd0 {
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#power-domain-cells = <0>;
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domain-idle-states = <&SILVER_CLUSTER_D3>;
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};
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};
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chosen {
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bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 pcie_ports=compat";
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};
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soc: soc { };
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};
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&reserved_memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hyp_region: hyp_region@45600000 {
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no-map;
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reg = <0x0 0x45600000 0x0 0x700000>;
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};
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xbl_aop_mem: xbl_aop_mem@45d00000 {
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no-map;
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reg = <0x0 0x45d00000 0x0 0x200000>;
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};
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sec_apps_mem: sec_apps_region@45fff000 {
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no-map;
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reg = <0x0 0x45fff000 0x0 0x1000>;
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};
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smem_region: smem@46000000 {
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no-map;
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reg = <0x0 0x46000000 0x0 0x200000>;
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};
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pil_modem_mem: modem_region@4ab00000 {
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no-map;
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reg = <0x0 0x4ab00000 0x0 0x6900000>;
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};
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wlan_msa_mem: wlan_msa_region@51400000 {
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no-map;
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reg = <0x0 0x51400000 0x0 0x100000>;
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};
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pil_adsp_mem: adsp_regions@51500000 {
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no-map;
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reg = <0x0 0x51500000 0x0 0x1400000>;
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};
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pil_ipa_fw_mem: ips_fw_region@52900000 {
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no-map;
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reg = <0x0 0x52900000 0x0 0x10000>;
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};
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pil_ipa_gsi_mem: ipa_gsi_region@52910000 {
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no-map;
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reg = <0x0 0x52910000 0x0 0x5000>;
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};
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pil_reserved_unused_mem: pil_reserved_unused_region@52915000 {
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no-map;
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reg = <0x0 0x52915000 0x0 0xEB000>;
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};
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tz_stat: tz_stat@53200000 {
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no-map;
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reg = <0x0 0x53200000 0x0 0x100000>;
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};
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pimem_vault: pimem_vault@53300000 {
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no-map;
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reg = <0x0 0x53300000 0x0 0x1500000>;
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};
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adsp_mem: adsp_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0 0x00000000 0 0xffffffff>;
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reusable;
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alignment = <0 0x400000>;
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size = <0 0x800000>;
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};
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dump_mem: mem_dump_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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size = <0 0x800000>;
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};
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user_contig_mem: user_contig_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x1000000>;
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};
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qseecom_mem: qseecom_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x700000>;
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};
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qseecom_ta_mem: qseecom_ta_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x400000>;
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};
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memshare_mem: memshare_region {
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compatible = "shared-dma-pool";
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no-map;
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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alignment = <0x0 0x100000>;
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size = <0x0 0x800000>;
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};
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/* global autoconfigured region for contiguous allocations */
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system_cma:linux,cma {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x2000000>;
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linux,cma-default;
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};
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};
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&firmware {
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qtee_shmbridge {
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compatible = "qcom,tee-shared-memory-bridge";
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};
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qcom_smcinvoke {
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compatible = "qcom,smcinvoke";
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};
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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intc: interrupt-controller@f200000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupt-parent = <&intc>;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x20000>;
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reg = <0xf200000 0x10000>, /* GICD */
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<0xf300000 0x100000>; /* GICR * 8 */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <0>;
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};
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mpm: interrupt-controller@45f01b8 {
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compatible = "qcom,mpm-sa410m", "qcom,mpm";
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reg = <0x45f01b8 0x1000>,
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<0xf111008 0x4>, /* MSM_APCS_GCC_BASE 4K */
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<0xf121000 0x1000>;
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reg-names = "vmpm", "ipc", "timer";
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interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
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qcom,num-mpm-irqs = <96>;
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interrupt-controller;
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interrupt-parent = <&intc>;
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#interrupt-cells = <2>;
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};
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rpm_bus: qcom,rpm-smd {
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compatible = "qcom,rpm-smd";
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rpm-channel-name = "rpm_requests";
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interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
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power-domains = <&CLUSTER_PD>;
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rpm-channel-type = <15>; /* SMD_APPS_RPM */
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};
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cluster-device {
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compatible = "qcom,lpm-cluster-dev";
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power-domains = <&CLUSTER_PD>;
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};
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rpm-sleep-stats@4690000 {
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compatible = "qcom,rpm-sleep-stats";
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reg = <0x04690000 0x400>;
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};
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qcom,rpm-master-stats@45f0150 {
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compatible = "qcom,rpm-master-stats";
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reg = <0x45f0150 0x5000>;
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qcom,masters = "APSS", "MPSS", "ADSP", "CDSP", "TZ";
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qcom,master-stats-version = <2>;
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qcom,master-offset = <4096>;
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <19200000>;
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};
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qcom_tzlog: tz-log@c125720 {
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compatible = "qcom,tz-log";
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reg = <0xc125720 0x3000>;
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qcom,hyplog-enabled;
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hyplog-address-offset = <0x410>;
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hyplog-size-offset = <0x414>;
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};
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memtimer: timer@f120000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0xf120000 0x1000>;
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clock-frequency = <19200000>;
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frame@f121000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf121000 0x1000>,
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<0xf122000 0x1000>;
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};
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frame@f123000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf123000 0x1000>;
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status = "disabled";
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};
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frame@f124000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf124000 0x1000>;
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status = "disabled";
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};
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frame@f125000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf125000 0x1000>;
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status = "disabled";
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};
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frame@f126000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf126000 0x1000>;
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status = "disabled";
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};
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frame@f127000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf127000 0x1000>;
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status = "disabled";
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};
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frame@f128000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf128000 0x1000>;
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status = "disabled";
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};
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};
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tlmm: pinctrl@500000 {
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compatible = "qcom,sa410m-pinctrl";
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reg = <0x500000 0x7F000>,
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<0x598000 0xD000>;
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reg-names = "normal" , "extended";
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interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
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gpio-ranges = <&tlmm 0 0 139>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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wakeup-parent = <&mpm>;
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};
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qcom-secure-buffer {
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compatible = "qcom,secure-buffer";
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};
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qcom_scm: qcomscm {
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compatible = "qcom,scm";
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};
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qcom,rmtfs_sharedmem@0 {
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compatible = "qcom,sharedmem-uio";
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reg = <0x0 0x280000>;
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reg-names = "rmtfs";
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qcom,client-id = <0x00000001>;
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qcom,vm-nav-path;
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};
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clocks {
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xo_board: xo-board {
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compatible = "fixed-clock";
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clock-frequency = <38400000>;
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clock-output-names = "xo_board";
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#clock-cells = <0>;
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};
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|
|
|
sleep_clk: sleep-clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <32000>;
|
|
clock-output-names = "chip_sleep_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
pcie_0_pipe_clk: pcie_0_pipe_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "pcie_0_pipe_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
};
|
|
|
|
rpmcc: clock-controller {
|
|
compatible = "qcom,rpmcc-scuba";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
gcc: clock-controller@1400000 {
|
|
compatible = "qcom,sa410m-gcc", "syscon";
|
|
reg = <0x1400000 0x1f0000>;
|
|
reg-name = "cc_base";
|
|
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
|
clocks = <&rpmcc RPM_CXO_CLK>,
|
|
<&rpmcc RPM_CXO_A_CLK>,
|
|
<&pcie_0_pipe_clk>,
|
|
<&sleep_clk>,
|
|
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
|
|
clock-names = "bi_tcxo",
|
|
"bi_tcxo_ao",
|
|
"pcie_0_pipe_clk",
|
|
"sleep_clk",
|
|
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
mccc_debug: syscon@447d200 {
|
|
compatible = "syscon";
|
|
reg = <0x0447d200 0x100>;
|
|
};
|
|
|
|
cpucc_debug: syscon@f11101c {
|
|
compatible = "syscon";
|
|
reg = <0xf11101c 0x4>;
|
|
};
|
|
|
|
debugcc: clock-controller@0 {
|
|
compatible = "qcom,sa410m-debugcc";
|
|
qcom,gcc = <&gcc>;
|
|
qcom,mccc = <&mccc_debug>;
|
|
qcom,cpucc = <&cpucc_debug>;
|
|
clock-names = "xo_clk_src";
|
|
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
cpufreq_hw: qcom,cpufreq-hw {
|
|
compatible = "qcom,cpufreq-hw";
|
|
reg = <0xf521000 0x1400>;
|
|
reg-names = "freq-domain0";
|
|
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
|
|
clock-names = "xo", "alternate";
|
|
#freq-domain-cells = <1>;
|
|
};
|
|
|
|
bimc_noc: interconnect@0 {
|
|
compatible = "qcom,sa410m-bimc";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
config_noc: interconnect@1 {
|
|
compatible = "qcom,sa410m-config_noc";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
clk_virt: interconnect@2 {
|
|
compatible = "qcom,sa410m-clk_virt";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
sys_noc: interconnect@3 {
|
|
compatible = "qcom,sa410m-sys_noc";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
thermal_zones: thermal-zones { };
|
|
|
|
rpm_msg_ram: memory@045f0000 {
|
|
compatible = "qcom,rpm-msg-ram";
|
|
reg = <0x45f0000 0x7000>;
|
|
};
|
|
|
|
apcs_glb: mailbox@0f111000 {
|
|
compatible = "qcom,scuba-apcs-hmss-global";
|
|
reg = <0xF111000 0x1000>;
|
|
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
rpm-glink {
|
|
compatible = "qcom,glink-rpm";
|
|
interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
|
|
qcom,rpm-msg-ram = <&rpm_msg_ram>;
|
|
mboxes = <&apcs_glb 0>;
|
|
|
|
qcom,rpm_glink_ssr {
|
|
qcom,glink-channels = "glink_ssr";
|
|
// qcom,notify-edges = <&glink_adsp>;
|
|
};
|
|
};
|
|
|
|
tcsr_mutex_block: syscon@00340000 {
|
|
compatible = "syscon";
|
|
reg = <0x340000 0x20000>;
|
|
};
|
|
|
|
tcsr_mutex: hwlock {
|
|
compatible = "qcom,tcsr-mutex";
|
|
syscon = <&tcsr_mutex_block 0 0x1000>;
|
|
#hwlock-cells = <1>;
|
|
};
|
|
|
|
smem: qcom,smem {
|
|
compatible = "qcom,smem";
|
|
memory-region = <&smem_region>;
|
|
hwlocks = <&tcsr_mutex 3>;
|
|
};
|
|
|
|
qcom,glinkpkt {
|
|
compatible = "qcom,glinkpkt";
|
|
|
|
qcom,glinkpkt-at-mdm0 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DS";
|
|
qcom,glinkpkt-dev-name = "at_mdm0";
|
|
};
|
|
|
|
qcom,glinkpkt-data40-cntl {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA40_CNTL";
|
|
qcom,glinkpkt-dev-name = "smdcntl8";
|
|
};
|
|
|
|
qcom,glinkpkt-data1 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA1";
|
|
qcom,glinkpkt-dev-name = "smd7";
|
|
};
|
|
|
|
qcom,glinkpkt-data4 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA4";
|
|
qcom,glinkpkt-dev-name = "smd8";
|
|
};
|
|
|
|
qcom,glinkpkt-data11 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA11";
|
|
qcom,glinkpkt-dev-name = "smd11";
|
|
};
|
|
};
|
|
|
|
qcom,smp2p-modem {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <435>, <428>;
|
|
interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&apcs_glb 14>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <1>;
|
|
|
|
modem_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
modem_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
|
|
qcom,entry-name = "ipa";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
/* ipa - inbound entry from mss */
|
|
smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
|
|
qcom,entry-name = "ipa";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
qcom,smp2p-adsp {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <443>, <429>;
|
|
interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&apcs_glb 10>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <2>;
|
|
|
|
adsp_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
adsp_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
qcom,sps {
|
|
compatible = "qcom,msm-sps-4k";
|
|
qcom,pipe-attr-ee;
|
|
};
|
|
|
|
qnand_1: nand@0x4840000 {
|
|
compatible = "qcom,msm-nand";
|
|
reg = <0x4840000 0x1000>,
|
|
<0x4844000 0x1c000>;
|
|
reg-names = "nand_phys",
|
|
"bam_phys";
|
|
qcom,reg-adjustment-offset = <0x4000>;
|
|
interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "bam_irq";
|
|
clock-names = "core_clk";
|
|
clocks = <&rpmcc RPM_SMD_QPIC_CLK>;
|
|
|
|
//interconnects = <&system_noc MASTER_QPIC &mc_virt SLAVE_EBI1>;
|
|
interconnect-names = "nand-ddr";
|
|
qcom,msm-bus,name = "qpic_nand";
|
|
qcom,msm-bus,num-cases = <2>;
|
|
qcom,msm-bus,num-paths = <1>;
|
|
qcom,msm-bus,vectors-KBps =
|
|
<0 0>,
|
|
/* Voting for max b/w on PNOC bus for now */
|
|
<1057800 725760>;
|
|
|
|
iommus = <&apps_smmu 0x100 0x3>;
|
|
qcom,iommu-dma = "bypass";
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhc_1: sdhci@4744000 {
|
|
status = "disabled";
|
|
|
|
compatible = "qcom,sdhci-msm-v5";
|
|
reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
|
|
reg-names = "hc", "cqhci";
|
|
|
|
interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hc_irq", "pwr_irq";
|
|
|
|
bus-width = <8>;
|
|
non-removable;
|
|
supports-cqe;
|
|
|
|
no-sd;
|
|
no-sdio;
|
|
qcom,restore-after-cx-collapse;
|
|
|
|
mmc-ddr-1_8v;
|
|
mmc-hs200-1_8v;
|
|
mmc-hs400-1_8v;
|
|
mmc-hs400-enhanced-strobe;
|
|
|
|
cap-mmc-hw-reset;
|
|
|
|
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
|
|
<&gcc GCC_SDCC1_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
|
|
|
|
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
|
|
qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x00010800 0x80040868>;
|
|
|
|
/* Add dt entry for gcc hw reset */
|
|
//resets = <&gcc GCC_EMMC_BCR>;
|
|
//reset-names = "core_reset";
|
|
|
|
iommus = <&apps_smmu 0xC0 0x0>;
|
|
qcom,iommu-dma = "bypass";
|
|
|
|
qos0 {
|
|
mask = <0x0f>;
|
|
vote = <44>;
|
|
};
|
|
|
|
qcom_qseecom: qseecom@c1700000 {
|
|
compatible = "qcom,qseecom";
|
|
memory-region = <&qseecom_mem>;
|
|
qseecom_mem = <&qseecom_mem>;
|
|
qseecom_ta_mem = <&qseecom_ta_mem>;
|
|
user_contig_mem = <&user_contig_mem>;
|
|
qcom,hlos-num-ce-hw-instances = <1>;
|
|
qcom,hlos-ce-hw-instance = <0>;
|
|
qcom,qsee-ce-hw-instance = <0>;
|
|
qcom,disk-encrypt-pipe-pair = <2>;
|
|
qcom,no-clock-support;
|
|
qcom,appsbl-qseecom-support;
|
|
qcom,commonlib64-loaded-by-uefi;
|
|
qcom,qsee-reentrancy-support = <2>;
|
|
};
|
|
};
|
|
|
|
#include "sa410m-stub-regulators.dtsi"
|
|
|
|
#include "scuba-thermal.dtsi"
|
|
|
|
&thermal_zones {
|
|
wlan {
|
|
thermal-sensors = <&tsens0 1>;
|
|
};
|
|
|
|
cpuss-0 {
|
|
thermal-sensors = <&tsens0 2>;
|
|
trips {
|
|
cpu-0-2-config {
|
|
temperature = <115000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpuss-1 {
|
|
thermal-sensors = <&tsens0 3>;
|
|
trips {
|
|
cpu-1-3-configs {
|
|
temperature = <115000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdm-0 {
|
|
thermal-sensors = <&tsens0 4>;
|
|
trips {
|
|
mdm0-cx-mon {
|
|
temperature = <105000>;
|
|
};
|
|
|
|
mdm0_emer_mon: mdm0-emer-mon {
|
|
temperature = <125000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
/delete-node/ mdm0-cx-cdev0;
|
|
/delete-node/ mdm0-cx-cdev2;
|
|
|
|
mdm0-cx-cdev1 {
|
|
cooling-device = <&modem_proc 1 1>;
|
|
};
|
|
|
|
mdm0-emer-cdev0 {
|
|
trip = <&mdm0_emer_mon>;
|
|
cooling-device = <&modem_proc 3 3>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdm-1 {
|
|
thermal-sensors = <&tsens0 5>;
|
|
trips {
|
|
mdm1-cx-mon {
|
|
temperature = <105000>;
|
|
};
|
|
|
|
mdm1_emer_mon: mdm1-emer-mon {
|
|
temperature = <125000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
/delete-node/ mdm1-cx-cdev0;
|
|
/delete-node/ mdm1-cx-cdev2;
|
|
|
|
mdm1-cx-cdev1 {
|
|
cooling-device = <&modem_proc 1 1>;
|
|
};
|
|
|
|
mdm1-emer-cdev0 {
|
|
trip = <&mdm1_emer_mon>;
|
|
cooling-device = <&modem_proc 3 3>;
|
|
};
|
|
};
|
|
};
|
|
|
|
video {
|
|
thermal-sensors = <&tsens0 6>;
|
|
};
|
|
|
|
hm-center {
|
|
thermal-sensors = <&tsens0 7>;
|
|
};
|
|
|
|
/delete-node/ gpu;
|
|
/delete-node/ camera;
|
|
};
|
|
|
|
#include "msm-arm-smmu-sa410m.dtsi"
|
|
#include "sa410m-pinctrl.dtsi"
|
|
#include "monaco-gdsc.dtsi"
|
|
#include "sa410m-qupv3.dtsi"
|
|
#include "sa410m-dma-heap.dtsi"
|
|
#include "sa410m-pcie.dtsi"
|
|
|
|
&gcc_emac0_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_pcie_0_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_usb30_prim_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_turing_mmu_tbu1_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_turing_mmu_tbu0_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&qupv3_se4_2uart {
|
|
status = "ok";
|
|
};
|